JP3382907B2 - Semiconductor test circuit and test equipment - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test circuit, and more particularly, to a semiconductor test circuit for testing the operation of each amplifier in a semiconductor integrated circuit having a plurality of amplifiers whose gains can be variably controlled by digital signals. The present invention relates to a test device for performing a test in the semiconductor test circuit.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit having a plurality of amplifiers integrally, there are cases in which the gain of each amplifier is variably controlled by a digital signal. In such a semiconductor integrated circuit, a correct digital signal is input to each amplifier, and a test is required to test whether or not the amplifier is operating with a gain corresponding to the input digital signal. As such a test method, the test method shown in FIG. 7 has been conventionally used. In FIG. 7, reference numeral 1 denotes a semiconductor integrated circuit to be tested, which includes a plurality of amplifiers AMP1 to AMPm for amplifying signals input from input terminals IN1 to INm and outputting the amplified signals from output terminals OUT1 to OUTm, respectively. Of the gain control signals GSEL1 to GS, which are N-bit digital signals, to the amplifiers AMP1 to AMPm, respectively.
A logic circuit section CLB that outputs ELm is built in, and the amplifiers AMP1 to AMPm are set to gains corresponding to the digital values of the input gain control signals GSEL1 to GSELm, respectively.

In such a semiconductor integrated circuit, abnormality of the amplifier itself rarely occurs, but abnormality occurs in the logic circuit section CLB which outputs the gain control signals GSEL1 to GSELm to each amplifier, and the gain control signal GSEL1. There is an increasing demand to test that abnormalities occur in gain switching in each amplifier without correctly outputting ~ GSELm. In such a test,
A predetermined voltage VT is input to the input terminal INx of the amplifier AMPx (x is 1 to m) to be tested, and the LSI tester 10 is connected so as to measure the voltage VD of the output terminal OUTx of the amplifier AMPx. , The gain control signal GSELx corresponding to the preset gain is input to the amplifier AMPx from the logic circuit section CLB, and the gain of the amplifier AMPx becomes the set gain based on the voltage of the input terminal INx and the output terminal OUTx. To test. Then, this test is performed plural times by switching the gain setting to test whether the gain switching operation is normal.

[0004]

However, in such a test method, the input voltage source or voltmeter of the LSI tester is connected to or disconnected from each input terminal and output terminal of the amplifier AMPx to be tested. There is a problem that work is required and the work accompanying the test becomes complicated. Further, in the test, while switching the gains of the plurality of amplifiers AMPx by digital signals, the input terminal INx and the output terminal OUTx are switched.
The number of test steps for each amplifier is required because it is necessary to calculate each amplifier voltage individually, calculate the gain of each amplifier, and compare it with the set gain to judge the quality of the amplifier. If the number of amplifiers built in the semiconductor integrated circuit is large, the number of test steps for the semiconductor integrated circuit becomes enormous and the test time becomes long.

The main object of the present invention is to simplify the incidental work at the time of the gain switching test, shorten the test time required for each amplifier, and shorten the test time for the semiconductor integrated circuit. The present invention provides a semiconductor test circuit and a test device capable of performing the test.

[0006]

A semiconductor test circuit according to the present invention comprises a plurality of amplifiers having variable gains for amplifying and outputting input signals, and a gain control signal for controlling the gains of the plurality of amplifiers. In a semiconductor integrated circuit including a logic circuit section that outputs a signal, a switch provided on the output side of each of the amplifiers for selecting and extracting the output of each of the amplifiers, and a switch for extracting the output of the plurality of amplifiers by the switch. A comparator for comparing the levels of the output of one amplifier and the output of the other one amplifier; and an output holding means for holding the output of the comparator and outputting it to a test output terminal provided in the semiconductor integrated circuit. Is characterized by.

Another semiconductor test circuit of the present invention is
In a semiconductor integrated circuit, comprising: a plurality of amplifiers, each of which has a variable gain for amplifying and outputting an input signal, and a logic circuit unit, which outputs a gain control signal for controlling the gains of the plurality of amplifiers, A switch provided on the output side of each of the amplifiers for selecting and extracting the output of each of the amplifiers and the level of the output of one amplifier extracted from the plurality of amplifiers by the switch and the output of another amplifier are compared. Comparator, an output of the comparator, an exclusive OR gate that takes an exclusive OR of the expected value signal output from the logic circuit unit, and an output holding unit that holds the output of the exclusive OR gate And latch means for using the output of the output holding means as a set input and a reset signal from the logic circuit section as a reset input. And wherein the door.

Here, the logic circuit section supplies a gain control signal for controlling the gain of the one amplifier and the gain of the other amplifier to different gains respectively from the one amplifier and the other amplifier. It is configured to output to. Further, a configuration in which an offset adjusting circuit for making a difference in level at both the input terminals is connected to each of the input terminal of the output of the one amplifier of the comparator and the input terminal of the output of the other one amplifier. And

Further, the test apparatus of the present invention comprises means for inputting input signals of the same level to a plurality of amplifiers provided in the semiconductor test circuit of the present invention, and an output of the test output terminal as an expected value. And a gain control signal corresponding to the expected value data is output to the logic circuit unit. Further, another test apparatus of the present invention detects the output level of the test output terminal, and means for inputting input signals of the same level to a plurality of amplifiers provided in the semiconductor test circuit of the present invention. Means for causing the logic circuit section to output a gain control signal corresponding to the expected value signal, and outputting the reset signal that changes to a high level at the start of the test.

According to the present invention, one of a plurality of amplifiers
By inputting gain control signals with different gains to one amplifier and the other one amplifier, comparing the outputs of these amplifiers with a comparator, and comparing the comparison result with the expected data. , It becomes possible to test whether the gain control signal switching operation for each amplifier is normal or abnormal. Alternatively,
It is possible to test whether the switching operation of the gain control signal for each amplifier is normal or abnormal by arranging the latch means to be set according to the comparison result of the converter and checking the output of the latch means. .

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a semiconductor test circuit according to a first embodiment of the present invention. Semiconductor integrated circuit 1
Includes a plurality of amplifiers AMP1 to AMPm,
Each of the amplifiers AMP1 to AMPm has an input terminal IN1.
To INm are amplified and the output terminal OU is amplified.
It is configured to output to T1 to OUTm. Although detailed description is omitted, each of the amplifiers AMP1 to AMPm is configured such that its gain can be variably controlled by adjusting the resistance value of a passive element provided in the amplifier, for example, a variable resistor. Further, the semiconductor integrated circuit 1 includes an N-bit (N is an arbitrary number) gain control signal G for controlling the gain of each of the amplifiers AMP1 to AMPm.
Logic circuit unit CLB for generating SEL1 to GSELm
have. The logic circuit unit CLB is configured to operate the amplifiers AMP1 to AMPm according to a signal input from the outside.
Is set, and the gain control signals GSEL1 to GSE of digital values corresponding to the set gain are set.
Lm is output to each of the amplifiers AMP1 to AMPm. The configurations of the amplifiers AMP1 to AMPm and the logic circuit section CLB are the same as the conventional circuit configuration.

Further, in the semiconductor integrated circuit 1, the output terminals OUT1 to OU of the amplifiers AMP1 to AMPm are provided.
Switches SW1 to SW are provided at the output terminals connected to Tm, respectively.
Each end of m is connected. Also, each of the switches S
W1 to SWm may be any combination, for example, in this embodiment, odd-numbered amplifiers AMP1, AMPm-1,
The other ends of the switches SW1, SWm-1, ... Are connected to each other, and the connection ends are connected to the positive input terminal of the comparator CMP. In addition, even-numbered amplifiers AMP2, A
The other ends of the switches SW2, SWm, ... Of MPm, ... Are connected to each other, and the connection end is connected to the negative input terminal of the comparator CMP. In addition, the switches SW1 to SW
m is configured to be ON / OFF controlled by a control signal (not shown) generated by the logic circuit section CLB, and the switches SW1 to SWm are OF in normal operation.
When the test is performed, the odd-numbered and even-numbered switches SW1 and SW2, ..., SWm−1 and SWm adjacent to each other are paired and controlled so as to be simultaneously turned on.

In the comparator CMP, the odd-numbered and even-numbered two selected by the switches SW1 to SWm are used.
The output potentials of the two amplifiers are compared and the comparator CMP
When the positive input of is higher than the negative input, the output of the comparator CMP is High level, and when the positive input of the comparator CMP is lower than the negative input, the output of the comparator CMP is Low level. Become. The offset adjusting circuits OS1 and OS2 are connected to the positive and negative inputs of the comparator CMP, respectively. This is because when the gain control signals GSEL1 or GSEL2 of the two amplifiers under test have failed and become equal signals, the outputs of the two amplifiers have the same potential and the positive and negative inputs of the comparator CMP are equal. This is for the purpose of ensuring that the failure can be detected even in this case. This offset adjustment circuit OS1,
OS2 is controlled by a signal created in the logic circuit unit CLB. Further, a D-type flip-flop D-FF to which the output of the comparator CMP is input is provided, and the clock input of the D-type flip-flop D-FF is connected to the signal generated by the logic circuit section CLB. . The output of the D-type flip-flop D-FF is connected to the TEST output terminal OUT0 provided in the semiconductor integrated circuit 1.

Next, the test operation in the semiconductor test circuit of FIG. 1 will be described with reference to the timing chart of FIG. Figure 2
The timing diagram of is a case where the gain control signals GSEL1 and GSEL2 from the logic circuit portion CLB are 3 bits and the amplifier AMP1 and the amplifier AMP2 are being tested. At this time, the switches SW1 and SW2 are turned on by the control signal from the logic circuit unit CLB, the output of the amplifier AMP1 is connected to the positive input of the comparator CMP, and the output of the amplifier AMP2 is connected to the comparator C.
It is set to be connected to the negative input of MP. Further, at the input terminals IN1 and IN2 of each amplifier, a voltage VT of a predetermined potential lower than the reference voltage VREF from the LSI tester 10 and having the same potential is applied to the LS.
It is input from the I tester 10. Further, the LS output terminal OUT0 of the semiconductor integrated circuit 1 has the LS
The TEST output terminal O is provided in the I tester 10.
Expected value data 1 consisting of a preset time-dependent change pattern of the voltage output from the UT0
A collation circuit 12 that collates with 1 and outputs a normal (PASS) signal when both match and an abnormal (FAIL) signal when both do not match is connected.

After making the above settings, first, in the logic circuit section CLB, the gain control signals GSEL1 and GSE are set based on the preset time-dependent change pattern of the gain.
L2 is input to each of the amplifiers AMP1 and AMP2. Here, GSEL1 = “001” and GSEL2 = “000”.
Is set to. Therefore, the amplifiers AMP1, AMP
When 2 is normal, the gain of the amplifier AMP1 is higher than that of the amplifier AMP2.
The output of 1 has a higher potential than the output of the amplifier AMP2.
That is, the positive input of the comparator CMP has a higher potential than the negative input, and the output of the comparator CMP becomes a high level output. Since the output of the comparator CMP is latched by the D-type flip-flop D-FF and output to the TEST output terminal OUT0 of the semiconductor integrated circuit 1, T
High level is output to the EST output terminal OUT0.

Next, the gain control signals GSEL1, GSE
LSEL is switched and GSEL1 = "010" and GSEL
2 = “001” is set. Also at this time, each amplifier A
When MP1 and AMP2 are normal, the output of the amplifier AMP1 has a higher potential than the output of the amplifier AMP2, and TE
A high level is output to the ST output terminal OUT0. Next, GSEL1 = "100" and GSEL2 = "0".
11 ”is set, but similarly, H is set to the TEST output terminal.
The high level is output.

Next, GSEL1 = “000” and GSEL
2 = “001” is set. At this time, the amplifier AMP
When 1 and AMP2 are normal, the gain of the amplifier AMP1 is lower than the gain of the amplifier AMP2, and the output of the amplifier AMP1 has a lower potential than the output of the amplifier AMP2. That is, the potential of the positive input of the comparator CMP becomes lower than that of the negative input, and the output of the comparator CMP becomes L.
A low level is output, and a low level is output to the TEST output terminal. Similarly, GSEL1 = "001" and GSEL2 = "010", and GSEL1 = "01".
1 ”and GSEL2 =“ 100 ”are set, but in both cases, the Low level is output to the TEST output terminal.

Then, the time-varying output from the TEST output terminal OUT0 is collated by the collation circuit 12 of the LSI tester 10 with the expected value data 11 preset in correspondence with the gain control signal. This makes it possible to detect whether the output of each amplifier is normal or abnormal. The timing diagram of FIG. 2 shows the case where the output of the TEST output terminal OUT0 is collated with the expected value data 11, which confirms that the gain control signal is operating correctly.

On the other hand, when the output level of the TEST output terminal OUT0 is output as a level different from each of the above High and Low levels, the amplifiers AMP1 and A
Any gain of MP2 does not become the gain corresponding to the gain control signal. FIG. 3 is an example thereof, and shows a case where an abnormality occurs in the gain control signals for the amplifier AMP1 and the amplifier AMP2. Here, GSEL1
This is the case where the most significant bit (third bit) of has failed to "1". In this case, the output potentials of the amplifiers AMP1 and AMP2 are as shown in the figure, and GSEL1 = “000” and G
SEL2 = “001”, GSEL1 = “001” and GS
EL2 = “010”, GSEL1 = “011” and GSE
When L2 = “100” is set, the output of the TEST output terminal OUT0 must be High level, which is Low level output.
Therefore, when the output of the TEST output terminal OUT0 that changes with time is collated with the expected value data 11 preset in correspondence with the gain control signal in the collation circuit 12 of the LSI tester 10, FIG. In the timing diagram, the output of the TEST output terminal OUT0 is the expected value data 1
1 is not checked, and it is detected that the gain control signal is abnormal.

The offset adjusting circuits OS1 and OS2 are connected to the positive and negative inputs of the comparator CMP, respectively. This offset adjustment circuit OS1, OS
2 is a gain control signal GSEL1> GSEL2,
That is, when the positive input side of the comparator CMP is higher than the negative input side, the offset adjusting circuit OS on the negative input side is provided.
The control signal from the logic circuit unit CLB to
The level is set so that the potential of the negative input of the comparator CMP rises. However, the level of this offset must be below the minimum potential difference generated at the outputs of the amplifiers AMP1 and AMP2. By providing an offset level to the input of the comparator CMP in this way, a failure occurs and GSEL1 = GSEL2, and even when the outputs of the amplifiers AMP1 and AMP2 become equal, the potential of the negative input is higher than that of the positive input of the comparator CMP. As the output becomes higher, the output of the comparator CMP becomes the Low level, which is different from the expected value, and an abnormality is detected. Similarly, when GSEL1 <GSEL2, that is, when the positive input side of the comparator CMP becomes lower than the negative input side, the offset adjustment circuit OS1 on the positive input side
The control signal from the logic circuit section CLB to the high level is set to High level, and setting is made so that the potential of the positive input of the comparator CMP rises. Even in this case, due to the failure, GSEL
1 = GSEL2 and even when the outputs of the amplifiers AMP1 and AMP2 are equal, the potential of the positive input is higher than the negative input of the comparator CMP,
Output becomes High level, which is different from the expected value, and an abnormality is detected.

In FIG. 4, GSEL1 and GSEL2 are 3 bi.
In the case of t, the level H (High) of the output of the TEST output terminal when each bit has a failure of “0” or “1”
Although h) and L (Low) are shown, the output of the TEST output terminal is different from that of a normal product even if any bit of the gain control signal fails, and the gain control signal is switched. It can be detected that the operation is abnormal. The same applies when the gain control signal is 4 bits or more.

In the above embodiment, the amplifier AMP1
The amplifier AMP2 has been described above, but a pair of amplifiers is configured for the other amplifiers, and the same test as described above is performed on the two amplifiers that configure the pair, so that the gain of the gain control signal in the logic circuit unit CLB is increased. It is possible to test whether the switching operation is normal or abnormal.

FIG. 5 is a block diagram of the semiconductor test circuit of the second embodiment of the present invention, showing an example in which the output of the TEST output terminal is further improved. Where the first
The same parts as those of the embodiment of FIG. In this embodiment, an exclusive OR gate XOR is inserted between the comparator CMP and the D-type flip-flop D-FF, and the output of the comparator CMP is input to one input of the exclusive OR gate XOR. It is connected. An expected value signal generated by the logic circuit section CLB is connected to the other input of the exclusive OR gate XOR. Further, the output of the D-type flip-flop D-FF is connected to the set input of an SR latch circuit SR-L composed of a set / reset flip-flop, and the reset input of the SR latch circuit SR-L is connected to the set input. The reset signal from the logic circuit unit CLB is input. The reset signal is a signal that changes from Low to High at the start of the test.

In this second embodiment, the same output is output from the comparator CMP by testing the amplifiers AMP1 to AMPm as in the first embodiment. Then, this output is exclusive ORed with the expected value signal from the logic circuit unit CLB in the exclusive OR gate XOR. Here, when the expected value signal and the output of the comparator CMP are equal, that is, when the normal operation is performed, the output of the exclusive OR gate XOR is L.
ow level, but expected value signal and comparator CMP
When the outputs of the two are different, that is, when there is an abnormality, the output of the exclusive OR gate XOR becomes the high level. Further, the output of the exclusive OR gate XOR is held by the D-type flip-flop D-FF and then connected to the set input of the SR latch circuit SR-L. A reset signal from the logic circuit unit CLB is input to the reset input of the SR latch circuit SR-L. This reset signal is
As described above, since the signal changes from Low to High at the start of the test, in the case of a non-defective product, the output of the D-type flip-flop D-FF does not become High level, and therefore the output of the SR latch circuit SR-L is , Low remains. On the other hand, in the case of an abnormality, the output of the comparator CMP and the expected value signal generated by the logic circuit unit CLB are different, so the output of the D-type flip-flop D-FF becomes High, and this output is held thereafter. .

Therefore, as described in the first embodiment, the test is performed while changing the combination of the gain control signals GSEL with time, and finally the SR latch circuit S
The potential VD of the output of RL, that is, the output of the TEST output terminal OUT0 is measured to determine whether the output is Low or Hi.
It is possible to detect whether all the gain switching operations are normal or whether some abnormalities have occurred, only by confirming whether the gain is gh.

[0026]

As described above, according to the present invention, one of a plurality of gain-controlled amplifiers provided in a semiconductor integrated circuit has a gain different from that of another amplifier. By inputting a control signal, comparing the output of these amplifiers with a comparator, and comparing the comparison result with the expected data, the gain control signal switching operation for each amplifier is normal or abnormal. It will be possible to test if there is. Alternatively, by setting the latch means according to the comparison result of the converter and confirming the output of the latch means,
It is possible to test whether the gain control signal switching operation for each amplifier is normal or abnormal. As a result, in the present invention, the gain switching operation of the amplifier can be tested as a logic function test, so that the test process can be simplified and the test time can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram of a semiconductor test circuit according to a first embodiment of the present invention.

FIG. 2 is a timing diagram when the gain control signal switching operation is normal in the first embodiment.

FIG. 3 is a timing chart when the gain control signal switching operation in the first embodiment is abnormal.

FIG. 4 is a diagram showing an output value when a failure occurs in each bit.

FIG. 5 is a block diagram of a semiconductor test circuit according to a second embodiment of the present invention.

FIG. 6 is a timing diagram when the gain control signal switching operation is normal in the second embodiment.

FIG. 7 is a block diagram of an example of a conventional semiconductor test circuit.

[Explanation of symbols]

1 Semiconductor integrated circuit 10 LSI tester 11 Expected value data 12 Matching circuit AMP1 to AMPm amplifier IN1-INm input terminals OUT0 TEST output terminal OUT1 to OUTm output terminals CLB logic circuit SW1 to SWm switches CMP comparator D-FF D-type flip-flop XOR Exclusive OR gate GSEL1 to GSELm gain control signal

Claims (6)

(57) [Claims] 1. A semiconductor integrated circuit comprising: a plurality of amplifiers having variable gains for amplifying and outputting input signals; and a logic circuit section for outputting a gain control signal for controlling the gains of the plurality of amplifiers. A switch provided on the output side of each of the amplifiers for selecting and extracting the output of each of the amplifiers, the output of one amplifier extracted by the switch from the plurality of amplifiers, and the output of the other amplifier A comparator that compares each level of
A semiconductor test circuit, comprising: output holding means for holding the output of the comparator and outputting the output to a test output terminal provided in the semiconductor integrated circuit. 2. A semiconductor integrated circuit comprising: a plurality of amplifiers having variable gains for amplifying and outputting an input signal; and a logic circuit section for outputting a gain control signal for controlling the gains of the plurality of amplifiers. A switch provided on the output side of each of the amplifiers for selecting and extracting the output of each of the amplifiers, the output of one amplifier extracted by the switch from the plurality of amplifiers, and the output of the other amplifier A comparator that compares each level of
An exclusive OR gate that takes the exclusive OR of the output of the comparator and the expected value signal output from the logic circuit unit; output holding means that holds the output of the exclusive OR gate; and the output A semiconductor test circuit, comprising: a latch means for receiving an output of the holding means as a set input and a reset signal from the logic circuit section as a reset input. 3. The logic circuit section supplies a gain control signal for controlling the one amplifier and the other amplifier to different gains to the one amplifier and the other amplifier, respectively. The semiconductor test circuit according to claim 1, wherein the semiconductor test circuit outputs. 4. An offset adjusting circuit for causing a difference in level between the input terminals of the output of the one amplifier and the input terminal of the output of the other one amplifier of the comparator, respectively. The semiconductor test circuit according to claim 1, wherein the semiconductor test circuit is connected. 5. A device for testing the semiconductor test circuit according to claim 1, comprising means for inputting input signals of the same level to the plurality of amplifiers, A test apparatus for a semiconductor test circuit, comprising: means for comparing an output of a test output terminal with expected value data, and causing the logic circuit section to output a gain control signal corresponding to the expected value data. 6. A device for testing the semiconductor test circuit according to claim 2, wherein the plurality of amplifiers receives input signals of the same level, Means for detecting an output level of a test output terminal, causing the logic circuit section to output a gain control signal corresponding to the expected value signal, and the reset signal changing to a high level at the start of a test. A test device for a semiconductor test circuit characterized by outputting.