JP2001153931A - Semiconductor testing circuit and testing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit for testing the operation of switching gain control signals, which controls the gain of each amplifier, in a semiconductor integrated circuit provided with a plurality of gain-controllable amplifiers, and to shorten the test time. SOLUTION: A semiconductor integrated circuit 1 provided with a plurality of gain-controllable amplifiers AMP1-AMPm to amplify and output inputted signals and a logic circuit part CLB to output gain control signals GSEL1- GSELm for controlling the gains of the plurality of amplifiers AMP1-AMPm is provided with switches SW1-SWm for selecting and extracting the outputs of the amplifiers AMP1-AMPm, a comparator CMP to compare the output of one amplifier extracted by each of the switches SW1-SWm with each output level of another amplifier, and an output holding means (D-type flip-flop) D-FF to hold and output the output of the compactor CMP to a test output terminal OUT0. By collating the output of the comparator CMP with expected-value data 11, it is possible to test whether the operation of switching gain control signals to each amplifier is normal or anomalous.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test circuit, and more particularly, to a semiconductor test circuit for testing the operation of each amplifier in a semiconductor integrated circuit having a plurality of amplifiers whose gain can be variably controlled by digital signals. And a test apparatus for performing a test in the semiconductor test circuit.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit integrally including a plurality of amplifiers, a configuration may be adopted in which the gain of each amplifier is variably controlled by a digital signal. In such a semiconductor integrated circuit, a test is required to test whether a correct digital signal is input to each amplifier and whether the amplifier is operating with a gain corresponding to the input digital signal. Conventionally, a test method shown in FIG. 7 is used as such a test method. In FIG. 7, reference numeral 1 denotes a semiconductor integrated circuit to be tested, which includes a plurality of amplifiers AMP1 to AMPm for amplifying signals input from input terminals IN1 to INm and outputting the amplified signals from output terminals OUT1 to OUTm. AMP1 to AMPm, the gain control signals GSEL1 to GS each comprising an N-bit digital signal.
A logic circuit section CLB that outputs ELm is built in, and each of the amplifiers AMP1 to AMPm is set to have a gain corresponding to the digital value of the gain control signal GSEL1 to GSELm that is input.

In such a semiconductor integrated circuit, although the abnormality of the amplifier itself rarely occurs, an abnormality occurs in the logic circuit section CLB which outputs the gain control signals GSEL1 to GSELm to each amplifier, and the gain control signal GSEL1 There is an increasing demand for testing whether an error occurs in gain switching in each amplifier without correctly outputting .about.GSELm. For such tests,
A predetermined voltage VT is input to an input terminal INx of an amplifier AMPx (x is 1 to m) to be tested, and an LSI tester 10 is connected so as to measure a voltage VD of an output terminal OUTx of the amplifier AMPx. Then, a gain control signal GSELx corresponding to a preset gain is input from the logic circuit unit CLB to the amplifier AMPx, and the gain of the amplifier AMPx becomes the set gain based on the voltages of the input terminal INx and the output terminal OUTx. Test if you have. Then, this test is performed a plurality of times by switching the gain setting to test whether the gain switching operation is normal.

[0004]

However, in such a test method, an input voltage source or a voltmeter of an LSI tester is connected to or disconnected from each input terminal and output terminal of the amplifier AMPx to be tested. Work is required, and there is a problem that work accompanying the test becomes complicated. In the test, the gain is switched by a digital signal for each of the plurality of amplifiers AMPx, and the input terminal INx and the output terminal OUTx are switched.
Is required to calculate each amplifier's voltage individually, calculate the gain of each amplifier, and compare this with the set gain to judge the quality of the amplifier. When the number of amplifiers built in the semiconductor integrated circuit is large, the number of test steps for the semiconductor integrated circuit becomes enormous, and the test time is lengthened.

A main object of the present invention is to simplify the additional work in the gain switching test, shorten the test time required for each amplifier, and shorten the test time for a semiconductor integrated circuit. The present invention provides a semiconductor test circuit and a test apparatus that can perform the test.

[0006]

A semiconductor test circuit according to the present invention comprises a plurality of amplifiers having variable gains for amplifying and outputting an input signal, and a gain control signal for controlling the gains of the plurality of amplifiers. And a logic circuit section for outputting the output of each of the amplifiers, and a switch for selecting and extracting the output of each of the amplifiers, A comparator for comparing each level of an output of one amplifier with an output of another amplifier; and output holding means for holding an output of the comparator and outputting the output to a test output terminal provided in the semiconductor integrated circuit. It is characterized by.

Further, another semiconductor test circuit of the present invention comprises:
A semiconductor integrated circuit comprising: a plurality of amplifiers each having a variable gain for amplifying and outputting an input signal; and a logic circuit unit for outputting a gain control signal for controlling the gain of the plurality of amplifiers. And a switch for selecting and extracting the output of each of the amplifiers, and comparing the levels of the output of one amplifier extracted from the plurality of amplifiers with the switches and the output of the other amplifier. A comparator, an exclusive OR gate for performing an exclusive OR of an output of the comparator, and an expected value signal output from the logic circuit unit, and an output holding unit for holding an output of the exclusive OR gate And a latch unit that uses the output of the output holding unit as a set input and a reset signal from the logic circuit unit as a reset input. And wherein the door.

Here, the logic circuit section may control a gain control signal for controlling the one amplifier and the other amplifier to have different gains, respectively, by the one amplifier and the other one amplifier. Output. Also, an offset adjustment circuit for providing a difference in level between the two input terminals to each of the input terminal of the output of the one amplifier of the comparator and the input terminal of the output of the other one amplifier is connected. And

Further, the test apparatus of the present invention comprises: means for inputting an input signal of the same level to a plurality of amplifiers provided in the semiconductor test circuit of the present invention; Means for comparing the expected value data with the logic circuit unit. According to another embodiment of the present invention, there is provided a test apparatus for inputting the same level input signal to a plurality of amplifiers provided in the semiconductor test circuit of the present invention, and detecting an output level of the test output terminal. Means for outputting a gain control signal corresponding to the expected value signal to the logic circuit section, and outputting the reset signal which changes to a high level at the start of a test.

According to the present invention, one of a plurality of amplifiers
By inputting gain control signals with different gains to one amplifier and another amplifier, comparing the outputs of these amplifiers with a comparator, and comparing the comparison result with expected data. This makes it possible to test whether the switching operation of the gain control signal for each amplifier is normal or abnormal. Or,
By setting the latch means based on the comparison result of the converter and confirming the output of the latch means, it is possible to test whether the switching operation of the gain control signal for each amplifier is normal or abnormal. .

[0011]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a semiconductor test circuit according to the first embodiment of the present invention. Semiconductor integrated circuit 1
Has a plurality of amplifiers AMP1 to AMPm,
Each of the amplifiers AMP1 to AMPm has an input terminal IN1.
To INm to amplify the voltage VT inputted to the output terminal OU
It is configured to output to T1 to OUTm. Although the detailed description of each of the amplifiers AMP1 to AMPm is omitted, the gain of the amplifier AMP1 to AMPm can be variably controlled by adjusting the resistance value of a passive element provided in the amplifier, for example, a variable resistor. The semiconductor integrated circuit 1 has an N-bit (N is an arbitrary number) gain control signal G for controlling the gain of each of the amplifiers AMP1 to AMPm.
Logic circuit section CLB that generates SEL1 to GSELm
have. The logic circuit unit CLB is configured to receive the signals from the amplifiers AMP1 to AMPm in response to an externally input signal.
, And gain control signals GSEL1 to GSE1 of digital values corresponding to the set gain.
Lm is output to each of the amplifiers AMP1 to AMPm. The configurations of the amplifiers AMP1 to AMPm and the logic circuit unit CLB are the same as the conventional circuit configuration.

Further, the semiconductor integrated circuit 1 has output terminals OUT1 to OUT of the amplifiers AMP1 to AMPm.
Switches SW1 to SW at output terminals connected to Tm, respectively.
m is connected to one end. Further, each of the switches S
W1 to SWm are arbitrary combinations, for example, in this embodiment, odd-numbered amplifiers AMP1, AMPm-1,
The other ends of the switches SW1, SWm-1,... Are connected to each other, and the connection end is connected to the positive input terminal of the comparator CMP. Also, the even-numbered amplifiers AMP2, A
The other ends of the switches SW2, SWm,... Of MPm,... Are connected to each other, and the connection ends thereof are connected to the negative input terminal of the comparator CMP. The switches SW1 to SW
m is configured to be turned on and off by a control signal (not shown) generated by the logic circuit unit CLB. The switches SW1 to SWm are turned off during normal operation.
.., And SWm-1 and SWm, which are adjacent to each other, are turned on at the same time in a test.

In the comparator CMP, the odd-numbered and even-numbered two selected by the switches SW1 to SWm are used.
The output potentials of the two amplifiers are compared, and the comparator CMP
When the positive input of the comparator CMP has a higher potential than the negative input, the output of the comparator CMP has a high level. When the positive input of the comparator CMP has a lower potential than the negative input, the output of the comparator CMP has a low level. Become. Further, offset adjustment circuits OS1 and OS2 are connected to the positive input and the negative input of the comparator CMP, respectively. This is because if the gain control signals GSEL1 or GSEL2 of the two amplifiers under test fail and become equal, the outputs of the two amplifiers have the same potential, and the positive and negative inputs of the comparator CMP are equal. The potential is set, but in this case as well, it is to ensure that a failure can be detected. This offset adjustment circuit OS1,
OS2 is controlled by a signal generated by the logic circuit unit CLB. Further, a D-type flip-flop D-FF to which an output of the comparator CMP is input is provided, and a clock input of the D-type flip-flop D-FF is connected to a signal generated by the logic circuit unit CLB. . The output of the D-type flip-flop D-FF is connected to a TEST output terminal OUT0 provided in the semiconductor integrated circuit 1.

Next, a test operation in the semiconductor test circuit of FIG. 1 will be described with reference to a timing chart of FIG. FIG.
In the timing chart of FIG. 7, the gain control signals GSEL1 and GSEL2 from the logic circuit unit CLB are 3 bits, and the amplifiers AMP1 and AMP2 are tested. At this time, the switches SW1 and SW2 are turned on by the control signal from the logic circuit unit CLB, the output of the amplifier AMP1 is connected to the positive input of the comparator CMP, and the output of the amplifier AMP2 is
It is set to be connected to the negative input of MP. The input terminals IN1 and IN2 of the amplifiers respectively receive a predetermined voltage lower than the reference voltage VREF from the LSI tester 10 and the same voltage VT as LS.
It is input from the I tester 10. Further, the TEST output terminal OUT0 of the semiconductor integrated circuit 1 has the LS
I tester 10 is provided in the TEST output terminal O
The time-dependent change data of the voltage output from UT0 is converted into expected value data 1 which is a predetermined time-dependent change pattern of the voltage.
A collation circuit 12 is connected to collate with a 1 and output a normal (PASS) signal when the two coincide with each other, and output an abnormal (FAIL) signal when they do not coincide with each other.

After the above settings are made, first, the logic circuit section CLB controls the gain control signals GSEL1 and GSE1 based on a predetermined gain change pattern with time.
L2 is input to each of the amplifiers AMP1 and AMP2. Here, GSEL1 = “001” and GSEL2 = “000”
Is set to Therefore, the amplifiers AMP1 and AMP
2 is normal, the gain of the amplifier AMP1 is higher than the gain of the amplifier AMP2.
1 has a higher potential than the output of the amplifier AMP2.
That is, the potential of the positive input of the comparator CMP becomes higher than that of the negative input, and the output of the comparator CMP becomes a High level output. Since the output of the comparator CMP is latched by the D-type flip-flop D-FF and output to the TEST output terminal OUT0 of the semiconductor integrated circuit 1, T
A high level is output to the EST output terminal OUT0.

Next, gain control signals GSEL1, GSE
By switching L2, GSEL1 = "010" and GSEL
2 = “001” is set. At this time, each amplifier A
When MP1 and AMP2 are normal, the output of the amplifier AMP1 has a higher potential than the output of the amplifier AMP2, and TE
A high level is output to the ST output terminal OUT0. Next, GSEL1 = “100” and GSEL2 = “0”
11 ", and similarly, the TEST output terminal
The high level is output.

Next, GSEL1 = “000” and GSEL1
2 = “001” is set. At this time, the amplifier AMP
1, when AMP2 is normal, the gain of the amplifier AMP1 is lower than the gain of the amplifier AMP2, and the output of the amplifier AMP1 has a lower potential than the output of the amplifier AMP2. That is, the potential of the positive input of the comparator CMP becomes lower than that of the negative input, and the output of the comparator CMP becomes L
The output becomes the low level, and the low level is output to the TEST output terminal. Similarly, GSEL1 = “001” and GSEL2 = “010”, and GSEL1 = “01”
1 ”and GSEL2 =“ 100 ”are set, and both output a low level to the TEST output terminal.

Then, the output that changes with time from the TEST output terminal OUT0 is compared with expected value data 11 set in advance in the matching circuit 12 of the LSI tester 10 in accordance with the gain control signal. This makes it possible to detect the normal or abnormal output of each amplifier. The timing chart of FIG. 2 shows a case where the output of the TEST output terminal OUT0 is collated with the expected value data 11, which confirms that the gain control signal is operating correctly.

On the other hand, when the output level of the TEST output terminal OUT0 is output as a level different from each of the above-mentioned High and Low levels, the amplifiers AMP1 and A2 are output.
Any one of the gains of MP2 does not become the gain corresponding to the gain control signal. FIG. 3 is an example of such a case, and shows a case where an abnormality has occurred in the gain control signals for the amplifiers AMP1 and AMP2. Here, GSEL1
Is the case where the most significant bit (third bit) has failed to “1”. In this case, the output potentials of the amplifiers AMP1 and AMP2 are as shown in FIG.
SEL2 = “001”, GSEL1 = “001” and GS
EL2 = “010”, GSEL1 = “011” and GSE
Where L2 = “100” is set, where the output of the TEST output terminal OUT0 must be at the high level, the output is at the low level.
For this reason, when the output that changes over time of the TEST output terminal OUT0 is compared with the expected value data 11 set in advance in the matching circuit 12 of the LSI tester 10 corresponding to the gain control signal, FIG. In the timing chart, the output of the TEST output terminal OUT0 is the expected value data 1
It is not collated with 1, and it is detected that the gain control signal is abnormal.

The offset adjustment circuits OS1 and OS2 are connected to the positive and negative inputs of the comparator CMP, respectively. The offset adjustment circuits OS1, OS
2 is the case where the gain control signal GSEL1> GSEL2,
In other words, when the positive input side of the comparator CMP is higher than the negative input side, the offset adjustment circuit OS on the negative input side
2 from the logic circuit unit CLB to High
Level so that the potential of the negative input of the comparator CMP rises. However, the level of this offset must be lower than the minimum potential difference generated at the outputs of the amplifiers AMP1 and AMP2. By giving an offset level to the input of the comparator CMP in this way, even if a failure occurs and GSEL1 = GSEL2 and the outputs of the amplifiers AMP1 and AMP2 become equal, the potential of the negative input of the comparator CMP is higher than that of the positive input of the comparator CMP. As a result, the output of the comparator CMP becomes Low level, which differs from the expected value, and it is detected that the output is abnormal. Similarly, when GSEL1 <GSEL2, that is, when the positive input side of the comparator CMP is lower than the negative input side, the offset adjustment circuit OS1 on the positive input side
The control signal from the logic circuit unit CLB to the high level is set to a high level, and setting is performed so that the potential of the positive input of the comparator CMP increases. Even in this case, GSEL
1 = GSEL2, and even when the outputs of the amplifiers AMP1 and AMP2 become equal, the potential of the positive input becomes higher than the negative input of the comparator CMP, and the comparator CMP
Becomes high level, which is different from the expected value, and it is detected that the output is abnormal.

FIG. 4 shows that GSEL1 and GSEL2 are 3 bi
In the case of t, when each bit fails to “0” or “1”, the output level H (Hig
h) and L (Low), which indicates that even if any bit of the gain control signal fails, the output of the TEST output terminal becomes different from that of a normal product, and the gain control signal is switched. It can be detected that the operation is abnormal. The same applies to the case where the gain control signal is 4 bits or more.

In the above embodiment, the amplifier AMP1
And the amplifier AMP2, the other amplifiers constitute a pair of amplifiers, and a test similar to the above is performed on the two amplifiers constituting the pair to obtain the gain of the gain control signal in the logic circuit unit CLB. It is possible to test whether the switching operation is normal or abnormal.

FIG. 5 is a block diagram of a semiconductor test circuit according to the second embodiment of the present invention, showing an example in which the output of the TEST output terminal is further improved. Here, the first
The same parts as those in the configuration of FIG. In this embodiment, an exclusive OR gate XOR is interposed between the comparator CMP and the D-type flip-flop D-FF, and the output of the comparator CMP is connected to one input of the exclusive OR gate XOR. It is connected. The other input of the exclusive OR gate XOR is connected to an expected value signal generated by the logic circuit unit CLB. Further, the output of the D-type flip-flop D-FF is connected to the set input of an SR latch circuit SR-L composed of a set / reset flip-flop, and the reset input of this SR latch circuit SR-L is A reset signal is input from the logic circuit unit CLB. This reset signal changes from low to high at the start of the test.

In the second embodiment, the same output is output from the comparator CMP by testing the amplifiers AMP1 to AMPm as in the first embodiment. This output is exclusive-ORed with the expected value signal from the logic circuit unit CLB in the exclusive-OR gate XOR. Here, when the expected value signal is equal to the output of the comparator CMP, that is, when the normal operation is performed, the output of the exclusive OR gate XOR becomes L
low level, but the expected value signal and the comparator CMP
Are different from each other, that is, when the output is abnormal, the output of the exclusive OR gate XOR becomes High level. Further, the output of the exclusive OR gate XOR is held by a D-type flip-flop D-FF, and then connected to the set input of the SR latch circuit SR-L. A reset signal from the logic circuit unit CLB is input to the reset input of the SR latch circuit SR-L. This reset signal
As described above, since the signal changes from low to high at the start of the test, the output of the D-type flip-flop D-FF does not go to high level in the case of a good product. , Low. On the other hand, in the case of an abnormality, the output of the comparator CMP and the expected value signal generated by the logic circuit unit CLB are different from each other, so that the output of the D-type flip-flop D-FF becomes High, and this output is maintained thereafter. .

Therefore, as described in the first embodiment, a test is performed while changing the combination of the gain control signals GSEL with time, and finally the SR latch circuit S
The potential VD of the output of the RL, that is, the output of the TEST output terminal OUT0 is measured to determine whether the output is Low or Hi.
It is possible to detect whether all the gain switching operations are normal or whether some of the gain switching operations are abnormal only by checking whether the gain switching operation is gh.

[0026]

As described above, according to the present invention, among a plurality of amplifiers provided in a semiconductor integrated circuit and controlled in gain, gains different from each other for one amplifier and another amplifier are provided. By inputting control signals, comparing the outputs of these amplifiers with comparators, and comparing the comparison results with expected data, the switching operation of the gain control signal for each amplifier is normal or abnormal. It will be possible to test if there is. Alternatively, by setting the latch means according to the comparison result of the converter, and confirming the output of the latch means,
It is possible to test whether the switching operation of the gain control signal for each amplifier is normal or abnormal. Thus, according to the present invention, since the gain switching operation of the amplifier can be tested as a logic function test, the test process can be simplified and the test time can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor test circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart when a switching operation of a gain control signal according to the first embodiment is normal.

FIG. 3 is a timing chart when the switching operation of the gain control signal is abnormal in the first embodiment.

FIG. 4 is a diagram illustrating output values when a failure occurs in each bit.

FIG. 5 is a block diagram of a semiconductor test circuit according to a second embodiment of the present invention.

FIG. 6 is a timing chart in a case where a gain control signal switching operation in the second embodiment is normal.

FIG. 7 is a block diagram of an example of a conventional semiconductor test circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit 10 LSI tester 11 Expected value data 12 Collation circuit AMP1-AMPm Amplifier IN1-INm Input terminal OUT0 TEST output terminal OUT1-OUTm Output terminal CLB Logic circuit part SW1-SWm Switch CMP Comparator D-FF D-type flip-flop XOR Exclusive OR gate GSEL1 to GSELm Gain control signal

Claims (6)

[Claims] 1. A semiconductor integrated circuit comprising: a plurality of amplifiers having variable gains for amplifying and outputting input signals; and a logic circuit unit for outputting a gain control signal for controlling gains of the plurality of amplifiers. A switch provided on the output side of each of the amplifiers for selecting and extracting the output of each of the amplifiers; an output of one of the amplifiers extracted from the plurality of amplifiers by the switch and an output of another of the amplifiers A comparator for comparing each level of
A semiconductor test circuit comprising: output holding means for holding an output of the comparator and outputting the output to a test output terminal provided in the semiconductor integrated circuit. 2. A semiconductor integrated circuit comprising: a plurality of variable gain amplifiers for amplifying and outputting an input signal; and a logic circuit unit for outputting a gain control signal for controlling the gain of the plurality of amplifiers. A switch provided on the output side of each of the amplifiers for selecting and extracting the output of each of the amplifiers; an output of one of the amplifiers extracted from the plurality of amplifiers by the switch and an output of another of the amplifiers A comparator for comparing each level of
An exclusive-OR gate that takes an exclusive-OR of an output of the comparator and an expected value signal output from the logic circuit unit; an output holding unit that holds an output of the exclusive-OR gate; A latch circuit for setting the output of the holding unit as a set input and setting a reset signal from the logic circuit unit as a reset input. 3. The logic circuit section includes a gain control signal for controlling the one amplifier and the another amplifier to have different gains, respectively, for each of the one amplifier and the other one amplifier. The semiconductor test circuit according to claim 1, wherein the semiconductor test circuit outputs a signal. 4. An offset adjusting circuit for providing a difference between the level of the input terminal of the one amplifier and the level of the input terminal of the other amplifier to the input terminal of the output of the one amplifier. 4. The semiconductor test circuit according to claim 1, wherein the semiconductor test circuit is connected. 5. An apparatus for testing the semiconductor test circuit according to claim 1, wherein said means for inputting an input signal of the same level to said plurality of amplifiers is provided. Means for comparing the output of a test output terminal with expected value data, and causing the logic circuit unit to output a gain control signal corresponding to the expected value data. 6. An apparatus for testing a semiconductor test circuit according to claim 2, wherein said means for inputting an input signal of the same level to said plurality of amplifiers, Means for detecting the output level of a test output terminal, causing the logic circuit unit to output a gain control signal corresponding to the expected value signal, and the reset signal changing to a high level at the start of a test. A test device for a semiconductor test circuit, characterized by outputting.