JP4898539B2 - D / A converter and operation test method thereof - Google Patents

Description

  The present invention relates to a D / A converter provided with a test circuit, which is used for a system power supply or the like, and an operation test method thereof.

  In a conventional D / A converter operation test method, a high-precision voltmeter is connected to the output of the D / A converter, and a predetermined voltage is output for all combinations of digital code signals. I was sure that. However, in such a method, since the time (settling time) until the output voltage of the D / A converter reaches a predetermined voltage is long, the time required for the test becomes long and the production efficiency deteriorates. As the number of bits of the A converter increases, this tendency becomes more prominent.

  Thus, there has been a D / A converter test apparatus that shortens the test time of the D / A converter (see, for example, Patent Document 1). In this case, two switch groups, Ach and Bch, are provided for taking out one divided voltage by switch means for turning on / off the divided voltage by resistors connected in series in accordance with the digital code signal. The Bch switch means SiB (i is an integer) is turned on together with any one of the Ach switch means S (i-1) A or S (i + 1) A, and the output voltage of each ch at that time The magnitude relation of the above is measured by a comparator, and the quality of the switch means is judged from the result.

Similarly, the test of the Ach switch means is performed by turning on the Ach switch means SiA together with any one of the Bch switch means S (i-1) B or S (i + 1) B, The magnitude relation of the output voltage is measured by a comparator, and the quality of the switch means is determined from the result. Such a test was repeated and the test time was shortened only by the test of the switch means.
JP 2006-279132 A

  However, in such a method, there is a problem that two D / A outputs of Ach and Bch are required, and it cannot be applied to a 1ch D / A converter.

  The present invention has been made to solve such problems, and does not require a high-precision voltmeter, and can reduce the test time even with a 1ch D / A converter. An object is to obtain an A converter and an operation test method thereof.

A D / A converter according to the present invention is a D / A converter that D / A converts and outputs an input digital code signal.
A reference voltage generation circuit unit that generates a predetermined reference voltage and performs output control of the generated reference voltage according to a third test mode switching signal input from the outside;
A plurality of divided voltages obtained by dividing the inputted reference voltage by a plurality of voltage dividing ratios by a plurality of resistors connected in series are turned on / off in response to the digital code signal. A D / A conversion circuit that outputs an analog signal via a switch;
A first switch circuit that outputs a test signal input from the outside via a predetermined test signal input terminal as the reference voltage to the D / A conversion circuit unit in response to a first test mode switching signal input from the outside And
A second switch circuit unit for outputting an analog signal output from the D / A conversion circuit unit to the outside via a predetermined test signal output terminal in response to a second test mode switching signal input from the outside;
With
The D / A conversion circuit unit is connected to a plurality of switches that turn on / off the voltage input as the reference voltage according to the digital code signal in response to a fourth test mode switching signal input from the outside. It is output as an analog signal.

  The third test mode switching signal and the fourth test mode switching signal are the same test mode switching signal, and the first test mode switching signal and the second test mode switching signal are signals of the test mode switching signal. You may make it the same signal which reversed the level.

  In the test mode, the reference voltage generation circuit unit stops outputting the generated reference voltage, and the first switch circuit unit receives the test signal input via the test signal input terminal. A reference voltage is output to the D / A conversion circuit unit, and the D / A conversion circuit unit outputs an analog signal through a plurality of switches that turn on / off the voltage input as the reference voltage in accordance with the digital code signal. The second switch circuit unit outputs the analog signal output from the D / A conversion circuit unit to the outside via the test signal output terminal.

  In the normal operation mode, the reference voltage generation circuit unit outputs the generated reference voltage to the D / A conversion circuit unit, and the first switch circuit unit is input via the test signal input terminal. The output of the test signal to the D / A conversion circuit unit is cut off, and the second switch circuit unit cuts off the output of the analog signal output from the D / A conversion circuit unit to the test signal output terminal. The D / A converter circuit unit outputs one voltage from among the divided voltages obtained by dividing the inputted reference voltage by a plurality of voltage dividing ratios by a plurality of resistors connected in series. An analog signal is output through a plurality of switches that are turned on / off according to the signal.

In the D / A converter operation test method according to the present invention, a predetermined reference voltage is divided into a plurality of divided voltages by a plurality of resistors connected in series at a plurality of divided ratios. In an operation test method for a D / A converter that outputs an analog signal through a plurality of switches that are turned on / off in accordance with an input digital code signal, and that performs D / A conversion on the digital code signal.
During test mode,
A predetermined test signal is input from the outside as the reference voltage,
The test signal is output as an analog signal through the switch turned on according to the digital code signal,
Detecting the output analog signal,
The operation of the turned on switch is checked.

  In addition, the digital code signals are sequentially changed, and the operation check of the switches that are turned on is performed for all combinations of digital code signals.

  The test signal is a predetermined clock signal, and an operation check of the turned-on switch is performed depending on whether the clock signal is output as the analog signal.

  Further, the digital code signal is changed for each cycle of the clock signal.

  According to the D / A converter and the D / A converter operation test method of the present invention, a predetermined reference voltage is divided from a plurality of divided voltages divided by a plurality of voltage dividing ratios by a plurality of resistors connected in series. One voltage is output as an analog signal through a plurality of switches that are turned on / off according to the input digital code signal, and the digital code signal is D / A converted and output. A predetermined test signal is input from the outside as a voltage, the test signal is output as an analog signal through the switch turned on in accordance with the digital code signal, the output analog signal is detected, and the ON signal is detected. Checked the operation of the switch. Therefore, the test time can be shortened without using a highly accurate voltmeter and even with a 1ch D / A converter.

  In the normal operation mode, the first switch circuit unit cuts off the output of the test signal inputted through the test signal input terminal to the D / A conversion circuit unit, and the second switch circuit unit. Since the analog signal output from the D / A conversion circuit unit is blocked from being output to the test signal output terminal, a voltage is improperly applied to both the test signal input terminal and the test signal output terminal. Even if it is made short-circuited or short-circuited, the normal operation can be eliminated.

  In addition, since the digital code signal is changed for each cycle of the clock signal so that one cycle of the clock signal is the same as one set time of the digital code signal, the test of all bits is short. Can be done in time.

Next, the present invention will be described in detail based on the embodiments shown in the drawings.
First embodiment.
FIG. 1 is a block diagram showing a configuration example of a D / A converter according to the first embodiment of the present invention.
In FIG. 1, a D / A converter 1 includes a D / A conversion circuit 2, a reference voltage generation circuit 3 that generates and outputs a predetermined reference voltage Vref, a first switch M1 including an NMOS transistor, and an NMOS transistor. And a second switch M2.

  Further, the D / A converter 1 includes a D [11: 0] terminal including terminals to which a 12-bit digital code signal D [11: 0] is input and a CLK terminal to which a clock signal CLK is input. A SLEEP terminal to which the sleep signal SLEEP is input, a TEST1 terminal to which the first test mode switching signal TEST1 is input, a TEST2 terminal to which the second test mode switching signal TEST2 is input, and a third test mode switching signal TEST3. To output the output signal of the D / A conversion circuit 2 to the outside, the TEST4 terminal to which the fourth test mode switching signal TEST4 is input, the Tin terminal to which the test signal is input from the outside, Aout for outputting the analog signal Aout output from the Tout terminal and the D / A conversion circuit 2 to the outside And a terminal. The D / A conversion circuit 2 is a D / A conversion circuit unit, the reference voltage generation circuit 3 is a reference voltage generation circuit unit, the first switch M1 is a first switch circuit unit, and the second switch M2 is a second switch. Each circuit part is made.

  The reference voltage generation circuit 3 generates a reference voltage Vref used in the D / A converter 1, and a Vout terminal that is an output terminal is connected to a VRT terminal of the D / A conversion circuit 2. Further, in the reference voltage generation circuit 3, the sleep signal SLEEP is input to the SLEEP terminal that forms the input terminal, and the third test mode switching signal TEST3 is input to the TEST terminal that forms the input terminal. The first switch M1 is connected between the Tin terminal and the VRT terminal of the D / A conversion circuit 2, and the gate of the first switch M1 is connected to the TEST1 terminal. The second switch M2 is connected between the Tout terminal and the DAout terminal of the D / A conversion circuit 2, and the gate of the second switch M2 is connected to the TEST2 terminal. The D / A conversion circuit 2 further receives a digital code signal D [11: 0], a clock signal CLK, a sleep signal SLEEP, and a fourth test mode switching signal TEST4, and performs a D / A converted analog signal Aout. Is output from the AMPout terminal, which is an output terminal, to the Aout terminal.

FIG. 2 is a diagram showing a circuit example of the reference voltage generation circuit 3 of FIG.
In FIG. 2, the reference voltage generating circuit 3 includes a reference voltage generating circuit 11 using a bandgap reference, an operational amplifier circuit 12, resistors 13 and 14 forming feedback resistors, and an NMOS transistor M11. The reference voltage output from the reference voltage generation circuit 11 is output to the non-inverting input terminal of the operational amplifier circuit 12, amplified by the operational amplifier circuit 12, and output as the reference voltage Vref from the Vout terminal. The reference voltage generation circuit 11 and the operational amplifier circuit 12 are each input with a sleep signal SLEEP. When a predetermined sleep signal SLEEP is input, the reference voltage generation circuit 11 and the operational amplifier circuit 12 are stopped so that the consumption current becomes almost zero. At this time, the output terminal of the operational amplifier circuit 12 is in a high impedance state.

  Resistors 13 and 14 are connected in series between the output terminal of the operational amplifier circuit 12 and the drain of the NMOS transistor M11, and the source of the NMOS transistor M11 is connected to the ground voltage. The connection between the resistors 13 and 14 is connected to the inverting input terminal of the operational amplifier circuit 12, the gate of the NMOS transistor M11 is connected to the TEST terminal, and the third test mode switching signal TEST3 is input. The NMOS transistor M11 is turned on when the third test mode switching signal TEST3 is at a high level, and connects one end of the resistor 14 to the ground voltage. However, when the third test mode switching signal TEST3 is at a low level, the NMOS transistor M11 is turned off. 14 is disconnected from the ground voltage.

FIG. 3 is a diagram showing a circuit example of the D / A conversion circuit 2 of FIG.
In FIG. 3, the D / A conversion circuit 2 includes a decoder 21 that decodes and outputs low-bit digital code signals D0 to D5 into 64 lines, and a latch circuit that latches the output signal of the decoder 21 in synchronization with the clock signal CLK. 22, a decoder 23 that decodes and outputs the high-bit digital code signals D6 to D11 into 64 lines, a latch circuit 24 that latches the output signal of the decoder 23 in synchronization with the clock signal CLK, a resistance voltage dividing circuit 25, An operational amplifier circuit 26 that amplifies the output voltage from the resistance voltage divider circuit 25, resistors 27 and 28 that form feedback resistors of the operational amplifier circuit 26, and an NMOS transistor M21 that is on / off controlled by a fourth test mode switching signal TEST4. And a resistor R0.

Further, the resistor voltage dividing circuit 25 includes 4096 resistors R1 to R4096, 64 NMOS transistors SL0 to SL63 that are turned on / off by corresponding output signals L0 to L63 output from the latch circuit 22, and latches. 4096 NMOS transistors S1 to S4096 that are ON / OFF controlled by corresponding output signals H0 to H63 output from the circuit 24. The NMOS transistors SL0 to SL63 and S1 to S4096 each switch.
Resistors R0 to R4096 are connected in series between the drain of the NMOS transistor M21 and the VRT terminal, the source of the NMOS transistor M21 is connected to the ground voltage, and the gate of the NMOS transistor M21 is connected to the TEST terminal. A fourth test mode switching signal TEST4 is input.

  Further, in the NMOS transistors S1 to S4096, the drains are connected to the corresponding connecting portions of the series circuit of the resistors R0 to R4096, the sources are connected to the drains of the corresponding NMOS transistors SL0 to SL63, respectively, and the gates are connected to the outputs. Signals H0 to H63 are input correspondingly. The sources of the NMOS transistors SL0 to SL63 are connected, and the connection is connected to the DAout terminal and the non-inverting input terminal of the operational amplifier circuit 26, respectively. Output signals L0 to L63 are respectively input to the gates of the NMOS transistors SL0 to SL63.

  The output terminal of the operational amplifier circuit 26 is connected to the AMPout terminal, and resistors 27 and 28 are connected in series between the output terminal of the operational amplifier circuit 26 and the ground voltage. The connection portion of the resistor 27 and the resistor 28 is connected to the inverting input terminal of the operational amplifier circuit 26. Further, the sleep signal SLEEP is input to the operational amplifier circuit 26, and the operational amplifier circuit 26 is controlled in operation by the sleep signal SLEEP. The The operational amplifier circuit 26 amplifies the divided voltage output from the resistance voltage dividing circuit 25 at an amplification factor determined by the resistance values of the feedback resistors 27 and 28 and outputs the amplified voltage to the AMPout terminal.

  In such a configuration, when the D / A converter 1 performs a normal operation, the first test mode switching signal TEST1 and the second test mode switching signal TEST2 are at a low level, respectively, and the third test mode switching signal TEST3 and the second test mode switching signal TEST3 Each of the 4 test mode switching signals TEST4 is at a high level. In this case, the first switch M1 and the second switch M2 are each turned off to be in a cut-off state, and the Tin terminal and the Tout terminal are disconnected from the internal circuit. Also, the NMOS transistor M11 is turned on and becomes conductive, and the operational amplifier circuit 12 amplifies the output voltage of the reference voltage generation circuit 11 with an amplification factor determined by the resistance values of the feedback resistors 13 and 14, and the D / A converter circuit. 2 to the VRT terminal. Also, since the NMOS transistor M21 is turned on and becomes conductive, one end of the resistor R0 is connected to the ground voltage, and the reference voltage Vref from the reference voltage generation circuit 3 is input to the series circuit of the resistors R0 to R4096. The D / A converter 1 performs a normal D / A conversion operation. Since the normal operation of the D / A conversion circuit 2 is well known, its description is omitted.

Next, the case where the D / A converter 1 is tested will be described.
In this case, first, a predetermined sleep signal SLEEP is input, the reference voltage generation circuit 11 and the operational amplifier circuit 12 stop operating, and the output terminal of the operational amplifier circuit 12 enters a high impedance state. The operational amplifier circuit 26 also stops operating.
Next, the third test mode switching signal TEST3 and the fourth test mode switching signal TEST4 are each set to a low level. For this reason, the NMOS transistors M11 and M21 are turned off to be cut off, the connection of the resistors R0 and 14 to the ground voltage is cut off, and the connections at both ends in the series circuit of the resistors R0 to R4096 are connected from other circuits. Completely disconnected.

Next, the first test mode switching signal TEST1 and the second test mode switching signal TEST2 are each set to a high level. For this reason, the first switch M1 and the second switch M2 are turned on and become conductive, the Tin terminal is connected to the VRT terminal of the D / A conversion circuit 2, and one end of the resistor R4096 is connected to the Tin terminal. Further, the Tout terminal is connected to the DAout terminal of the D / A conversion circuit 2.
Next, arbitrary digital code signals D0 to D11 are input, and a predetermined voltage is input to the Tin terminal. Confirm that the voltage is output to the Tout terminal. The test is completed by performing such confirmation with all combinations of the digital code signals D0 to D11.

  Specifically, it is assumed that the digital code signals D0 to D11 are all 0. Then, the NMOS transistor SL0 and the NMOS transistors S1 to S64 of the resistance voltage dividing circuit 25 are turned on. At this time, when the voltage V1 is input to the Tin terminal, the voltage V1 is input to the VRT terminal of the D / A conversion circuit 2 through the first switch M1, and further turned on through the series circuit of the resistors R1 to R4096. The signal is output to the DAout terminal of the D / A conversion circuit 2 through the NMOS transistor S1 and the NMOS transistor SL0, and is output to the Tout terminal of the D / A converter 1 through the second switch M2. That is, the voltage input to the Tin terminal is output to the Tout terminal as it is.

  Next, when the bits of the digital code signals D0 to D11 are sequentially increased until all bits become 1, the number of resistors through which the voltage input to the Tin terminal passes decreases one by one, and the NMOS transistors that are turned on sequentially move. Thus, the voltage input to the Tin terminal is always output to the Tout terminal. If the NMOS transistors S1 to S4096 and SL1 to SL63 have a problem, the voltage input from the Tout terminal to the Tin terminal is not output when the digital code signal that turns on the defective NMOS transistor is set. A defective NMOS transistor can be detected.

  In an actual test, a test signal forming a clock signal as shown in FIG. 4 is input to the Tin terminal, and a signal having a waveform as shown in FIG. 4 is output from the Tout terminal. The smaller the voltage amplitude V1 of the input test signal, the faster the operation can be performed. However, since it is restricted by the characteristics of the NMOS transistor used for the switch means, it is set to about 2V. If 50 pF is applied as a load of the measuring instrument connected to the Tout terminal, the settling time due to the time constant needs to be 100 μsec. For this reason, when the period of the clock signal is 200 μsec, the time required for the inspection of all the NMOS transistors S1 to S4096 and SL0 to SL63 is about 0.8 seconds.

In the above description, four first test mode switching signals TEST1, second test mode switching signal TEST2, third test mode switching signal TEST3, and fourth test mode switching signal TEST4 are used. However, one test mode switching signal is used. The operation may be switched by TEST. In this case, FIG. 1 is as shown in FIG. In FIG. 5, the same or similar parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted here, and only differences from FIG. 1 are described.
5 differs from FIG. 1 in that the first test mode switching signal TEST1, the second test mode switching signal TEST2, the third test mode switching signal TEST3, and the fourth test mode switching signal TEST4 in FIG. The test mode switching signal TEST is input to the A / A conversion circuit 2 and the reference voltage generation circuit 3, respectively, and the signal level of the test mode switching signal TEST is inverted by the inverter 31 to each gate of the first switch M1 and the second switch M2. In other words, the received signals are input.

  In this way, in order to set the test mode, the test mode switching signal TEST may be set to the low level after inputting the predetermined sleep signal SLEEP, and the third test mode switching signal TEST3 as shown in FIG. The test procedure for setting the first test mode switching signal TEST1 and the second test mode switching signal TEST2 to high level can be performed simultaneously. Since the operation in the test mode is the same as that in FIG. 1, the description thereof is omitted.

  As described above, the D / A converter according to the first embodiment disconnects the resistance voltage dividing circuit 25 from the reference voltage generation circuit 3 and inputs a predetermined voltage to one end of the resistance voltage dividing circuit 25 in the test mode. Thus, the voltage output through the NMOS transistor which forms a switch with each resistor of the resistance voltage dividing circuit 25 is observed. Therefore, it is possible to test an NMOS transistor that constitutes a switch constituting the resistance voltage dividing circuit 25 in a short time without using a high-precision voltmeter, and even a 1ch D / A converter can be tested. Can be shortened.

It is the block diagram which showed the structural example of the D / A converter in the 1st Embodiment of this invention. FIG. 2 is a diagram illustrating an example of an internal circuit of a reference voltage generation circuit 3 in FIG. 1. It is the figure which showed the example of the internal circuit of the D / A conversion circuit 2 of FIG. It is the timing chart which showed each waveform example of the signal input from the Tout terminal with respect to the signal input into the Tin terminal. It is the block diagram which showed the structural example of the D / A converter in the 2nd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 D / A converter 2 D / A conversion circuit 3 Reference voltage generation circuit 21, 23 Decoder 22, 24 Latch circuit 25 Resistance voltage dividing circuit 26 Operation amplifier circuit 27, 28 Resistance M1 1st switch M2 2nd switch M21, S1 S4096 and SL0 to SL63 NMOS transistor R0 to R4096, 27, 28 Resistance

Claims (8)

In a D / A converter for D / A converting and outputting an input digital code signal,
A reference voltage generation circuit unit that generates a predetermined reference voltage and performs output control of the generated reference voltage according to a third test mode switching signal input from the outside;
A plurality of divided voltages obtained by dividing the inputted reference voltage by a plurality of voltage dividing ratios by a plurality of resistors connected in series are turned on / off in response to the digital code signal. A D / A conversion circuit that outputs an analog signal via a switch;
A first switch circuit that outputs a test signal input from the outside via a predetermined test signal input terminal as the reference voltage to the D / A conversion circuit unit in response to a first test mode switching signal input from the outside And
A second switch circuit unit for outputting an analog signal output from the D / A conversion circuit unit to the outside via a predetermined test signal output terminal in response to a second test mode switching signal input from the outside;
With
The D / A conversion circuit unit is connected to a plurality of switches that turn on / off the voltage input as the reference voltage according to the digital code signal in response to a fourth test mode switching signal input from the outside. A D / A converter characterized by outputting as an analog signal.   The third test mode switching signal and the fourth test mode switching signal are the same test mode switching signal, and the first test mode switching signal and the second test mode switching signal indicate the signal level of the test mode switching signal. 2. The D / A converter according to claim 1, wherein the same signal is inverted.   In the test mode, the reference voltage generation circuit unit stops outputting the generated reference voltage, and the first switch circuit unit receives the test signal input via the test signal input terminal as the reference voltage. To the D / A conversion circuit unit, and the D / A conversion circuit unit outputs the voltage input as the reference voltage as an analog signal through a plurality of switches that are turned on / off according to the digital code signal. 3. The D according to claim 1, wherein the second switch circuit unit outputs the analog signal output from the D / A conversion circuit unit to the outside through the test signal output terminal. / A converter.   In the normal operation mode, the reference voltage generation circuit unit outputs the generated reference voltage to the D / A conversion circuit unit, and the first switch circuit unit receives the input through the test signal input terminal. The output of the test signal to the D / A conversion circuit unit is cut off, and the second switch circuit unit cuts off the output of the analog signal output from the D / A conversion circuit unit to the test signal output terminal, The D / A conversion circuit unit converts one voltage among the divided voltages obtained by dividing the input reference voltage by a plurality of voltage dividing ratios by a plurality of resistors connected in series into the digital code signal. 4. The D / A converter according to claim 1, wherein the D / A converter outputs the signal as an analog signal through a plurality of switches which are turned on / off in response. A plurality of divided voltages obtained by dividing a predetermined reference voltage by a plurality of voltage dividing ratios by a plurality of resistors connected in series, and turning on / off one voltage in accordance with an input digital code signal In an operation test method of a D / A converter that outputs the digital code signal by D / A conversion, which is output as an analog signal via a switch
During test mode,
A predetermined test signal is input from the outside as the reference voltage,
The test signal is output as an analog signal through the switch turned on according to the digital code signal,
Detecting the output analog signal,
An operation test method for a D / A converter, comprising performing an operation check on the turned-on switch.   6. The operation test method for a D / A converter according to claim 5, wherein the digital code signals are sequentially changed, and the operation check of the turned-on switches is performed for all combinations of the digital code signals.   7. The D / according to claim 5, wherein the test signal is a predetermined clock signal, and an operation check of the turned on switch is performed depending on whether the clock signal is output as the analog signal. A converter operation test method.   8. The operation test method for a D / A converter according to claim 7, wherein the digital code signal is changed for each cycle of the clock signal.

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