JP6328899B2 - Resistance array circuit, current generation circuit, current control type oscillation circuit, FLL circuit, and resistance array test method - Google Patents

Description

  The present invention relates to a resistor array circuit having a test function, a current generation circuit using the resistor array circuit, a current control type oscillation circuit, and an FLL circuit.

  A resistance array configured by connecting a plurality of resistance elements in series is used, for example, in a variable resistance circuit, a voltage generation circuit, a current generation circuit, a DA converter, and the like. In order to test the resistance value of each resistance element constituting the resistance array and the presence or absence of disconnection of the connection path of each resistance element, a resistance array with a test function is known.

  For example, in Patent Document 1, a plurality of resistor ladder units configured by a plurality of first resistors connected in series, one end connected to a connection point of the plurality of first resistors, and the other end connected in common. A control switch, a test switch connected between a common connection point of a plurality of control switches and a high-level power supply, a second resistor connected between one end of the resistor ladder section and the ground, and during testing A test circuit for a semiconductor integrated circuit having a logic circuit that turns on a test switch and controls all of a plurality of control switches to an off state or one of a plurality of control switches to an on state is described ing.

  Further, in Patent Document 2, one of the divided voltages obtained by dividing the reference voltage Vref output from the reference voltage generation circuit 3 in accordance with the signal TEST3 at a plurality of voltage division ratios is obtained as a digital code signal D [ 11: 0] and a D / A conversion circuit 2 that outputs via a plurality of switches that are turned on / off in response to the signal 11: 0], and a test signal that is input to the input terminal Tin in response to the signal TEST1, as a reference voltage Vref. The D / A conversion circuit 2 includes a first switch M1 that outputs to the conversion circuit 2 and a second switch M2 that outputs a signal output from the D / A conversion circuit 2 to the output terminal Tout according to the signal TEST2. Is a D / A converter that outputs a voltage input as a reference voltage Vref according to a signal TEST4 via a plurality of switches that are turned on / off according to a digital code signal D [11: 0]. Data have been described.

JP 2004-48566 A JP 2008-277940 A

FIG. 1 is a diagram illustrating an example of a configuration of a resistance array circuit 100 having a test function. The resistance array circuit 100 includes m × n resistance elements r connected in series, and each constitutes a plurality of resistance units R _{1 to} R _n including m resistance elements r. That is, each resistor unit _R 1 to R _n are connected in series. Terminal portions of the resistor array are connected to terminals T1 and T2, respectively.

Each connection point and one end of the resistance between elements in the resistance unit R _1, the switching element Q ₁₁ are respectively connected. Each of the switching element _{Q 11} is, for example, a n-channel MOSFET, the drain of which is connected to the resistive element r, the relay point _C 1 in which the source is _associated, C 2, is _connected., To _{C m-1} and _{C m} the gate is connected to a common gate line G _11. Similarly, the one end portion of each connection point and the resistance unit _R 2 to R _n between the resistance element r in the resistance unit _R 2 to R _n are connected to the switching element _Q 12 _{to Q 1n.} The switching elements Q _{12 to} Q _1n are, for example, n-channel MOSFETs, the drain is connected to the resistance element r, and the source is connected to the corresponding relay points C ₁ , C ₂ ,..., C _m−1 and C _m . is, the gate is connected to the gate line _G 12 _{~G 1n} respectively. The gate lines G _{11 to} G _1n are connected to the decoder 110.

Decoder 110, a first resistance control signal sel_r a digital signal of n bits supplied from the control unit 400: Based on the [n 1], or the control of the high level of the gate lines G ₁₁ ~G _1n Supply the signal. Among the switching elements Q _{11 to} Q _1n , each of the switching elements connected to the gate wiring supplied with the high-level control signal is turned on, and the connection point between the resistance elements in the corresponding resistance unit and the resistance unit Are connected to the relay points C _{1 to} C _m , respectively. For example, a first resistance control signal SEL_R: when the gate line G ₁₁ is selected by the [n 1], each switching element Q ₁₁ connected to the gate line G ₁₁ is turned on, resistor unit R ₁ one end of the connection point and the resistance unit R ₁ between the resistive elements in are respectively connected to the relay point C ₁ -C _m.

The relay point _C 1 -C _m, respectively, the switching elements _Q 21 _{to Q 2m} is connected. The switching element _Q 21 _{to Q 2m,} for example, an n-channel MOSFET, the drain of which is connected to the corresponding relay point _C 1 -C _m, the source is connected to the potential _{V SS,} gates gate line _G 21 _{~G 2m} To the decoder 110.

Decoder 110, a second resistance control signal sel_c supplied from the control unit 400: Based on the [m 1], and supplies a high-level control signal to one of the gate lines G ₂₁ ~G _2m. Among the switching elements Q _{21 to} Q _2m , the switching element connected to the gate wiring to which the high-level control signal is supplied is turned on, and the corresponding relay point (any one of C _{1 to} C _m ) has the potential V _SS. Connected to. For example, the second resistance control signal Sel_c: If [m 1] by the switching element Q ₂₂ is a selectively turned on, relay point C ₂ is connected to the potential V _SS.

For example, a first resistance control signal sel_r [n: 1] gate lines G ₁₁ is selected by and the second resistance control signal Sel_c: When the gate line G ₂₂ is selected by [m 1], the switching element each and the switching element _{Q 22} of Q ₁₁ are turned on, the resistor unit _{R 1,} connection point X between the resistor _{r a} and _{r b} is connected to the potential _{V SS.} In this case, assuming that the potential of the terminal T2 is fixed to the potential V _SS, since the connection point X and the terminal T2 is short-circuited, the resistance value between the terminals T1 and T2, the terminal T1 And the resistance value of each resistance element arranged between the connection point X and the connection point X. Thus, in the resistance array circuit 100, the resistance value between the terminal T1 and the terminal T2 is such that the first resistance value control signal sel_r [n: 1] and the second resistance value control signal sel_c [m: 1]. A variable resistor determined according to the above is configured.

  An output circuit 500 for testing each resistance element r and each switching element is connected to the terminal T1. The output circuit 500 includes an operational amplifier circuit having a non-inverting input terminal connected to the terminal T1 and an inverting input terminal connected to the output terminal. That is, the output circuit 500 constitutes a voltage follower, and outputs a voltage appearing at the terminal T1 from the output terminal 501.

When testing the resistor array circuit 100 supplies a constant current between the terminals T1 and T2, the output circuit 500 while sequentially selects the gate lines _G 11 _{~G 1n} and _G 21 _{~G 2m} by the decoder 110 It is determined whether the output voltage appearing at the output terminal 501 is appropriate. That is, the output circuit 500 converts the resistance value of each resistance element r constituting the resistance array circuit 100 into a voltage value and outputs the voltage value.

However, according to such a test method, the path test for testing the operation of each switching element and the conduction state on the connection path of the resistance element r and the resistance value test for testing the resistance value of each resistance element r are simultaneously performed. since the be done, in order to guarantee the quality of the resistor array circuit 100, for all combinations of the gate lines G ₁₁ ~G _1n and gate lines G ₂₁ ~G _2m be testing is essential . In other words, m × n measurements are essential. Since a certain amount of time is required until the output voltage output from the output circuit 500 is stabilized, the test time becomes longer when tests are performed on all paths.

  The present invention has been made in view of the above points, and separately performs a path test for testing a conduction state on a connection path of a resistor array and a resistance value test for testing a resistance value of each resistance element. A resistance array circuit capable of shortening the test time by making possible, a current generation circuit using the resistance array circuit, a current control type oscillation circuit, an FLL circuit, and a test method for the resistance array circuit With the goal.

A resistor array circuit according to the present invention includes a plurality of resistor units each including a plurality of resistor elements connected in series, a resistor array in which the plurality of resistor units are connected in series, and each of the plurality of resistor units A plurality of first switching elements provided between each resistance element and a relay point corresponding to each resistance element, and a plurality of second switching elements provided between each of the relay points and a first potential A switching element, a plurality of third switching elements provided between one end of each of the plurality of resistance units and the first potential, a second end of each of the plurality of resistance units, and a second potential A plurality of fourth switching elements provided between each of the relay points and a plurality of fifth switching elements provided between each of the relay points and the output unit, and the plurality of fifth switching elements provided in a first test mode. Resistance unit The third switching element is controlled so that the end is connected to the first potential, the fifth switching element is controlled so that relay points connected to the output unit are sequentially switched, and the output unit is connected to the output unit. Control means for controlling the first switching element so that the resistance units connected to the relay points are sequentially switched in conjunction with switching of the connected relay points .

  The current generation circuit according to the present invention includes the resistor array circuit and a current generator that is connected to a connection terminal of the resistor array circuit and generates a current having a current value according to a resistance value between the connection terminals. .

  The current control type oscillation circuit according to the present invention includes the current generation circuit and an oscillator that outputs an output signal having a frequency corresponding to a current value of the current generated by the current generation circuit.

  The FLL circuit according to the present invention is configured by providing the current control type oscillation circuit in a frequency lock loop.

A test method for a resistance array according to the present invention includes a plurality of resistance units each including a plurality of resistance elements connected in series, and the test method for a resistance array in which the plurality of resistance units are connected in series, Connecting one end of a plurality of resistance units to a first potential; connecting each resistance element in any one of the plurality of resistance units to a corresponding relay point; and the relay point A step of connecting any one of the output unit to the output unit, the output unit outputting an output signal of a level corresponding to a conduction state of a path passing through the relay point connected to the output unit, and the output Sequentially switching the relay points connected to the output unit, and switching the resistance units connected to the relay points in conjunction with the switching of the relay points connected to the output unit. Comprising a step of switching, the.

  According to the present invention, it is possible to individually perform a path test for testing the conduction state on the connection path of the resistor array and a resistance value test for testing the resistance value of each resistance element, thereby reducing the test time. It becomes possible.

It is a figure which shows an example of a structure of the resistance array circuit provided with the test function. It is a block diagram which shows the structure of the resistance array circuit which concerns on embodiment of this invention. It is a figure which shows the structure of the resistance array circuit which concerns on embodiment of this invention. It is the figure which illustrated the one aspect | mode of the 1st path | route test which concerns on embodiment of this invention. It is the figure which illustrated the one aspect | mode of the 2nd path | route test which concerns on embodiment of this invention. It is the figure which illustrated the one aspect | mode of the resistance value test which concerns on embodiment of this invention. It is the figure which illustrated the one aspect | mode of the resistance value test which concerns on embodiment of this invention. It is a block diagram which shows the structure of the electric current generation circuit which concerns on embodiment of this invention. It is a block diagram which shows the structure of the current control type oscillation circuit which concerns on embodiment of this invention. It is a block diagram which shows the structure of the FLL circuit which concerns on embodiment of this invention.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or corresponding components are given the same reference numerals.

  FIG. 2 is a block diagram showing a configuration of the resistance array circuit 1 according to the embodiment of the present invention. The resistance array circuit 1 is configured as a semiconductor integrated circuit including a variable resistance unit 10, a path selection unit 20, a determination output unit 30, and a control unit 40.

  The variable resistance unit 10 includes a resistance array including a plurality of resistance elements connected in series, and a first resistance value control signal sel_r [n: which is an n-bit digital signal supplied from the control unit 40. 1] and a second resistance value control signal sel_c [m: 1], which is an m-bit digital signal, constitutes a variable resistor whose resistance value changes between the terminal T1 and the terminal T2. Note that the first resistance value control signal sel_r [n: 1] and the second resistance value control signal sel_c [m: 1] may be upper bits and lower bits of a series of n + m bit digital signals.

  The variable resistance unit 10 also includes a first test control signal test_1 [0], which is a 1-bit digital signal supplied from the control unit 40 when a path test and a resistance value test described later are performed, and an m-bit digital signal. In response to the second test control signal test_2 [m: 1], which is a signal, a predetermined node on the connection path of the resistance element constituting the variable resistance unit 10 is connected to a predetermined potential.

  The path selection unit 20 has one end connected to a predetermined node in the variable resistance unit 10 in response to a path selection signal rc [m: 1] that is an m-bit digital signal supplied from the control unit 40 in the path test. By turning on one of the m switches, a path that passes through the switch that has been turned on is connected to the determination output unit 30.

  The determination output unit 30 determines the conduction state of the path selected by the path selection unit 20, and outputs a determination output signal rc_out having a signal level corresponding to the determination result. The determination output unit 30 corresponds to the output unit in the present invention.

  FIG. 3 is a diagram showing a detailed configuration of the resistor array circuit 1 according to the embodiment of the present invention.

The variable resistance unit 10 includes a resistance array including m × n resistance elements r connected in series. This resistor array constitutes a plurality of resistance units R _{1 to} R _n each including m resistance elements r. That is, each resistor unit _R 1 to R _n are connected in series. Terminal portions of the resistor array are connected to terminals T1 and T2, respectively.

Each connection point and one end of the resistance between elements in the resistance unit R ₁ (node A), the switching element Q ₁₁ are respectively connected. Each of the switching element _{Q 11} is, for example, a n-channel MOSFET, the drain of which is connected to the resistive element r, the relay point _C 1 in which the source is _associated, C 2, is _connected., To _{C m-1} and _{C m} the gate is connected to a common gate line G _11.

Similarly, one end of each connection point and the resistance unit _R 2 to R _n between the resistor elements in the resistor unit _R 2 to R _n (node B to E), each switching element _Q 12 _{to Q 1n} It is connected. The switching elements Q _{12 to} Q _1n are, for example, n-channel MOSFETs, the drain is connected to the resistance element r, and the source is connected to the corresponding relay points C ₁ , C ₂ ,..., C _m−1 and C _m . is, the gate is connected to the gate line _G 12 _{~G 1n} respectively. The gate lines G _{11 to} G _1n are connected to the first decoder 11.

The first decoder 11 supplies a high-level drive signal to any one of the gate wirings G _{11 to} G _1n based on the first resistance value control signal sel_r [n: 1] supplied from the control unit 40. Among the switching elements Q _{11 to} Q _1n , each of the switching elements connected to the gate wiring supplied with the high-level drive signal is turned on, and the connection point between the resistance elements in the corresponding resistance unit and the resistance unit Are connected to the relay points C _{1 to} C _m , respectively. For example, a first resistance control signal SEL_R: when the gate line G ₁₁ is selected by the [n 1], each switching element Q ₁₁ connected to the gate line G ₁₁ is turned on, resistor unit R ₁ one end of the connection point and the resistance unit R ₁ (node a) between the resistive elements in are respectively connected to the relay point C ₁ -C _m.

The relay point _C 1 -C _m, respectively, the switching elements _Q 21 _{to Q 2m} is connected. The switching element _Q 21 _{to Q 2m,} for example, an n-channel MOSFET, the drain of which is connected to the corresponding relay point _C 1 -C _m, the source is connected to the potential _{V SS,} gates gate line _G 21 _{~G 2m} Is connected to the first decoder 11.

The first decoder 11 includes gate wirings G _{21 to} G based on the second resistance value control signal sel_c [m: 1] supplied from the control unit 40 together with the first resistance value control signal sel_r [n: 1]. _A high level drive signal is supplied to any one of _{2 m} . Among the switching elements Q _{21 to} Q _2m , the switching element connected to the gate wiring to which the high-level drive signal is supplied is turned on, and the corresponding relay point (any one of C _{1 to} C _m ) has the potential V _SS. Connected to. For example, the second resistance control signal Sel_c: If [m 1] by the switching element Q ₂₂ is a selectively turned on, relay point C ₂ is connected to the potential V _SS.

For example, a first resistance control signal sel_r [n: 1] gate lines G ₁₁ is selected by and the second resistance control signal Sel_c: When the gate line G ₂₂ is selected by [m 1], the switching element each and the switching element _{Q 22} of Q ₁₁ are turned on, the resistor unit _{R 1,} connection point X between the resistor _{r a} and _{r b} is connected to the potential _{V SS.} In this case, assuming that the potential of the terminal T2 is fixed to the potential V _SS, since the connection point X and the terminal T2 is short-circuited, the resistance value between the terminals T1 and T2, the terminal T1 And the resistance value of each resistance element arranged between the connection point X and the connection point X. As described above, the variable resistance unit 10 has a resistance value between the terminal T1 and the terminal T2 such that the first resistance value control signal sel_r [n: 1] supplied from the control unit 40 and the second resistance value control. A variable resistor determined according to the signal sel_c [m: 1] is configured.

In addition, each of the resistance units R ₁ , R ₂ ,..., R _n-2 and R _n−1 has one end (nodes A, B, C and D) at the switching elements Q ₃₁ and Q _32. , ... _{it is} connected to the potential _{V SS} via a _{Q 3n-2} and _{Q 3n-1.} In addition, each of the resistance units R ₁ , R ₂ ,..., R _n−2 , R _n−1 and R _n has the other end (nodes F, G, H, I and J) at the switching element Q _41. , Q ₄₂ ,..., Q _4n−2 , Q _4n−1 and Q _4n are connected to the potential V _DD . The resistance array circuit 1 has pads 13 and 14 for applying a potential V _DD and a potential V _SS from the outside. By connecting an external power source to these pads, the potential V _DD and the potential V _SS can be arbitrarily set. The size can be set.

The switching elements Q _{31 to} Q _3n−1 are, for example, N-channel MOSFETs, their drains are connected to one ends (nodes A to D) of the resistance units R _{1 to} R _n−1 , and their sources are at the potential _VSS . It is connected. The gates of the switching elements Q _{31 to} Q _3n−1 are connected to the second decoder 12 through a common gate wiring. The second decoder 12 supplies a high level drive signal to each gate of the switching elements Q _{31 to} Q _3n−1 based on the first test control signal test_1 [0] supplied from the control unit 40. , the oN state of each of the switching elements _Q 31 _{~Q 3n-1.} Thus, one end of the resistor unit _{R 1 ~R n-1} (node to D) are respectively connected to the potential _{V SS.} In this embodiment, the switching elements Q _{31 to} Q _3n-1 are collectively turned on / off by connecting the gates of the switching elements Q _{31 to} Q _3n-1 to a common gate wiring. The switching elements Q _{31 to} Q _3n-1 may be individually turned on / off by connecting the gates of the elements Q _{31 to} Q _3n-1 to individual gate wirings.

On the other hand, the switching elements Q _{41 to} Q _4n are, for example, P-channel MOSFETs, the drains are connected to the other ends (nodes F to J) of the resistance units R _{1 to} R _n , and the sources are connected to the potential V _DD. ing. The gates of the switching elements Q _{41 to} Q _4n are connected to the second decoder 12. The second decoder 12 supplies a low-level drive signal to one of the gates of the switching elements Q _{41 to} Q _4n based on the second test control signal test_2 [n: 1] supplied from the control unit 40. The switching element is turned on. The other end (any one of the nodes F to J) of the resistance unit connected to the switching element that is turned on is connected to the potential V _DD .

The switching elements Q _{11 to} Q _1n correspond to the first switching element in the present invention. The switching element _Q 21 _{to Q 2m} is gymnastics second switching element in the present invention. Switching elements _Q 31 _{~Q 3n-1} corresponds to the third switching element in the present invention. Switching elements Q _{41 to} Q _4n correspond to the fourth switching element in the present invention.

The path selection unit 20 includes switching elements Q _{51 to} Q _5m and a third decoder 31. The switching elements Q _{51 to} Q _5m are, for example, n-channel MOSFETs, the sources are connected to the corresponding relay points C _{1 to} C _m , the drains are connected to the determination output unit 30, and the gates are connected to the third decoder 21. ing.

The third decoder 21, the path selection signal rc supplied from the control unit 40: on the basis of [m 1], and supplies a drive signal of one of the gate to the high level of the switching elements Q ₅₁ to Q _{5 m,} the The switching element is turned on. A relay point (any _{one of the} nodes C _{1 to} C _m ) connected to the switching element that is turned on is connected to the determination output unit 30. Switching elements Q _{51 to} Q _5m correspond to the fifth switching element in the present invention.

The determination output unit 30 has an input terminal connected to the drains of the switching elements Q _{51 to} Q _5m, an output terminal connected to the output terminal 32, one terminal connected to the potential V _DD , and the other terminal Includes a resistance element r ₃₀ connected to the input terminal of the inverter 31. The determination output unit 30 generates a determination output signal rc_out having a signal level corresponding to the conduction state of the test target path determined according to the operation state of the switching elements Q _{11 to} Q _1n , Q _{21 to} Q _2m , and Q _{51 to} Q _5m. Output from the output terminal 32. In the present embodiment, the determination output unit 30 is configured using an inverter, but may be configured using a comparator.

  According to the resistance array circuit 1 according to the present embodiment, the path test for testing the operation of each switching element and the conduction state of each path in the resistance array circuit 1 and the resistance value test for testing the resistance value of the resistance element r are performed. It can be done independently of each other.

The path test in the resistance array circuit 1 will be described below. Path test in the resistor array circuit 1 includes a switching element _{Q 11 ~Q 1n, Q 31 ~Q} 3n-1, Q 51 ~Q a first path test performed by operating the _{5 m,} the switching elements _Q 21 _{to Q 2m, Q 31 ~Q 3n-1, Q} 51 ~Q 5m is operated and a second path tests performed. The first path test corresponds to the first test mode in the present invention, and the second path test corresponds to the second test mode in the present invention.

  FIG. 4 is a diagram illustrating one mode of the first path test in the resistance array circuit 1. In FIG. 4, the switching elements that are turned on are circled and displayed.

When performing the first path test, the control unit 40 supplies the first test control signal test_1 [0] to the second decoder 12. The second decoder 12 supplies receives the first test control signal TEST_1 [0], the drive signal of the gate to the high level of each of the switching elements _{Q 31 ~Q 3n-1.} Thus, each of the switching elements _Q 31 _{~Q 3n-1} is turned on, the node A~D is connected to the potential _{V SS.}

Subsequently, the control unit 40 supplies the first resistance value control signal sel_r [n: 1] to the first decoder 11 to select one of the gate wirings G _{11 to} G _1n . The first decoder 11 supplies a high-level drive signal to the selected gate line among the gate lines G _{11 to} G _1n based on the first resistance value control signal sel_r [n: 1]. Each of the switching elements Q ₁₁ switching elements driving signal of high level is connected to the supplied gate wiring of the to Q _1n are turned on, the connection between the resistive elements in the resistive unit corresponding to the selected gate line The point and one end of the resistance unit are connected to the relay points C _{1 to} C _m , respectively. FIG. 4 illustrates a case where the gate line G _1n is selected and each of the switching elements Q _1n connected to the gate line G _1n is turned on.

Subsequently, the control unit 40 selects one of the switching elements Q _{51 to} Q _5m by supplying a path selection signal rc [m: 1] to the third decoder 21. The third decoder 21 supplies a high-level drive signal to one of the gates of the switching elements Q _{51 to} Q _5m according to the path selection signal rc [m: 1], and turns on the switching element. 4, if there is illustrated a switching element Q ₅₁ is turned on.

As shown in FIG. 4, each switching element is turned on to pass through switching element Q _3n−1 , resistance unit R _n , switching element Q _1n , relay point C _1, and switching element Q ₅₁ . The “path 1” indicated by the broken line in FIG.

Since the high-level input signal is input to the inverter 31 by the pull-up resistor r ₃₀ , the determination output from the output terminal 32 before the path to be tested is connected to the determination output unit 30. The level of the output signal rc_out is a low level.

When the conduction state of “path 1” shown in FIG. 4 is good (that is, when there is no disconnection or the like on the path and the switching element on the path operates normally), “path 1” is When connected to the decision output unit 30, the input terminal of the inverter 31 is connected to the potential V _SS via a "route 1", the level of the decision output signal rc_out becomes high level. On the other hand, when the state of “path 1” is defective (that is, when disconnection or the like occurs on the path or the switching element on the path does not operate normally), the potential of the input terminal of the inverter 31 is Since the high level is maintained, the level of the determination output signal rc_out is maintained at the low level. That is, when the conduction state of the path to be tested is good, the level of the determination output signal rc_out transitions from the low level to the high level in synchronization with the switching operation of the switching element for selecting the path. . On the other hand, when the conduction state of the path to be tested is defective, the level of the determination output signal rc_out is kept low regardless of the switching operation of the switching element for selecting the path.

The control unit 40 sequentially shifts the gate line to be selected from the gate lines G _{11 to} G _1n by the first resistance value control signal sel_r [n: 1], and at the same time the switching element by the path selection signal rc [m: 1]. The switching elements to be selected among Q _{51 to} Q _5m are sequentially shifted, and the test target paths are sequentially switched. That is, the control unit 40 controls the switching elements Q _{51 to} Q _5m via the third decoder 21 so that the relay points connected to the determination output unit 30 are sequentially switched, and the relay points connected to the determination output unit 30 The switching elements Q _{11 to} Q _1n are controlled via the first decoder 11 so that the resistance units connected to the relay points are sequentially switched in conjunction with the switching of the first and second switches. While the paths to be tested are sequentially switched, the level of the determination output signal rc_out is constantly monitored by a tester (not shown). For example, the tester has a good conduction state of each path based on whether or not the level of the determination output signal rc_out transitions in synchronization with the switching timing of each switching element when switching the path to be tested. It is determined whether or not. In the first path test is preferably carried out for all combinations of the switching element _Q 11 _{to Q 1n} and the switching elements _Q 51 _{to Q 5 m.} In the first path test, it is possible to test the connection state between the resistance elements, the operation of the switching elements Q _{11 to} Q _1n , Q _{31 to} Q _3n−1 , Q _{51 to} Q _5m , and the like.

  FIG. 5 is a diagram illustrating an example of the second path test in the resistor array circuit 1. In FIG. 5, the switching elements that are turned on are circled and displayed.

When performing the second path test, the control unit 40 supplies the first test control signal test_1 [0] to the second decoder 12. The second decoder 12 supplies receives the first test control signal TEST_1 [0], the drive signal of the gate to the high level of each of the switching elements _{Q 31 ~Q 3n-1.} Thus, each of the switching elements _Q 31 _{~Q 3n-1} is turned on, the node A~D is connected to the potential _{V SS.}

Subsequently, the control unit 40 supplies the second resistance value control signal sel_c [m: 1] to the first decoder 11 to select one of the gate wirings G _{21 to} G _2m . Based on the second resistance value control signal sel_c [m: 1], the first decoder 11 supplies a high-level drive signal to the gate line selected from the gate lines G _{21 to} G _2m . Among the switching elements Q _{21 to} Q _2m , the switching element connected to the gate wiring to which the high-level driving signal is supplied is turned on, and the corresponding relay point (any one of C _{1 to} C _m ) is set to the potential _VSS . Connected. 5, the gate line G ₂₁ is selected, when the switching element Q ₂₁ connected to the gate line G ₂₁ is turned on is illustrated.

Subsequently, the control unit 40 supplies a path selection signal rc [m: 1] corresponding to the second resistance value control signal sel_c [m: 1] to the third decoder 21. Thus, among the switching elements Q ₅₁ to Q _{5 m,} the second resistance control signal Sel_c: corresponding to the switching element is turned on based on the [m 1] (one of the switching elements Q ₂₁ to Q _2m) The switching element to be selected is selected. The third decoder 21 supplies a high-level drive signal to one of the gates of the switching elements Q _{51 to} Q _5m according to the path selection signal rc [m: 1], and turns on the switching element. 5, if there is illustrated a switching element Q ₅₁ is turned on.

As illustrated in FIG. 5, when the switching elements Q ₂₁ and Q ₅₁ are turned on, the “path 2” indicated by the broken line in FIG. 5 passes through the switching element Q ₂₁ , the relay point C _1, and the switching element Q ₅₁ . Is connected to the inverter 31 of the determination output unit 30.

When the conduction state of “path 2” shown in FIG. 5 is good (that is, when no disconnection or the like occurs on the path and the switching element on the path operates normally), “path 2” is When connected to the decision output unit 30, the input terminal of the inverter 31 is connected to the potential V _SS via a "path 2", the level of the decision output signal rc_out becomes high level. On the other hand, when the state of “path 2” is defective (that is, when a disconnection or the like occurs on the path or the switching element on the path does not operate normally), the potential of the input terminal of the inverter 31 is Since the high level is maintained, the level of the determination output signal rc_out is maintained at the low level. That is, when the conduction state of the path to be tested is good, the level of the determination output signal rc_out transitions from the low level to the high level in synchronization with the switching operation of the switching element for selecting the path. . On the other hand, when the conduction state of the path to be tested is defective, the level of the determination output signal rc_out is kept low regardless of the switching operation of the switching element for selecting the path.

The control unit 40 sequentially shifts the gate wiring to be selected from the gate wirings G _{21 to} G _2m by the second resistance value control signal sel_c [m: 1] and at the same time the switching element by the path selection signal rc [m: 1]. The switching elements to be selected among Q _{51 to} Q _5m are sequentially shifted, and the test target paths are sequentially switched. That is, the control unit 40 controls the switching elements Q _{51 to} Q _5m via the third decoder 21 so that the relay points connected to the determination output unit 30 are sequentially switched, and the relay points connected to the determination output unit 30 conjunction with through the first decoder 11 as is sequentially switched relay points that are connected to the potential V _SS by controlling the switching element Q ₂₁ to Q _2m to the switching of. In the second path test, the control unit 40 forms a path to be tested by associating the second resistance value control signal sel_c [m: 1] with the path selection signal rc [m: 1]. To do. While the paths to be tested are sequentially switched, the level of the determination output signal rc_out is constantly monitored by a tester (not shown). For example, the tester determines whether or not the conduction state of each path is good based on whether or not the level of the determination output signal rc_out transitions in synchronization with the switching timing of each switching element for selecting the path. judge. In the second path test, it is possible to test the operations of the switching elements _Q 21 _{to Q 2m} and the switching elements _Q 51 _{to Q 5 m.}

  As described above, according to the path test of the resistance array circuit 1 according to the present embodiment, it is possible to determine the conduction state of the path to be tested based on the signal level of the determination output signal rc_out.

  The resistance value test in the resistance array circuit 1 will be described below. The resistance value test corresponds to the third test mode in the present invention.

  FIG. 6 is a diagram illustrating an example of a resistance value test in the resistor array circuit 1. In FIG. 6, the switching elements that are turned on are circled and displayed.

When the resistance value test is performed, the control unit 40 supplies the second test control signal test_2 [n: 1] to the second decoder 12 to select one of the switching elements Q _{41 to} Q _4n . Based on the second test control signal test_2 [n: 1], the second decoder 12 supplies a low-level drive signal to the gate of the switching element selected from the switching elements Q _{41 to} Q _4n . The switching element is turned on. Thus, among the resistor units R ₁ to R _n, the ends of the resistor unit connected to the switching element is turned on is connected to the potential V _DD. FIG. 6 illustrates the case where the switching element Q ₄₁ is turned on and the node F that is the end of the resistance unit R ₁ is connected to the potential V _DD .

Subsequently, the control unit 40 supplies the first resistance value control signal sel_r [n: 1] and the second resistance value control signal sel_c [m: 1] to the first decoder, whereby the gate wirings G _{11 to} G ₁₁ thereby selecting one of _1n, you select any one of the gate lines _G 21 _{~G 2m.} As a result, each switching element connected to the selected gate wiring is turned on. In FIG. 6, when gate lines G _1n and G ₂₁ are selected, each of switching elements Q _1n connected to gate line G _1n and switching element Q ₂₁ connected to gate line G ₂₁ are turned on. Is illustrated.

As shown in FIG. 6, a path indicated by a broken line in FIG. 6 passes through the resistance units R _{1 to} R _n , the switching element Q _1n , the relay point C _1, and the switching element Q ₂₁ by turning on each switching element. Current flows through This current, since it has a size corresponding to the resistance value of the potential difference and the route between the potential V _DD and the potential V _SS, by measuring a tester (not shown) the current value, the resistance value on the route Can be acquired. For example, the tester derives a determination result regarding the performance of the resistance element depending on whether the measured current value or the acquired resistance value is within a predetermined standard range.

According to the resistance array circuit 1 according to the present embodiment, the second test control signal test_2 [n: 1], the first resistance value control signal sel_r [n: 1], and the second resistance value control signal sel_c [ m: the combination of switching elements to be turned on appropriately by 1, the voltage corresponding to the potential difference between the potential V _DD and the potential V _SS to any range of resistor array originating from the one of the nodes F~J It is possible to apply. Therefore, by measuring the current flowing through the range, it is possible to obtain the resistance value of the combined resistor composed of each resistance element included in the range. That is, an arbitrary range of the resistance array starting from any one of the nodes F to J can be set as a resistance value test target. Thereby, according to the resistance array circuit 1 which concerns on this embodiment, it is possible to perform a resistance value test which is illustrated below.

For example, as shown in FIG. 6, the switching elements Q _1n and the switching elements Q ₂₁ and Q ₄₁ are turned on, so that the resistance value of the combined resistance composed of all the resistance elements r constituting the variable resistance unit 10 is obtained. It is possible to obtain. This makes it possible to easily determine whether or not the entire resistance element is formed as designed.

Further, from the state shown in FIG. 6, a first resistance control signal sel_r [n: 1] and the second resistance control signal sel_c [m: 1] by sequentially changing the, is connected to the potential V _SS By sequentially moving the points on the resistor array to the terminal T1 side, the current value may be measured while sequentially reducing the resistance elements through which the current flows. Thereby, it is possible to acquire the resistance values of all the resistance elements r constituting the variable resistance unit 10. That is, the resistance value of the reduced resistance element can be obtained from the change in the current value when one resistance element is reduced. According to such measurement, the monotonicity of the resistance value of the resistance element r can be evaluated.

Further, according to the resistance array circuit 1 according to the present embodiment, it is possible to perform a resistance value test for each resistance unit. Figure 7 is an illustrated diagram of the case where the resistance unit R ₂ performs resistance test. When the resistance unit R ₂ performs resistance test, the control unit 40, a second test control signal test_2 [n: 1] The switching element Q ₄₂ is turned on by the supply to the second decoder 12, Node G is connected to potential V _DD . The control unit 40, a first resistance control signal sel_r [n: 1] by selecting the gate line G ₁₂ corresponding to the resistance unit R _2, and turned on each of the switching elements Q _12. The control unit 40, the second resistance control signal sel_c [m: 1] by example, select gate lines G _21, the switching element Q ₂₁ is turned on. By thus to each of the switching elements turned on, one is an end node B of the resistor unit R ₂ is connected to the potential V _SS, the node G, which is the other end is connected to the potential V _DD Runode, current flows in the resistance elements r constituting a resistor unit R _2. By measuring this current, it is possible to obtain the resistance value of the combined resistance of the resistance unit R _2. Thus, the workmanship of the resistance elements constituting the resistance unit R ₂ can be easily evaluated.

FIG. 7 illustrates the case where the resistance unit is evaluated by obtaining the resistance value of the combined resistance composed of all the resistance elements included in the resistance unit. However, by selecting the gate wirings G _{21 to} G _2m , FIG. The resistance unit may be evaluated by obtaining the resistance values of some of the resistance elements included in the resistance unit. When each of the resistance units R _{1 to} R _n is a test target, the switching element (any one of the switching elements Q _{41 to} Q _4n ) selected by the second test control signal test_2 [n: 1] Are sequentially shifted, and the gate wiring (any one of the gate wirings G _{11 to} G _1n ) selected by the first resistance value control signal sel_r [n: 1] is sequentially shifted so as to correspond to this.

  As described above, according to the resistance array circuit 1 according to the embodiment of the present invention, the path test and the resistance value test can be performed independently. In the path test, the conduction state of the path to be tested can be determined based on the signal level of the determination output signal rc_out, so the test time required for the path test is significantly shorter than the test time required for the resistance value test. can do. For example, the test time in the case where the path test is performed on all paths of the resistor array composed of 10 columns × 32 rows of resistive elements arranged in a matrix is about 10 μsec. On the other hand, the test time required for the resistance value test of all 320 resistance elements is about 96 sec.

  Further, according to the resistance array circuit 1 according to the present embodiment, it is possible to perform a resistance value test for each resistance unit. Here, since the resistance value of the resistance element formed as a semiconductor integrated circuit has a correlation with the resistance value of the surrounding resistance element, the resistance values of other resistance elements are based on the resistance values of some of the resistance elements. In some cases, the resistance value can be guaranteed. That is, there is a case where quality can be guaranteed without necessarily performing resistance value tests on all the resistance elements. According to the resistance array circuit 1 according to the present embodiment, the path test and the resistance value test can be performed independently. For example, a path test with a relatively short test time is performed for all paths. As for the resistance value test, it is possible to operate only a part of the resistance elements according to the mass production results, or to perform the resistance value test for each resistance unit. As a result, it is possible to reduce the number of times the resistance value test is performed, so that it is possible to significantly reduce the time required for the resistance value test as compared with the case where the resistance value test is performed for each of all the resistance elements. Become. On the other hand, in the configuration as shown in FIG. 1 in which the path test and the resistance value test cannot be performed independently, when the path test is to be performed for all paths, the resistance value of all the resistance elements is necessarily set to 1. One test is performed, and the test time is significantly longer than that of the resistor array circuit 1 according to the embodiment of the present invention.

Further, according to the resistor array circuit 1 according to the present invention, both ends of the resistor element it is possible to apply any voltage corresponding to the potential difference between the potential V _DD and the potential V _SS. By applying a relatively high voltage to both ends of the resistance element when performing the resistance value test, the current flowing through the resistance element can be increased, so that the measurement accuracy of the resistance value can be increased.

  FIG. 8 is a block diagram showing a configuration of the current generation circuit 50 according to the embodiment of the present invention including the resistor array circuit 1.

The current generation circuit 50 includes the above-described resistance array circuit 1 that functions as a variable resistor, and a current generation unit 51 connected to the terminal T1 of the resistance array circuit 1. The potential V _DD and the potential V _SS are supplied to both the current generator 51 and the resistor array circuit 1. The terminal T2 of the resistor array circuit 1 is connected to the potential V _SS.

  The current generator 51 generates a current corresponding to the resistance value between the terminals T 1 and T 2 of the resistor array circuit 1 and outputs the current from the output terminal 52. In the resistor array circuit 1, when an instruction signal for instructing a resistance value is supplied from the outside, the control unit 40 configuring the resistor array circuit 1 uses the first resistance value control signal sel_r [n: 1 based on the instruction signal. ] And the second resistance value control signal sel_ [m: 1] are generated and supplied to the first decoder 11. Thereby, the resistance value between the terminals T1 and T2 becomes a value corresponding to the instruction signal. That is, the current generation circuit 50 according to the present embodiment can change the magnitude of the current output from the output terminal 52 by giving an instruction signal from the outside. According to the current generation circuit 50 according to the present embodiment, the path test and the resistance value test can be performed on the portion of the resistance array circuit 1 as described above.

  FIG. 9 is a block diagram showing a configuration of a current control type oscillation circuit 60 according to the embodiment of the present invention including the above-described current generation circuit 50.

  The current control type oscillation circuit 60 includes a current generation circuit 50 and an oscillator 61 connected to the output terminal 52 of the current generation circuit 50. The oscillator 61 outputs from the output terminal 62 an output signal having a frequency corresponding to the magnitude of the current supplied from the current generation circuit 50. That is, the current control type oscillation circuit 60 can change the frequency of the output signal by giving an instruction signal to the resistor array circuit 1 from the outside. According to the current control type oscillation circuit 60 according to the present embodiment, the path test and the resistance value test can be performed on the portion of the resistance array circuit 1 as described above.

  FIG. 10 is a block diagram showing a configuration of a frequency lock loop (FLL) circuit 70 according to the embodiment of the present invention including the current control type oscillation circuit 60 described above. The FLL circuit 70 includes a current control type oscillation circuit 60, a flip-flop 72, a counter 74, an adjustment unit 76 and a conversion unit 78.

  The flip-flop 72 divides the reference clock signal S 0 to generate a reference signal S 1 having a target frequency, and supplies this to the counter 74. The counter 74 supplies the adjustment unit 76 with a count value S3 obtained by counting the number of pulses of the output signal S2 output from the current control type oscillation circuit 60 using the reference signal S1 supplied from the flip-flop 72. The adjustment unit 76 generates an adjustment signal S4 so that the count value S3 corresponds to the target frequency, and supplies this to the conversion unit 78. The converter 78 converts the adjustment signal S4 into an instruction signal S5 that indicates the resistance value of the resistor array circuit 1 constituting the current control type oscillation circuit 60, and supplies this to the current control type oscillation circuit 60. The current control type oscillator 60 changes the resistance value between the terminals T1 and T2 of the resistor array circuit 1 based on the instruction signal S5, and outputs the output signal S2 adjusted to the target frequency.

  According to the FLL circuit 70 according to the present embodiment, the path test and the resistance value test can be performed on the portion of the resistor array circuit 1 constituting the current control type oscillator 60 as described above. Here, as a method of testing the performance of each resistance element of the resistor array circuit constituting the FLL circuit, a method of checking the output signal of the FLL circuit while changing the resistance value step by step can be considered. However, this requires a huge amount of test time. In the FLL circuit, a relatively long time is required until the frequency of the output signal is stabilized, and it takes about 10 seconds to confirm one frequency. Therefore, for example, if the resistance array circuit has 320 resistance elements, it takes 3200 seconds to test all the resistance elements. On the other hand, when the resistance array circuit 1 according to the embodiment of the present invention is used to form an FLL circuit and the resistance value test is performed on the portion of the resistance array circuit 1 as described above, about 300 msec per resistance element. The test is completed in about 96 seconds for 320 resistance elements. In addition, as described above, the resistance value test can be simplified by using the resistance unit as a test target instead of the individual resistance elements, so that the test time can be further shortened.

DESCRIPTION OF SYMBOLS 1 Resistance array circuit 10 Variable resistance part 11 1st decoder 12 2nd decoder 20 Path | route selection part 21 3rd decoder 30 Determination output part 30
31 Inverter 32 Output Terminal 40 Control Unit 50 Current Generation Circuit 51 Current Generation Unit 60 Current Control Type Oscillation Circuit 61 Oscillator 70 FLL Circuits C _{1 to} C _m Relay Points R ₁ to Rn Resistance Unit r Resistance Elements Q _{11 to} Q _1n , Q ₂₁ -Q _2m , Q ₃₁ -Q _3n-1 , Q ₄₁ -Q _4n , Q ₅₁ -Q _5m switching element

Claims (12)

A plurality of resistance units each including a plurality of resistance elements connected in series; a resistance array in which the plurality of resistance units are connected in series;
A plurality of first switching elements provided between each resistance element of each of the plurality of resistance units and a relay point corresponding to each resistance element;
A plurality of second switching elements provided between each of the relay points and a first potential;
A plurality of third switching elements provided between one end of each of the plurality of resistance units and the first potential;
A plurality of fourth switching elements provided between the other end of each of the plurality of resistance units and a second potential;
A plurality of fifth switching elements provided between each of the relay points and the output unit;
In the first test mode, the third switching element is controlled so that one end of the plurality of resistance units is connected to the first potential, and the relay point connected to the output unit is sequentially switched. Control means for controlling the first switching element to control the fifth switching element and sequentially switch the resistance units connected to the relay point in conjunction with switching of the relay point connected to the output unit; ,
A resistor array circuit including: A plurality of resistance units each including a plurality of resistance elements connected in series; a resistance array in which the plurality of resistance units are connected in series;
A plurality of first switching elements provided between each resistance element of each of the plurality of resistance units and a relay point corresponding to each resistance element;
A plurality of second switching elements provided between each of the relay points and a first potential;
A plurality of third switching elements provided between one end of each of the plurality of resistance units and the first potential;
A plurality of fourth switching elements provided between the other end of each of the plurality of resistance units and a second potential;
A plurality of fifth switching elements provided between each of the relay points and the output unit;
In the second test mode, the fifth switching element is controlled so that the relay points connected to the output unit are sequentially switched, and the first switching unit is interlocked with the switching of the relay points connected to the output unit. Control means for controlling the second switching element so that relay points connected to the potential are sequentially switched;
  A resistor array circuit including: A plurality of resistance units each including a plurality of resistance elements connected in series; a resistance array in which the plurality of resistance units are connected in series;
A plurality of first switching elements provided between each resistance element of each of the plurality of resistance units and a relay point corresponding to each resistance element;
A plurality of second switching elements provided between each of the relay points and a first potential;
A plurality of third switching elements provided between one end of each of the plurality of resistance units and the first potential;
A plurality of fourth switching elements provided between the other end of each of the plurality of resistance units and a second potential;
A plurality of fifth switching elements provided between each of the relay points and the output unit;
In the third test mode, the fourth switching element is controlled so that the other end of any one of the resistance units is connected to the second potential, The first switching element is controlled so that each resistance element in any one of the resistance units is connected to a corresponding relay point, and the first switching element is connected to the first potential so that any one of the relay points is connected to the first potential. Control means for controlling the two switching elements;
A resistor array circuit including: The output unit, to any one of claims 1 to 3 for outputting an output signal of the signal level corresponding to the conduction state of the route via the relay point which is connected via the switching elements of the fifth The resistor array circuit described. Wherein, in the third test mode, the to switch the range of the resistance element in which a current flows first switching element, in at least one control of the second switching element and the fourth switching element The resistance array circuit according to claim 3 , wherein the state is switched. Among the first switching elements, the gates of the switching elements connected to a common resistance unit are connected to a common gate wiring,
Wherein each of the second switching element, the resistance array circuit according to any one of claims 1 to 5 are connected to different gate lines from each other. Each gate of the third switching element is connected to a common gate wiring,
Wherein each gate of the fourth switching element, resistor array circuit according to any one of claims 1 to 6 are connected to different gate lines from each other. The output unit is
An inverter having an input terminal connected to any of the relay points by any of the fifth switching elements;
A resistance element having one terminal connected to the input terminal of the inverter and the other terminal connected to the second potential;
Resistor array circuit according to any one of claims 1 to 7 comprising a. A resistance array circuit according to any one of claims 1 to 8 ,
A current generator that is connected to the connection terminals of the resistor array circuit and generates a current having a current value corresponding to a resistance value between the connection terminals;
Including a current generation circuit. A current generation circuit according to claim 9 ;
An oscillator that outputs an output signal having a frequency corresponding to the current value of the current generated by the current generation circuit;
Current-controlled oscillator circuit. An FLL circuit comprising the current controlled oscillation circuit according to claim 10 provided in a frequency lock loop. A resistance array test method comprising a plurality of resistance units each including a plurality of resistance elements connected in series, wherein the plurality of resistance units are connected in series,
Connecting one end of the plurality of resistance units to a first potential;
Connecting each resistance element in any one of the plurality of resistance units to a corresponding relay point; and
Connecting any of the relay points to an output unit;
The output unit outputting an output signal of a level corresponding to a conduction state of a path passing through a relay point connected to the output unit;
Sequentially switching relay points connected to the output unit;
Sequentially switching the resistance units connected to the relay point in conjunction with switching of the relay point connected to the output unit;
Including test methods.