JP2006269477A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit for measuring the delay time of a built-in circuit without inputting any special signals for measuring timing from the outside. <P>SOLUTION: The semiconductor integrated circuit comprises a signal generation circuit 20 for generating a first signal input to a circuit 10 to be measured, and a second signal including a plurality of pulses for latching a signal output from the circuit to be measured; an output holding circuit 40 including a plurality of latch circuits connected in series, for successively latching signals output from the circuit to be measured in synchronism with a plurality of pulses included in the second signal; and a plurality of pads electrically connected to each output terminal of the plurality of latch circuits. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention generally relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a function of measuring a delay time of a built-in circuit.

  Conventionally, in order to measure the delay time of a circuit built in a semiconductor integrated circuit, a pad is provided at the input terminal and output terminal of the circuit, and a delay is obtained by connecting an LSI tester to these pads via a probe. Time was being measured. For example, at a strobe position where a predetermined time has elapsed since a signal was input to a circuit, the level of the signal output from the circuit is determined, and the delay time of the circuit is measured by changing the strobe position. It was.

However, low-cost LSI testers have low measurement resolution, and it is difficult to measure the delay time of a circuit that operates at high speed. In addition, since it is affected by the wiring capacity and wiring resistance of a measurement jig such as a probe and a cable connected thereto, it is difficult to perform accurate measurement. On the other hand, in recent years when the speed of circuit operation is increasing, it is desired to accurately measure a delay time on the order of 1 nanosecond.

  As a related technique, the following Patent Document 1 discloses a test circuit that can correctly measure delay characteristics of a semiconductor device without being affected by a load of wiring connecting a semiconductor device to be tested and an LSI tester. It is disclosed. According to Patent Document 1, a timing comparator is built in a semiconductor device, and this timing comparator is composed of a data latch circuit. The data latch circuit inputs a pulse signal whose timing is set for the input signal from the outside, compares the timing between the data signal output in response to the input signal and the pulse signal, and the result of the comparison A binary signal corresponding to is output. This binary signal is compared with an expected value on the LSI tester side to determine pass / fail.

However, in the test circuit of Patent Document 1, since it is necessary to input an input signal and a pulse signal whose timing is set with respect to the input signal from the outside to the semiconductor device, a signal generator for generating these signals Must be connected to the semiconductor device, and is affected by the wiring capacity and wiring resistance of the measuring jig and cable used for this purpose, making it difficult to perform accurate measurement.
Japanese Patent Laying-Open No. 2003-227864 (first page, FIG. 1)

  Therefore, in view of the above points, the present invention provides a semiconductor integrated circuit capable of measuring the delay time of a built-in circuit without inputting a special signal for timing measurement from the outside. Objective.

  In order to solve the above-described problems, a semiconductor integrated circuit according to the present invention includes a first signal input to a circuit under measurement and a plurality of pulses used for latching a signal output from the circuit under measurement. A signal generation circuit for generating a second signal including the plurality of serially connected latch circuits for sequentially latching signals output from the circuit under measurement in synchronization with a plurality of pulses included in the second signal And a plurality of pads electrically connected to the output terminals of the plurality of latch circuits.

  Here, the signal generation circuit may include a variable frequency oscillation circuit that generates a second signal by performing an oscillation operation in accordance with a control signal, or the first signal and the second signal are activated in synchronization. A logic circuit to be converted may be further included.

  Alternatively, the signal generation circuit includes a plurality of inverters that delay the input pulses with different delay times, and a circuit that generates the second signal by combining the plurality of pulses respectively output from the plurality of inverters. May be included. In that case, the semiconductor integrated circuit includes a greater number of inverters than the number of inverters in each group of the plurality of groups of inverters, and provides the input signal with a delay time measured to determine the pulse interval in the second signal. A measurement delay time generation circuit may be further provided.

  The semiconductor integrated circuit may further include a level determination circuit that compares the potential of the signal output from the circuit under test with the variable reference potential and supplies the comparison result to the output holding circuit. A plurality of groups of inverters that delay the signals to be delayed by different delay times, and a selection circuit that selects one of the plurality of signals output from the plurality of groups of inverters, respectively.

  According to the present invention, in a semiconductor integrated circuit, a signal generation circuit that generates a first signal input to a circuit under measurement and a second signal including a plurality of pulses, and a device under measurement in synchronization with the plurality of pulses By providing an output holding circuit that sequentially latches the output signal of the circuit, the delay time of the built-in circuit can be measured without inputting a special signal for timing measurement from the outside. As a result, the delay time in the semiconductor integrated circuit can be measured without being affected by the measurement resolution of the LSI tester, the wiring capacity and the wiring resistance of the measurement jig and cable.

Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram showing a configuration of a delay time measuring circuit built in a semiconductor integrated circuit according to an embodiment of the present invention. As shown in FIG. 1, in this semiconductor integrated circuit, a test signal and a strobe signal are generated together with a circuit under test 10 in which a delay time from when the input signal level changes until the output signal level changes is measured. A signal generation circuit 20, a level determination circuit 30 for determining the level of the output signal of the circuit under test 10, and a plurality of latch circuits 41, 42, 43 connected in series for sequentially latching signals output from the level determination circuit 30 ,... Includes a delay time measuring circuit constituted by an output holding circuit 40.

  The latch circuits 41, 42, 43,... Are configured by flip-flops or registers. In order to measure the outputs Q1, Q2, Q3,..., QN of these latch circuits with an LSI tester, a plurality of test pads are electrically connected to the output terminals of the latch circuits 41, 42, 43,. Connected. A test pad for observing the strobe signal STRB is also provided. The level determination circuit 30 may be omitted and the output signal of the circuit under test 10 may be directly input to the output holding circuit 40.

  In the test mode, the test signal generated by the signal generation circuit 20 is input to the circuit under test 10. The input terminal of the circuit under test 10 is connected to other circuits and input pads in addition to the signal generation circuit 20, and in the normal mode in which the signal generation circuit 20 does not operate, A signal is input from another circuit, and the signal is output to an output pad or another circuit.

  FIG. 2 is a timing chart showing the operation of the delay time measuring circuit shown in FIG. The test signal output from the signal generation circuit 20 is input to the circuit under test 10, and an output signal is output from the circuit under test 10. The strobe signal includes a plurality of pulses used to latch the output signal of the circuit under test 10. The rising edge of the test signal and the rising edge of the first pulse included in the strobe signal are synchronized with each other. The plurality of latch circuits 41, 42, 43,... Connected in series sequentially latch the output signal of the circuit under test 10 in synchronization with the plurality of pulses included in the strobe signal. In FIG. 2, the output level of the first latch circuit 41 is shown as the latch circuit output.

As shown in FIG. 2, the time interval Δt from the timing t ₁ when the test signal is activated and rises to the high level to the timing t ₂ when the output of the latch circuit 41 rises is measured as the delay time of the circuit under test 10. The According to this example, a high level latched at the timing t ₂ is, because synchronization with the last pulse included in the strobe signal appears at the output Q3 of the third latch circuit 43, the time interval Δt is, This corresponds to the cycle of two pulses of the strobe signal. Therefore, the delay time of the circuit under test 10 can be obtained by measuring the frequency or pulse interval of the strobe signal and obtaining the period of two pulses.

  FIG. 3 is a circuit diagram showing a first specific example of the signal generating circuit in FIG. The signal generation circuit 20 is based on an oscillation circuit 20a whose oscillation frequency is variable, a flip-flop 20b that generates a test signal based on the control signals S1a and S1b, a control signal S1b, and an oscillation signal from the oscillation circuit 20a. And a NAND circuit 20c for generating a strobe signal.

  The oscillation circuit 20a includes a NAND circuit 21, two inverters 22 and 23, two resistors R1 and R2, and a capacitor C. The oscillation frequency of the oscillation circuit 20a is determined by the value of the resistor R2 and the value of the capacitor C. The resistor R1 is a protective resistor. In this example, the resistor R2 is a variable resistance circuit as shown in FIG. 4, and the oscillation frequency of the oscillation circuit 20a can be controlled by the control signals S2a, S2b,.

  That is, when the control signal S2a becomes high level, the output of the inverter 25 becomes low level, and high level and low level signals are applied to the gates of the N channel MOS transistor QN11 and the P channel MOS transistor QP11 constituting the analog switch, respectively. Thus, the transistors QN11 and QP11 are turned on. Thereby, the resistor Ra is connected between the node N1 and the node N2.

  Similarly, when the control signal S2b becomes high level, the output of the inverter 26 becomes low level, and high level and low level signals are respectively applied to the gates of the N channel MOS transistor QN12 and the P channel MOS transistor QP12 constituting the analog switch. Thus, the transistors QN12 and QP12 are turned on. Thereby, the resistor Rb is connected between the node N1 and the node N2.

  In this way, a desired resistance among the resistances Ra, Rb,... Is connected between the node N1 and the node N2, thereby realizing a plurality of types of resistance values in the resistance R2 shown in FIG. This determines the oscillation frequency of the oscillation circuit 20a. By measuring the oscillation frequency of the oscillation circuit 20a, the pulse interval in the strobe signal can be obtained.

Referring to FIG. 3 again, when the control signal S1a shown in FIG. 3 becomes high level, the oscillation circuit 20a starts oscillating and the reset of the flip-flop 20b is released. The power supply potential V _DD is applied to the data input terminal of the flip-flop 20b, and the flip-flop 20b activates the test signal to high level in synchronization with the rising edge of the control signal S1b. When the control signal S1b becomes high level, the NAND circuit 20c outputs the oscillation signal of the oscillation circuit 20a as a strobe signal. The test signal propagates to the circuit under test 10 shown in FIG. 1, and the strobe signal propagates to the output holding circuit 40 shown in FIG. Thereafter, when the control signals S1a and S1b become low level, the oscillation circuit 20a stops oscillating, the flip-flop 20b is reset and the test signal is deactivated to low level, and the NAND circuit 20c stops outputting the strobe signal. To do.

  FIG. 5 is a circuit diagram showing a second specific example of the signal generating circuit in FIG. The signal generation circuit 20 includes a delay circuit 51, an exclusive OR circuit 52, a one-pulse generation circuit 54 configured by an AND circuit 53, and a plurality of delay circuits 55a, 55b, 55c each including a plurality of inverters. , And an OR circuit 56. Further, a measurement delay time generation circuit 57 is built in the semiconductor integrated circuit.

  In the one-pulse generation circuit 54, the delay circuit 51 is realized by gate delay of a plurality of logic gates. The exclusive OR circuit 52 obtains an exclusive OR of the test signal and the delayed test signal, thereby detecting the edge of the test signal and generating a pulse. The AND circuit 53 outputs a pulse generated by the exclusive OR circuit 52 while the test signal is at a high level. As a result, one pulse synchronized with the rising edge of the test signal is output from the one-pulse generation circuit 54.

  The pulses output from the one-pulse generation circuit 54 are given delays by a plurality of delay circuits 55a, 55b, 55c,. The number of inverters differs between adjacent delay circuits by a predetermined even number ΔM. Accordingly, a plurality of pulses are output from the plurality of delay circuits 55a, 55b, 55c,. These pulses are synthesized by the OR circuit 56, and a strobe signal including a plurality of pulses at equal intervals is generated.

  On the other hand, when the delay time is measured, the test signal is fixed at a low level, and the delay time measurement signal is input to the measurement delay time generation circuit 57. The measurement delay time generation circuit 57 has M inverters, which is larger than the number of inverters in each delay circuit, and gives a delay time to be measured in order to obtain a pulse interval in the strobe signal. The delay time measurement signal input to the measurement delay time generation circuit 57 is delayed by M inverters and output from the OR circuit 56. Since the delay time in the measurement delay time generation circuit 57 having a large number of inverters is large, the measurement can be easily performed using a normal LSI tester. Based on the delay time measured for the M inverters, the delay time by ΔM inverters, that is, the pulse interval in the strobe signal can be obtained.

  FIG. 6 is a circuit diagram showing a specific example of the level determination circuit in FIG. The level determination circuit 30 compares a potential of a signal output from the circuit under test 10 with a reference potential generated by the variable reference voltage source 31, and a variable reference voltage source 31 that generates an adjustable reference potential. And a comparator 32 for supplying the comparison result to the output holding circuit 40. When such a level determination circuit 30 is used, it is possible to accurately adjust the reference potential when determining whether the signal output from the circuit under test 10 is at a high level or a low level. it can.

  FIG. 7 is a circuit diagram showing a configuration of a delay time adjustment circuit built in the semiconductor integrated circuit according to one embodiment of the present invention. This delay time adjustment circuit can select one delay time from a plurality of delay times according to the selection signals S3a, S3b, S3c,. By using the delay time adjusting circuit as the circuit under test 10 shown in FIG. 1, it is possible to check the operation of the delay time measuring circuit used in the test mode. Alternatively, the delay time required in the normal mode is adjusted by the delay time adjustment circuit based on the delay time measured using the delay time measurement circuit.

  As shown in FIG. 7, this delay time adjusting circuit includes a plurality of delay circuits 60a, 60b, 60c,... Each composed of a plurality of inverters, and each includes a P-channel transistor, an N-channel transistor, and an inverter. And a plurality of analog switches configured to input a signal from an input pad or other circuit and output a signal to the output pad or other circuit.

  For example, when the selection signal S3a becomes high level, the output of the inverter 61 becomes low level, and high level and low level signals are respectively applied to the gates of the N channel MOS transistor QN21 and the P channel MOS transistor QP21 constituting the analog switch. Thus, the transistors QN21 and QP21 are turned on. As a result, the signal delayed by the delay circuit 60a is output from the delay time adjustment circuit.

  When the selection signal S3b becomes high level, the output of the inverter 62 becomes low level, and high level and low level signals are applied to the gates of the N channel MOS transistor QN22 and the P channel MOS transistor QP22 constituting the analog switch, respectively. Thus, the transistors QN22 and QP22 are turned on. As a result, the signal delayed by the delay circuit 60b is output from the delay time adjustment circuit.

  Similarly, when the selection signal S3c becomes high level, the output of the inverter 63 becomes low level, and high level and low level signals are respectively applied to the gates of the N channel MOS transistor QN23 and the P channel MOS transistor QP23 constituting the analog switch. Thus, the transistors QN23 and QP23 are turned on. As a result, the signal delayed by the delay circuit 60c is output from the delay time adjustment circuit.

  In this way, a desired delay time is selected in the delay time adjustment circuit. As a result, the operation of the delay time measurement circuit is checked, or the delay time is accurately adjusted based on the delay time measured using the delay time measurement circuit.

The block diagram which shows the structure of the delay time measuring circuit in one Embodiment of this invention. 2 is a timing chart showing the operation of the delay time measuring circuit shown in FIG. FIG. 2 is a circuit diagram showing a first specific example of a signal generation circuit in FIG. 1. The circuit diagram which shows the variable resistance circuit in FIG. The circuit diagram which shows the 2nd specific example of the signal generation circuit in FIG. FIG. 2 is a circuit diagram showing a specific example of a level determination circuit in FIG. 1. The circuit diagram which shows the structure of the delay time adjustment circuit in one Embodiment of this invention.

Explanation of symbols

  10 circuit under test, 20 signal generation circuit, 20a oscillation circuit, 20b flip-flop, 20c, 21 NAND circuit, 22, 23, 25, 26 inverter, 30 level determination circuit, 31 variable reference voltage source, 32 comparator, 40 output Holding circuit, 41, 42, 43, ... Latch circuit, 51 Delay circuit, 52 Exclusive OR circuit, 53 AND circuit, 54 One-pulse generation circuit, 55a, 55b, 55c, ... Delay circuit, 56 OR circuit, 57 Delay time generation circuit for measurement, 60a, 60b, 60c, ... delay circuit, 61-63 inverter, R1, R2 resistor, C capacitor, QP11-QP23 P channel MOS transistor, QN11-QN23 N channel MOS transistor

Claims (7)

A signal generating circuit for generating a first signal input to the circuit under test and a second signal including a plurality of pulses used to latch the signal output from the circuit under test;
An output holding circuit including a plurality of serially connected latch circuits that sequentially latch signals output from the circuit under test in synchronization with a plurality of pulses included in the second signal;
A plurality of pads respectively electrically connected to output terminals of the plurality of latch circuits;
A semiconductor integrated circuit comprising:   The semiconductor integrated circuit according to claim 1, wherein the signal generation circuit includes a frequency variable oscillation circuit that generates the second signal by performing an oscillation operation in accordance with a control signal.   The semiconductor integrated circuit according to claim 2, wherein the signal generation circuit further includes a logic circuit that activates the first signal and the second signal in synchronization.   A circuit for generating a second signal by combining a plurality of groups of inverters for delaying input pulses with different delay times and a plurality of pulses respectively output from the plurality of inverters; The semiconductor integrated circuit according to claim 1, comprising:   A measurement delay time generation circuit including a greater number of inverters than the number of inverters in each group of the plurality of groups of inverters, and providing a delay time measured to obtain a pulse interval in the second signal to an input signal; The semiconductor integrated circuit according to claim 4, further comprising:   The level determination circuit according to claim 1, further comprising a level determination circuit that compares a potential of a signal output from the circuit under measurement with a variable reference potential and supplies a comparison result to the output holding circuit. Semiconductor integrated circuit. A plurality of inverters for delaying input signals with different delay times; and
A selection circuit for selecting one of a plurality of signals respectively output from the plurality of groups of inverters;
The semiconductor integrated circuit according to claim 1, further comprising:

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