JP2006071290A - Semi-conductor testing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semi-conductor testing device capable of performing timing calibration using a timing calibration means having one analog comparator. <P>SOLUTION: The semi-conductor testing device applies positive and negative polar differential signals and a single signal as test signals to a DUT. As the timing calibration means of these test signals, a common analog comparator for detecting a cross point of the differential signals and comparing the single signal with a reference voltage is provided. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor test apparatus, and more particularly, to an improvement in a timing calibration circuit for adjusting a timing relationship of test signals supplied to a semiconductor to be measured (hereinafter referred to as DUT) with high accuracy.

  Patent Document 1 discloses a configuration of an apparatus that generates a signal capable of more accurate timing control as a differential signal applied to a DUT.

JP-A-11-38086

  Some DUTs have a differential signal input pin and a single signal input pin. FIG. 2 is a connection conceptual diagram in such a DUT test. The differential signal input pins and the single signal input pins of the DUT 100 are connected to the pattern signal generator 210 of the semiconductor test apparatus 200 via the variable delay circuit 220 and the differential pin driver 230 or the single pin driver 240 for testing. Differential signal and single signal are input.

  At this time, the semiconductor test apparatus 200 is configured so that the timings of the differential signal and the single signal applied to the differential signal input pin and the single signal input pin of the DUT 100 are in an optimal time relationship according to the timing of the strobe signal. It is necessary to adjust and control the delay amount of the variable delay circuit 220 provided in the signal system with high accuracy.

  Therefore, as shown in FIG. 3, a timing calibration circuit 300 is connected instead of the DUT 100 to control the delay amount of the variable delay circuit 220. In FIG. 3, a differential signal or a single signal is input from the pattern signal generator 210 of the semiconductor test apparatus 200 to the differential pin driver 230 or the single pin driver 240 via the variable delay circuit 220, respectively. A plurality of n types of positive differential signals output from the positive output terminal of the differential pin driver 230 are input to one input terminal of the analog comparator 302 via the relay tournament 301, and the negative polarity of the differential pin driver 230. A plurality of n types of negative differential signals output from the output terminal are input to the other input terminal of the analog comparator 302 via the relay tournament 303. A plurality of m single signals output from the single pin driver 240 are input to one input terminal of the analog comparator 305 via the relay tournament 304. A reference voltage is input to the other input terminal of the analog comparator 305.

  The output signal of the analog comparator 302 is input to one input terminal of the multiplexer 306, and the output signal of the analog comparator 305 is input to the other input terminal of the multiplexer 306.

  The multiplexer 306 is controlled to be switched so that one of the output signals of the analog comparators 302 and 305 is selected and output to the flip-flop 307 by a control signal (not shown). When the output signal of the comparator 302 is selected and a single signal is output, the output signal of the analog comparator 305 is selected.

  The output signal of the multiplexer 306 is input to one input terminal of the digital comparator 308 through a flip-flop 307 latched by a strobe signal. An expected value signal output from the pattern signal generator 210 is input to the other input terminal of the digital comparator 308. The digital comparator 308 outputs a determination value for the output signal of the multiplexer 306 latched by the flip-flop 307.

  In such a configuration, the delay amount of the variable delay circuit 220 provided in each signal system is adjusted so that the determination value of the digital comparator 308 is inverted at the timing latched in the flip-flop 307 by the strobe signal.

  4A and 4B are timing charts for explaining the adjustment of the delay amount in the case of a differential signal. FIG. 4A shows a change in the data string for setting the delay amount of the variable delay circuit 210, and FIG. 4B shows an analog comparator. 302 shows the output of 302 or 305, (c) shows the strobe signal input to the flip-flop 307, (c) shows the strobe signal input to the flip-flop 307, and (d) shows the output of the flip-flop 307. (E) shows the judgment value output of the digital comparator 308. The relay tournaments 301 and 303 select the differential signal 1 pin, and the multiplexer 306 selects the output of the analog comparator 302. Then, the data for setting the delay amount of the variable delay circuit 220 of the differential signal 1-pin system is changed in the order of A → B → C → D → E → F → G → H. The output timing of the analog comparator 302 also changes according to the change in the delay amount setting value of the variable delay circuit 210, and the output of the analog comparator 302 is latched in the flip-flop 307 by the strobe signal. The output of the analog comparator 302 latched in the flip-flop 307 is compared with an expected value by the digital comparator 308. Here, assuming that the expected value is, for example, Low, the determination value changes from Fail to Pass when the delay amount setting value is F. Therefore, the delay amount calibration result of the variable delay circuit 210 of the differential signal 1-pin system is F It becomes.

  Such a series of delay amount setting adjustment is performed for the differential signal from the 1-pin system to the n-pin system and the single signal from the 1001-pin system to the m-pin system, thereby adjusting the timing of the semiconductor test apparatus 200. .

However, since the circuit configuration of FIG. 3 uses two analog comparators 302 and 305, timing adjustment must be performed in a state including timing skew caused by characteristic variation between the two analog comparators. In other words, adjustment man-hours are required.
In addition, there is a problem that the number of parts increases, the configuration becomes complicated, and the cost increases.

  The present invention solves such a conventional problem, and an object of the present invention is to provide a semiconductor test apparatus capable of performing timing calibration using timing calibration means having one analog comparator.

In order to achieve such a problem, the invention according to claim 1 of the present invention is:
In a semiconductor test apparatus that applies a positive / negative differential signal and a single signal to a DUT as test signals,
As a timing calibration means for these test signals, a common analog comparator for performing cross-point detection of a differential signal and comparing a single signal with a reference voltage is provided.

According to a second aspect of the present invention, in the semiconductor test apparatus of the first aspect,
A means for selecting a differential signal and a single signal is provided in the preceding stage of the common analog comparator.

According to a third aspect of the present invention, in the semiconductor test apparatus of the second aspect,
The means for selecting the differential signal and the single signal is composed of two selection circuits that are switched and controlled in conjunction with each other.
In differential signal selection, a positive differential signal is selectively output from one selection circuit, and a negative differential signal is selectively output from the other selection circuit.
In selecting a single signal, a single signal is selectively output from one selection circuit, and a reference voltage is selectively output from the other selection circuit.

  According to the present invention, the timing calibration of the test signal applied to the DUT can be performed based on the output of one analog comparator.

  Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a specific example of a timing calibration circuit according to the present invention, and the same reference numerals are given to the parts common to FIG. In FIG. 1, a plurality of n positive polarity differential signals output from the pattern signal generator 210 are input to one input terminal of the first multiplexer 309 via the relay tournament 301, and the other input terminal is connected to the other input terminal. A plurality of m lines of single signals output from the pattern signal generator 210 are input via the relay tournament 304.

  A plurality of n types of negative differential signals output from the pattern signal generator are input to one input terminal of the second multiplexer 310 via the relay tournament 303, and a reference voltage is input to the other input terminal. ing.

  These multiplexers 309 and 310 are switched and controlled in conjunction with each other by a control signal (not shown). That is, when a differential signal is output, a positive differential signal is selectively output from the multiplexer 309 and a negative differential signal is selectively output from the multiplexer 310, and when a single signal is output, a single signal is selected from the multiplexer 309. The reference voltage is selectively output from the multiplexer 310. These multiplexers 309 and 310 are, for example, those configured as relay selection circuits.

  The output signal of the multiplexer 309 is input to one input terminal of the analog comparator 311, and the output signal of the multiplexer 310 is input to the other input terminal.

  The output signal of the analog comparator 311 is input to one input terminal of the digital comparator 308 via a flip-flop 307 that is latched by a strobe signal.

  An expected value signal output from the pattern signal generator 210 is input to the other input terminal of the digital comparator 308. The digital comparator 308 outputs a determination value for the output signal of the analog comparator 311 latched by the flip-flop 307.

  In such a configuration, the determination value of the digital comparator 308 is inverted at the timing latched in the flip-flop 307 by the strobe signal based on the timing chart illustrating the adjustment of the delay amount shown in FIG. 4 similar to the configuration of FIG. In addition, the delay amount of the variable delay circuit 220 provided in each signal system of the semiconductor test apparatus 200 is adjusted.

  Here, since the differential signal and the single signal are selected by the multiplexers 309 and 310 before being input to the analog comparator 311, only one analog comparator 311 is necessary, and two conventional analog comparators are required. It is possible to eliminate the timing skew caused by the variation between the signals and to efficiently adjust the timing between signals.

  In addition, the timing calibration circuit can be realized with a lower-cost configuration than before, which is beneficial for reducing the cost of the semiconductor test apparatus.

It is a block diagram which shows the specific example of the timing calibration circuit based on this invention. It is a connection conceptual diagram in the test of DUT which has a differential signal input pin and a single signal input pin. It is a block diagram which shows an example of the conventional timing calibration circuit. It is a timing chart explaining adjustment of delay amount.

Explanation of symbols

100 DUT
200 Semiconductor Test Equipment 210 Pattern Signal Generator 220 Variable Delay Circuit 230 Differential Pin Driver 240 Single Pin Driver 300 Timing Calibration Circuit 301 Positive Differential Signal Relay Tournaments 302, 305, 311 Analog Comparator 303 Negative Differential Signal Relay Tournament 304 Single relay tournament 307 Flip-flop 308 Digital comparators 306, 309, 310 Multiplexer

Claims (3)

In a semiconductor test apparatus that applies a positive / negative differential signal and a single signal to a DUT as test signals,
A semiconductor test apparatus characterized by providing a common analog comparator for detecting a cross point of a differential signal and comparing a single signal with a reference voltage as timing calibration means for these test signals.   2. The semiconductor test apparatus according to claim 1, wherein means for selecting a differential signal and a single signal is provided in front of the common analog comparator. The means for selecting the differential signal and the single signal is composed of two selection circuits that are switched and controlled in conjunction with each other.
In differential signal selection, a positive differential signal is selectively output from one selection circuit, and a negative differential signal is selectively output from the other selection circuit.
3. The semiconductor test apparatus according to claim 2, wherein in selecting a single signal, a single signal is selectively output from one selection circuit and a reference voltage is selectively output from the other selection circuit.

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