JP2007187489A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To evade the number of external terminals of the semiconductor circuit from increasing when performing the control of test switches, supplying impressing signals for measurement, and outputting measurement results, at the external test of the semiconductor integration circuit provided with built in a plurality of analogue circuit blocks. <P>SOLUTION: By a test mode designation signal (Norm/Test Mode), a semiconductor integration circuit (IC_Chip) is set to the test mode. To a plurality of analogue circuit blocks (Anlg_Cir1... Anlg_CirN), a plurality of switching circuits for testing (Tcnt_Sw1... Tcnt_SwN) for switching the signal paths from normal signal path in the test mode to that in the normal operation mode are connected. The test control interface circuit (Tcnt_Int) which is serially transmitted from outside with the control signal DI of a plurality of bits activates a plurality of switching circuits sequentially. In a plurality of analogue circuit blocks, the supply of the impressed signal for external measurement Tfd and control of the output of the measurement results Tdet are performed in order. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a technique useful for enabling an external test of a semiconductor integrated circuit containing an analog circuit.

  A semiconductor integrated circuit incorporating an analog circuit tends to incorporate an external circuit element of the semiconductor integrated circuit inside a semiconductor chip due to the advancement of analog circuit technology. As a result, the cost of the system on which the semiconductor integrated circuit is mounted is reduced, and the external circuit elements are reduced to improve the compactness and reliability of the system.

  On the other hand, as described in Non-Patent Document 1 below, a test technique (DFT; Design− for inserting a switch for facilitating an external test between a plurality of analog circuit blocks of an analog semiconductor integrated circuit. for-Test). The plurality of analog circuit blocks are connected in series on one signal path in the normal operation mode. The connection between the two analog circuit blocks is broken, and two series-connected test switches are inserted at the one break point. Two test switches inserted in series between two analog circuit blocks and connected in series are connected to a test bus. The test switch is controlled by two flip-flops connected in series on a digital control line provided in parallel with the test bus. One output of the two analog circuit blocks is separated from the signal path of the normal operation mode by one of the test switches. The other input of the two analog circuit blocks is connected to the test bus by the other of the test switches. In this manner, the other analog circuit block can be externally tested via the test bus and the other test switch independently of the one analog circuit block.

A. H. Bratt et al, "A Design-For-Test Structure for Optimizing Analogue and Mixed Signal IC Test" European Design and Test Conference. ED & TC 1995 Proceedings, 6-9 March 1995 PP. 24-33.

  Prior to the present invention, the present inventors conducted the following studies prior to the present invention.

  That is, prior to the present invention, the inventors have developed such that an external circuit element of a semiconductor integrated circuit is built in a semiconductor chip. This external circuit element is a passive element such as a voltage dividing resistor connected to the differential amplifier in the semiconductor chip and a capacitor and a resistor constituting a phase compensation circuit for preventing oscillation of the differential amplifier. However, by incorporating these passive elements inside the semiconductor chip, the inverting input terminal, the non-inverting input terminal, and the output terminal of the differential amplifier inside the semiconductor chip are not directly led out to the outside of the semiconductor chip. On the other hand, in the conventional product, the inverting input terminal, the non-inverting input terminal and the output terminal of the differential amplifier inside the semiconductor chip are directly led out of the semiconductor chip. Another important characteristic of the differential amplifier is the differential input offset voltage. In an ideal differential amplifier, when the differential input potential difference between the inverting input terminal and the non-inverting input terminal is zero volts, the currents of the two differential transistors of the differential amplifier are equally balanced. However, due to the uneven characteristics of the two differential transistors, the differential input potential difference in which the currents of the two differential transistors are balanced equally is a differential input offset voltage that is not zero volts. In actual post-production testing of a product, when the differential input offset voltage of the product is smaller than an allowable value, the product is shipped as a non-defective product, and when it is larger than the allowable value, the product is screened as a defective product. Since the inverting input terminal, non-inverting input terminal and output terminal of the differential amplifier inside the semiconductor chip are directly derived to the outside of the semiconductor chip, the differential input offset voltage test is performed by an external automatic test device in the conventional product. It was easy to do. However, since the passive element is built in the semiconductor chip, the inverting input terminal, the non-inverting input terminal, and the output terminal of the differential amplifier in the semiconductor chip are not directly led out of the semiconductor chip in the developed product. As a result, it became clear that the developed product could not easily test the differential input offset voltage using an external automatic test equipment. In the differential input offset voltage test, the applied voltage for measurement is supplied from the outside to the non-inverting input terminal of the differential amplifier, while the output voltage of the measurement result from the short-circuited connection node between the inverting input terminal and the output terminal is used. It is necessary to output. However, the developed product cannot supply the measurement applied voltage to the non-inverting input terminal and output the measurement result from the short-circuited node.

  The DFT technique proposed in Non-Patent Document 1 tests one analog circuit block from the outside by separating each of a plurality of analog circuit blocks of an analog semiconductor integrated circuit by a test switch. . However, there is no description in Non-Patent Document 1 regarding the response to the difficulty in supplying the measurement applied voltage and outputting the measurement result due to the incorporation of the passive element inside the semiconductor chip.

  Further, when the semiconductor integrated circuit includes a plurality of analog circuit blocks that are not connected in series on one signal path in the normal operation mode, supply and measurement of a measurement applied voltage for a plurality of analog circuit blocks that are not connected in series The non-patent document 1 does not describe how to output the result from the outside of the semiconductor integrated circuit. The simplest method is to execute the supply of the measurement applied voltage and the output of the measurement result of the plurality of non-series-connected analog circuit blocks in parallel from the plurality of external terminals of the semiconductor integrated circuit. However, even in this simple method, the problem that the number of external terminals of the semiconductor integrated circuit increases and the cost of the semiconductor integrated circuit increases is clarified.

  Therefore, the present invention has been made on the basis of the results of the above-described background art studies by the present inventors. Accordingly, it is an object of the present invention to control a test switch, supply a measurement application signal, and output a measurement result when testing a semiconductor integrated circuit including a plurality of non-series-connected analog circuit blocks from the outside. This is to avoid an increase in the number of external terminals of the semiconductor integrated circuit when the control is executed from the outside of the semiconductor integrated circuit. Another object of the present invention is to avoid the high cost of a semiconductor integrated circuit.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows.

  That is, the semiconductor integrated circuit (IC_Chip) according to one embodiment of the present invention has two operation modes, a normal operation mode and a test mode. In response to a test mode designation signal (Norm / Test Mode) supplied from the outside of the semiconductor integrated circuit (IC_Chip), the semiconductor integrated circuit (IC_Chip) is set to the operation mode of the test mode. The semiconductor integrated circuit (IC_Chip) includes a plurality of analog circuit blocks (Anlg_Cir1... Anlg_CirN) connected in non-series on one signal path in the normal operation mode. Each of the plurality of analog circuit blocks (Anlg_Cir1... Anlg_CirN) includes a differential amplifier (DA1) and a plurality of resistors (R11, R12, R13) constituting, for example, a voltage dividing circuit connected to the differential amplifier (DA1). And capacitors (C11, C12) constituting a phase compensation circuit for preventing oscillation connected to the differential amplifier (DA1). In the plurality of analog circuit blocks (Anlg_Cir1... Anlg_CirN), a plurality of test switch circuits (Tcnt_Sw1. It is connected. The semiconductor integrated circuit (IC_Chip) includes a test control interface circuit (Tcnt_Int) connected to a plurality of test switch circuits (Tcnt_Sw1... Tcnt_SwN). In the test mode operation mode, the plurality of test switch circuits (Tcnt_Sw1... Tcnt_SwN) are controlled from the outside of the semiconductor integrated circuit (IC_Chip) via the test control interface circuit (Tcnt_Int). In the operation mode of the test mode, the test control interface circuit (Tcnt_Int) sequentially activates a plurality of test switch circuits (Tcnt_Sw1 ... Tcnt_SwN) connected to the plurality of analog circuit blocks (Anlg_Cir1... Anlg_CirN). Accordingly, in the plurality of analog circuit blocks (Anlg_Cir1... Anlg_CirN), the supply of the measurement application signal (Tfd) from the outside of the semiconductor integrated circuit (IC_Chip) and the measurement result (Tdet) of the semiconductor integrated circuit (IC_Chip) in order Control of output to the outside is executed. Further, in each test of the plurality of analog circuit blocks (Anlg_Cir1... Anlg_CirN), the test control interface circuit (Tcnt_Int) receives a multi-bit test control signal (DI) serially transferred from the outside.

  According to the means of the first aspect of the present invention, in the plurality of analog circuit blocks (Anlg_Cir1... Anlg_CirN), the supply of the measurement application signal (Tfd) and the control of the output of the measurement result (Tdet) are sequentially performed from the outside. In each test of the plurality of analog circuit blocks (Anlg_Cir1... Anlg_CirN), the test control interface circuit (Tcnt_Int) receives a multi-bit test control signal (DI) serially transferred from the outside. Therefore, an increase in the number of external terminals of the semiconductor integrated circuit can be avoided during a test from the outside of the semiconductor integrated circuit incorporating a plurality of non-series-connected analog circuit blocks (FIGS. 1, 2, 3, and 5). 4).

  In a specific form of the present invention, the multi-bit test control signal (DI) is used to supply the measurement application signal and to output the measurement result in the test of each analog circuit block of the plurality of analog circuit blocks (Anlg_Cir1... Anlg_CirN). A switch control bit for controlling on / off of a plurality of test switches (TSW11 ... TSW14) constituting one test switch circuit (Tcnt_Sw1) of a plurality of test switch circuits (Tcnt_Sw1 ... Tcnt_SwN) for output control Information (TSCBI) is included (see FIGS. 1, 2, 3, and 4).

  In a specific form of the present invention, the test control signal (DI) of a plurality of bits includes test target bit information (which designates which analog circuit block of a plurality of analog circuit blocks (Anlg_Cir1... Anlg_CirN) is a test target) TTBI) (see FIGS. 1, 2, 3, and 4).

  In a specific form of the present invention, a plurality of test control circuits (Tcnt1... TcntN) are connected between the test control interface circuit (Tcnt_Int) and the plurality of test switch circuits (Tcnt_Sw1... Tcnt_SwN). Each of the test control circuits (Tcnt1... TcntN) controls on / off of the plurality of test switches (TSW11... TSW14) constituting each of the plurality of test switch circuits (Tcnt_Sw1... Tcnt_SwN) (FIG. 1, FIG. 2, see FIG. 3 and FIG.

  In a specific form of the present invention, the multi-bit test control signal (DI) serially transferred from the outside to the test control interface circuit (Tcnt_Int) is synchronized with a clock signal (CLK) having a substantially constant frequency from the outside. Transferred. As a result, it is possible to improve noise resistance when setting test conditions (see FIGS. 1, 2, 3, and 4).

  In a more specific form of the present invention, in the test mode operation mode, the test control interface circuit (Tcnt_Int) is externally synchronized with the clock signal (CLK) having a substantially constant frequency and has a plurality of bits of test control signal (DI). Are serially transferred, a strobe signal of a predetermined level is supplied to the test control interface circuit (Tcnt_Int). The predetermined level strobe signal is, for example, a high level chip selection signal (CS). As a result, the test control interface circuit (Tcnt_Int) is supplied with a chip selection signal (CS), a clock signal (CLK) having a substantially constant frequency, and a multi-bit test control signal (DI) for serial transfer. . Therefore, the test control interface circuit (Tcnt_Int) is a so-called three-wire serial interface, and can improve noise resistance when setting test conditions (see FIGS. 1, 2, 3, and 4). .

  In another more specific form of the present invention, the external terminal (T3) of the test control interface circuit (Tcnt_Int) to which the multi-bit test control signal (DI) is serially transferred in the operation mode of the test mode is connected to the normal operation mode. This is a common pin with the external signal terminal of the normal circuit (Log_Cir) inside the semiconductor integrated circuit (IC_Chip). Therefore, in the test from the outside of the semiconductor integrated circuit incorporating a plurality of non-series-connected analog circuit blocks, an increase in the number of external terminals of the semiconductor integrated circuit can be avoided (see FIG. 5).

In another more specific form of the present invention, the plurality of analog circuit blocks (Anlg_Cir1... Anlg_CirN) can be operated in parallel in the normal operation mode, and the plurality of analog circuit blocks (Anlg_Cir1... Anlg_CirN) can output a plurality of outputs (V _OUT1 ... V _OUTn ) in parallel (see FIG. 1).

  A semiconductor integrated circuit (IC_Chip) according to another embodiment of the present invention also has two operation modes, a normal operation mode and a test mode. In response to a test mode designation signal (Norm / Test Mode) supplied from the outside of the semiconductor integrated circuit (IC_Chip), the semiconductor integrated circuit (IC_Chip) is set to the operation mode of the test mode. The semiconductor integrated circuit (IC_Chip) includes a plurality of analog circuit blocks (Anlg_Cir1... Anlg_CirN) connected in non-series on one signal path in the normal operation mode. The plurality of analog circuit blocks (Anlg_Cir1... Anlg_CirN) have a plurality of test switch circuits (Tcnt_Sw1... Tcnt_SwN) for switching between a signal path in the test mode (IC_Chip) of the semiconductor integrated circuit and a signal path in the normal operation mode. It is connected. The semiconductor integrated circuit (IC_Chip) includes a test control interface circuit (Tcnt_Int) connected to a plurality of test switch circuits (Tcnt_Sw1... Tcnt_SwN). In the test mode operation mode, the plurality of test switch circuits (Tcnt_Sw1... Tcnt_SwN) are controlled from the outside of the semiconductor integrated circuit (IC_Chip) via the test control interface circuit (Tcnt_Int). In the operation mode of the test mode, the test control interface circuit (Tcnt_Int) sequentially activates a plurality of test switch circuits (Tcnt_Sw1... Tcnt_SwN) connected to the plurality of analog circuit blocks (Anlg_Cir1... Anlg_CirN). Accordingly, in the plurality of analog circuit blocks (Anlg_Cir1... Anlg_CirN), the supply of the measurement application signal (Tfd) from the outside of the semiconductor integrated circuit (IC_Chip) and the measurement result (Tdet) of the semiconductor integrated circuit (IC_Chip) in turn. Control of output to the outside is executed. Further, in each test of the plurality of analog circuit blocks (Anlg_Cir1... Anlg_CirN), the test control interface circuit (Tcnt_Int) receives a multi-bit test control signal (DI) serially transferred from the outside.

  According to the means of the other aspect of the present invention, in the plurality of analog circuit blocks (Anlg_Cir1... Anlg_CirN), the supply of the measurement application signal (Tfd) and the output of the measurement result (Tdet) are controlled in order from the outside. The test control interface circuit (Tcnt_Int) receives a multi-bit test control signal (DI) serially transferred from the outside in each test of the plurality of analog circuit blocks (Anlg_Cir1... Anlg_CirN). Therefore, in the test from the outside of the semiconductor integrated circuit incorporating a plurality of non-series-connected analog circuit blocks, an increase in the number of external terminals of the semiconductor integrated circuit can be avoided (see FIG. 5).

  Furthermore, in another specific form of the present invention, the external terminal (T3) of the test control interface circuit (Tcnt_Int) to which a plurality of bits of the test control signal (DI) is serially transferred in the operation mode of the test mode, This pin is shared with the external signal terminal of the normal circuit (Log_Cir) inside the semiconductor integrated circuit (IC_Chip) in the normal operation mode. Therefore, in the test from the outside of the semiconductor integrated circuit incorporating a plurality of non-series-connected analog circuit blocks, an increase in the number of external terminals of the semiconductor integrated circuit can be avoided (see FIG. 5).

  In another specific form of the present invention, a strobe signal (CS) having a predetermined level and a clock signal (CLK) having a substantially constant frequency are respectively supplied from the outside to the test control interface circuit (Tcnt_Int) in the operation mode of the test mode. The external terminals (T1, T2) of the supplied test control interface circuit (Tcnt_Int) are shared pins with the external signal terminals of the normal circuit (Log_Cir) inside the semiconductor integrated circuit (IC_Chip) in the normal operation mode (FIG. 5).

  In another more specific form of the present invention, the semiconductor integrated circuit (IC_Chip) includes a D / A converter (DA) and an A / D converter (AD) connected to the test control interface circuit (Tcnt_Int). . The D / A converter (DA) converts the measurement digital information of the multi-bit test control signal (DI) serially transferred from the outside supplied to the test control interface circuit (Tcnt_Int) into the measurement analog information (Tfd). To do. The converted measurement analog information (Tfd) is applied to one analog circuit block (Anlg_Cir1) via one test switch circuit (Tcnt_Sw1). An analog measurement result (Tdet) from one analog circuit block (Anlg_Cir1) is converted into a digital measurement result by an A / D converter (AD) via one test switch circuit (Tcnt_Sw1). This digital measurement result is transferred to the outside as a test output signal (DI) from the test control interface circuit (Tcnt_Int) as a multi-bit serial signal (see FIG. 6).

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, according to the present invention, it is possible to avoid an increase in the number of external terminals of a semiconductor integrated circuit during a test from the outside of the semiconductor integrated circuit incorporating a plurality of non-serially connected analog circuit blocks.

≪Circuit configuration of semiconductor integrated circuit having test control interface circuit≫
FIG. 1 is a diagram showing a circuit configuration of a semiconductor integrated circuit according to an embodiment of the present invention having a test control interface circuit Tcnt_Int and a plurality of test switch circuits Tcnt_Sw1... Tcnt_SwN. In the figure, all the circuit elements inside the broken line are generated on one silicon semiconductor chip IC_Chip of the semiconductor integrated circuit. Circles on four sides of one silicon semiconductor chip IC_Chip of the semiconductor integrated circuit indicate external terminals that connect the internal circuit of the silicon semiconductor chip IC_Chip with the outside. Outside the silicon semiconductor chip IC_Chip, an automatic test apparatus ATE for determining good / bad of one silicon semiconductor chip IC_Chip of the semiconductor integrated circuit is arranged. One silicon semiconductor chip IC_Chip of the semiconductor integrated circuit and the automatic test apparatus ATE are connected via external terminals T1, T2, T3, T4, and T5. The semiconductor integrated circuit IC_Chip has two operation modes, a normal operation mode and a test mode. In response to a test mode designation signal Norm / Test Mode supplied from the outside via the external terminal T6 of the semiconductor integrated circuit IC_Chip, the semiconductor integrated circuit IC_Chip is set to the test mode operation mode. For example, when the test mode designation signal Norm / Test Mode is high level, the semiconductor integrated circuit IC_Chip is set to the test mode, and when the test mode designation signal Norm / Test Mode is low level, the semiconductor integrated circuit IC_Chip is normally The operation mode is set.

  The semiconductor integrated circuit IC_Chip includes a plurality of analog circuit blocks Anlg_Cir1... Anlg_CirN that are non-series connected on one signal path in the normal operation mode. The plurality of analog circuit blocks Anlg_Cir1... Anlg_CirN are connected to a plurality of test switch circuits Tcnt_Sw1... Tcnt_SwN for switching between a signal path in the test mode and a signal path in the normal operation mode of the semiconductor integrated circuit IC_Chip. In the test mode operation mode, the plurality of test switch circuits Tcnt_Sw1... Tcnt_SwN are controlled from outside the semiconductor integrated circuit IC_Chip via the test control interface circuit Tcnt_Int. In the test mode operation mode, the test control interface circuit Tcnt_Int sequentially activates the plurality of test switch circuits Tcnt_Sw1... Tcnt_SwN connected to the plurality of analog circuit blocks Anlg_Cir1... Anlg_CirN. For example, only the first test switch circuit Tcnt_Sw1 connected to the first analog circuit block Anlg_Cir1 of the N analog circuit blocks Anlg_Cir1... Anlg_CirN is activated by the test control interface circuit Tcnt_Int and the test control circuit Tcnt1. Other test switch circuits are deactivated. In the activated first test switch circuit Tcnt_Sw1, the switch TSW11 is turned on, the switch TSW12 is turned off, and the switches TSW13 and TSW14 are turned on. The relationship between the measurement application signal Tfd supplied via the switch TSW13 and the measurement result Tdet output via the switch TSW14 is determined by the automatic test apparatus ATE, and the differential amplifier of the first analog circuit block Anlg_Cir1 Whether the differential input offset voltage of DA1 is good or bad is determined. Next, only the second test switch circuit Tcnt_Sw2 connected to the second analog circuit block Anlg_Cir2 of the N analog circuit blocks Anlg_Cir1... Anlg_CirN is activated by the test control interface circuit Tcnt_Int and the test control circuit Tcnt2. The other test switch circuits are deactivated. In the activated second test switch circuit Tcnt_Sw2, the switch TSW21 is turned on, the switch TSW22 is turned off, and the switches TSW23 and TSW24 are turned on. The relationship between the measurement application signal Tfd supplied via the switch TSW23 and the measurement result Tdet output via the switch TSW24 is determined by the automatic test apparatus ATE, and the differential amplifier of the second analog circuit block Anlg_Cir2 Whether the differential input offset voltage of DA2 is good or bad is determined. Finally, only the Nth test switch circuit Tcnt_SwN connected to the Nth analog circuit block Anlg_CirN of the N analog circuit blocks Anlg_Cir1... Anlg_CirN is activated by the test control interface circuit Tcnt_Int and the test control circuit Tcntn. The other test switch circuits are deactivated. In the activated N-th test switch circuit Tcnt_SwN, the switch TSWn1 is turned on, the switch TSWn2 is turned off, and the switches TSWn3 and TSWn4 are turned on. The relationship between the measurement applied signal Tfd supplied via the switch TSWn3 and the measurement result Tdet output via the switch TSWn4 is determined by the automatic test apparatus ATE, and the differential amplifier of the Nth analog circuit block Anlg_CirN Whether the DAn differential input offset voltage is good or bad is determined. In this way, in the plurality of analog circuit blocks Anlg_Cir1... Anlg_CirN, the supply of the measurement application signal Tfd and the output of the measurement result Tdet are sequentially controlled from the outside of the semiconductor integrated circuit IC_Chip. Further, in each test of the plurality of analog circuit blocks Anlg_Cir1... Anlg_CirN, the test control interface circuit Tcnt_Int receives a multi-bit test control signal DI serially transferred from the outside. As shown in FIG. 4, the multi-bit test control signal DI first includes test target bit information TTBI designating which analog circuit block of the plurality of analog circuit blocks Anlg_Cir1... Anlg_CirN is the test target. Further, as shown in FIG. 4, the multi-bit test control signal DI is used to control the supply of the measurement application signal and the output of the measurement result in the test of each analog circuit block of the plurality of analog circuit blocks Anlg_Cir1... Anlg_CirN. Switch control bit information TSCBI for controlling ON / OFF of a plurality of test switches TSW11, TSW12, TSW13, TSW14,... TSWn1, TSWn2, TSWn3, and TSWn4 that constitute each of the plurality of test switch circuits Tcnt_Sw1. Including. As shown in FIG. 1, a plurality of test control circuits Tcnt1... TcntN are connected between the test control interface circuit Tcnt_Int and the plurality of test switch circuits Tcnt_Sw1... Tcnt_SwN. Each of the plurality of test control circuits Tcnt1... TcntN turns on the plurality of test switches TSW11, TSW12, TSW13, TSW14.・ Control off. As shown in FIGS. 2 and 3, the test control signal DI of a plurality of bits serially transferred from the outside to the test control interface circuit Tcnt_Int is transferred in synchronization with a clock signal CLK having a substantially constant frequency from the outside. In the test mode operation mode, when a plurality of bits of the test control signal DI are serially transferred from the outside to the test control interface circuit Tcnt_Int in synchronization with the clock signal CLK having a substantially constant frequency, the test control interface circuit Tcnt_Int A strobe signal of a predetermined level is supplied. This predetermined level strobe signal is, for example, a high-level chip selection signal CS. As a result, the test control interface circuit Tcnt_Int is supplied with a chip selection signal CS, a clock signal CLK having a substantially constant frequency, and a test control signal DI having a plurality of bits for serial transfer. Therefore, the test control interface circuit Tcnt_Int is a so-called three-wire serial interface. The three-wire serial interface is currently spreading as a serial digital interface with a small number of I / O terminals and as a serial interface with a built-in microcomputer.

≪Normal operation mode of semiconductor integrated circuit≫
The semiconductor integrated circuit IC_Chip includes a plurality of analog circuit blocks Anlg_Cir1... Anlg_CirN that are non-series connected on one signal path in the normal operation mode. Each of the plurality of analog circuit blocks Anlg_Cir1... Anlg_CirN is a switching regulator. In this embodiment, six switching regulators are mounted in the semiconductor integrated circuit IC_Chip, and the same level or the same level depending on the voltage dividing ratio of the voltage dividing resistors R11, R12... Rn1, Rn2 from the input DC voltage VIN1. Different levels of output DC voltages V _OUT1 ... V _OUTn can be output in parallel. The plurality of switching regulators are determined by the ratio of the conduction period T _{ONH of the} high-side switches M11 and Mn1 to the conduction period T _ONL of the low-side switches M12 and Mn2 from the input DC voltage VIN1. Output DC voltages V _OUT1 ... V _OUTn are generated. Strictly speaking, the output DC voltage _V OUT1 _{... V OUTn} has one end to the external terminal T9 ... T13 is the output terminal of the switching regulator is connected, the other end connected to the load _Z L1 ... _{Z Ln} and smoothing capacitor C10 ... Cn0 Is generated at the other end of the smoothed coils L1... Ln. Load fluctuations such as current fluctuations flowing through the loads Z _L1 ... Z _Ln are fed back to the voltage dividing resistors R11, R12... Rn1, Rn2 via the external terminals T7. The load fluctuation detection signals by the voltage dividing resistors R11, R12... Rn1, Rn2 are amplified by the error amplifiers of the differential amplifiers DA1. Strictly speaking, the load fluctuation detection signals by the voltage dividing resistors R11, R12... Rn1, Rn2 are applied to the inverting input terminals of the differential amplifiers DA1. Reference voltages Vref1... Vrefn are supplied. The output signals of the differential amplifiers DA1... DAn as error amplifiers are applied to the non-inverting input terminals of the comparators CMP1... CMPn, while the inverting input terminals of the comparators CMP1... CMPn are supplied from the triangular wave signal generation circuit Tri_Gen1. A reference triangular wave signal for PWM (Pulse Width Modulation) modulation is supplied. The output signals of the comparators CMP1... CMPn are supplied to the inputs of the switching controllers SWC1. The outputs of the switching controllers SWC1... SWCn are supplied to inputs of drivers DR11 and DRn1 that drive the high-side switches M11 and Mn1 and inputs of drivers DR12 and DRn2 that drive the low-side switches M12 and Mn2. It is assumed that the output DC voltage V _OUT1 ... V _OUTn has increased due to a decrease in the current flowing through the loads Z _L1 ... Z _Ln . Then, the output DC level of the differential amplifiers DA1... DAn that is compared with the PWM modulation reference triangular wave signal by the comparators CMP1. As a result, the output high level period of the comparators CMP1... CMPn becomes longer, while the output low level period becomes shorter. Then, the switching controller SWC1 ... SWCn which is controlled by the output of the comparator CMP1 ... CMPn, while shortening the conduction period _{T ONH} of the high-side switch M11, Mn1, to lengthen the conduction period _{T ONL} of the low-side switch M12, Mn2. As a result, the output DC voltage _V OUT1 _{... V OUTn} is lowered, the load _Z L1 ... load despite variations DC output voltage _V OUT1 _{... V OUTn} of _{Z Ln} can be maintained substantially constant. Capacitors C11... Cn1 connected between output terminals and inverting input terminals of differential amplifiers DA1... DAn as error amplifiers are phase compensation capacitors for preventing oscillation of the differential amplifiers DA1. Also, the series circuit of resistors R13... Rn3 and capacitors C12... Cn2 connected between the external terminals T9... T13 and the inverting input terminals of the differential amplifiers DA1. This is a phase compensation circuit for improvement. Thus, in the normal operation mode of the semiconductor integrated circuit, the plurality of analog circuit blocks Anlg_Cir1... Anlg_CirN operate as a plurality of switching regulators. In this normal operation mode, in each of the plurality of test switch circuits Tcnt_Sw1. The state is controlled to the off state.

≪Semiconductor integrated circuit test mode≫
In order to set the operation mode of the semiconductor integrated circuit shown in FIG. 1 to the test mode, the test mode designating signal Norm / Test Mode supplied to the external terminal T6 is set to the high level. As shown in FIGS. 2 and 3, the test control interface circuit Tcnt_Int responds to the high-level test mode designation signal Norm / Test Mode. The test control interface circuit Tcnt_Int is input to the external terminal T3 in synchronization with the clock signal CLK having a substantially constant frequency at the terminal T2 during a period when the chip selection signal CS applied from the automatic test apparatus ATE to the external terminal T1 is at a high level. Data DI to be processed as a test control signal. In response to the test control signal DI, the test control interface circuit Tcnt_Int sequentially activates the plurality of test switch circuits Tcnt_Sw1... Tcnt_SwN connected to the plurality of analog circuit blocks Anlg_Cir1. Specifically, in response to the test target bit information TTBI included in the test control signal DI, the test control interface circuit Tcnt_Int is currently tested by the automatic test apparatus ATE which analog circuit block of the plurality of analog circuit blocks Anlg_Cir1... Anlg_CirN. It is specified whether it is a test target. With the following combination of the 3-bit test target bit information TTBI, six analog circuit blocks Anlg_Cir1... Anlg_CirN can be sequentially designated as test targets.

TTBI test target “001” first analog circuit block “010” second analog circuit block “011” third analog circuit block “100” fourth analog circuit block “101” fifth analog circuit block “111” 6th analog circuit block In the example of FIGS. 3 and 4, the combination of the 3-bit test target bit information TTBI is “101”, so the 5th analog circuit block is designated as the current test target. . Thereby, in the plurality of analog circuit blocks Anlg_Cir1... Anlg_CirN, the supply of the measurement application signal Tfd and the output of the measurement result Tdet are sequentially controlled from the outside of the semiconductor integrated circuit IC_Chip.

  As described above, after any one analog circuit block is designated as a test target from a plurality of analog circuit blocks Anlg_Cir1... Anlg_CirN, a plurality of test switch circuits that are connected to the designated analog circuit block are configured. Switch on / off control is arbitrarily designated by a plurality of bits of switch control bit information TSCBI. In the example of FIGS. 3 and 4, since the combination of the 4-bit switch control bit information TSCBI is “1011”, the first test switch TSW11 (TSWn1) constituting one test switch circuit is turned on. The second test switch TSW12 (TSWn2) is controlled to be turned off, and the third and fourth test switches TSW13 (TSWn3) and TSW14 (TSWn4) are controlled to be turned on. The first test switch TSW11 (TSWn1) is controlled to be turned on, whereby the output terminal and the inverting input terminal of the differential amplifier DA1 (DAn) are short-circuited. When the second test switch TSW12 (TSWn2) is controlled to be turned off, the inverting input terminal of the differential amplifier DA1 (DAn) is electrically connected to the voltage dividing circuits R11, R12 (voltage dividing circuits Rn1, Rn2). To be separated. When the third test switch TSW13 (TSWn3) is controlled to be turned on, the measurement application signal Tfd is supplied from the automatic test apparatus ATE to the inverting input terminal of the differential amplifier DA1 (DAn) via the external terminal T4. Is done. At this time, the reference voltage generation circuit Vref1 (Vrefn) connected to the inverting input terminal of the differential amplifier DA1 (DAn) is controlled to a high output impedance state. When the fourth test switch TSW14 (TSWn4) is controlled to be in the ON state, the measurement result Tdet of the short-circuited output terminal and the inverting input terminal of the differential amplifier DA1 (DAn) is transmitted via the external terminal T5. Transferred to automatic test equipment ATE. The automatic test apparatus ATE automatically determines that the differential offset voltage is small if the difference between the voltage of the measurement result Tdet of the external terminal T5 and the voltage of the measurement application signal Tfd of the external terminal T4 is within the allowable value range, and if not, the differential offset Automatically determines that the voltage is high.

<< Semiconductor Integrated Circuit According to Other Embodiments >>
FIG. 5 is a diagram showing a circuit configuration of a semiconductor integrated circuit according to another embodiment of the present invention. The difference between the circuit configuration of FIG. 1 and that of FIG. 1 will be described below. In the figure, the external terminals T1, T2, T3 used by the test control interface circuit Tcnt_Int in the test mode and the external terminals T4, T5 used by the plurality of test switch circuits Tcnt_Sw1 ... Tcnt_SwN are semiconductor integrated circuits in the normal operation mode. It is a pin shared with the external terminal of the normal circuit inside IC_Chip. In this example, since the internal normal circuit is composed of the logic circuit Log_cir, the semiconductor integrated circuit IC_Chip is an analog / digital mixed IC. A test mode designating signal Norm / Test Mode is commonly applied to the logic circuit Log_cir and the test control interface circuit Tcnt_Int as the internal normal circuit. When the test mode designation signal Norm / Test Mode is at a high level, the test mode is entered and the test control interface circuit Tcnt_Int acquires the right to use the external terminals T1, T2, T3, T4, and T5. When the test mode designation signal Norm / Test Mode is at a low level, the normal operation mode is entered, and the logic circuit Log_cir as a normal circuit acquires the right to use the external terminals T1, T2, T3, T4, and T5. Note that the plurality of analog circuit blocks Anlg_Cir1... Anlg_CirN constitute a plurality of switching rectifiers as in FIG.

  FIG. 6 is a diagram showing a circuit configuration of a semiconductor integrated circuit according to another embodiment of the present invention. The point that the circuit configuration of the figure is different from that of FIG. 5 will be described below. The semiconductor integrated circuit IC_Chip includes a D / A converter DA and an A / D converter AD connected to the test control interface circuit Tcnt_Int. The D / A converter DA and the A / D converter AD are connected to the output and input of the logic circuit Log_cir as an internal normal circuit in the normal operation mode of the semiconductor integrated circuit IC_Chip. Accordingly, the logic circuit Log_cir, the D / A converter DA, and the A / D converter AD as a normal circuit internally perform digital signal processing, and the external interface executes analog signal data processing. In the test mode of the semiconductor integrated circuit IC_Chip, the D / A converter DA converts the digital information for measurement of the multi-bit test control signal DI serially transferred from the outside supplied to the test control interface circuit Tcnt_Int into the measurement analog information Tfd. Convert. The converted measurement analog information Tfd is applied to the first analog circuit block Anlg_Cir1 via, for example, the first test switch circuit Tcnt_Sw1. The analog measurement result Tdet from the first analog circuit block Anlg_Cir1 is converted into a digital measurement result by the A / D converter AD via the first test switch circuit Tcnt_Sw1. This digital measurement result is transferred from the test control interface circuit Tcnt_Int to the external automatic test apparatus ATE in the form of a test output signal DI in the form of a multi-bit serial signal. During this transfer, the test control interface circuit Tcnt_Int sets the chip selection signal CS to a low level. That is, when the chip selection signal CS is at a high level, the test control signal DI is transferred from the external automatic test apparatus ATE to the test control interface circuit Tcnt_Int. When the chip selection signal CS is at a low level, the test output signal DI is transferred from the test control interface circuit Tcnt_Int to the external automatic test apparatus ATE.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, in the embodiment of FIG. 1, the plurality of triangular wave signal generation circuits Tri_Gen1... Tri_Genn may be a single common triangular wave signal generation circuit. Further, in the embodiment of FIG. 6, the plurality of analog circuit blocks Anlg_Cir1... Anlg_CirN are not limited to having the same analog signal processing function. That is, the plurality of analog circuit blocks Anlg_Cir1... Anlg_CirN can have different analog signal processing functions.

FIG. 1 is a diagram showing a circuit configuration of a semiconductor integrated circuit according to an embodiment of the present invention. FIG. 2 is a diagram for explaining the function of the test control interface circuit Tcnt_Int shown in FIG. FIG. 3 is a waveform diagram of an input signal and an output signal of the test control interface circuit Tcnt_Int shown in FIG. FIG. 4 is a diagram showing test target bit information TTBI and switch control bit information TSCBI included in the multi-bit test control signal DI shown in FIG. FIG. 5 is a diagram showing a circuit configuration of a semiconductor integrated circuit according to another embodiment of the present invention. FIG. 6 is a diagram showing a circuit configuration of a semiconductor integrated circuit according to another embodiment of the present invention.

Explanation of symbols

IC_Chip Semiconductor Integrated Circuit Norm / Test Mode Test Mode Designation Signal Anlg_Cir1... Anlg_CirN Multiple Analog Circuit Blocks ATE Automatic Test Device DI Serial Transfer Multiple Bit Test Control Signal Tcnt_Int Test Control Interface Circuit Tcntn Test Control Circuit TcntNtSw1 Switch circuit for testing

Claims (28)

The semiconductor integrated circuit has two operation modes, a normal operation mode and a test mode.
In response to a test mode designation signal supplied from the outside of the semiconductor integrated circuit, the semiconductor integrated circuit is set to an operation mode of the test mode,
The semiconductor integrated circuit includes a plurality of analog circuit blocks connected in non-series on one signal path in the normal operation mode,
Each of the plurality of analog circuit blocks includes a differential amplifier, a plurality of resistors connected to the differential amplifier, and a capacitor connected to the differential amplifier.
The plurality of analog circuit blocks are connected to a plurality of test switch circuits for switching a signal path in the test mode and a signal path in the normal operation mode of the semiconductor integrated circuit,
The semiconductor integrated circuit includes a test control interface circuit connected to the plurality of test switch circuits.
In the operation mode of the test mode, the plurality of test switch circuits are controlled from outside the semiconductor integrated circuit via the test control interface circuit,
In the operation mode of the test mode, the test control interface circuit sequentially activates the plurality of test switch circuits connected to the plurality of analog circuit blocks, so that the plurality of analog circuit blocks sequentially The supply of the measurement application signal from the outside of the semiconductor integrated circuit and the control of the output of the measurement result to the outside of the semiconductor integrated circuit are executed,
In each test of the plurality of analog circuit blocks, the test control interface circuit receives a plurality of bits of a test control signal serially transferred from the outside.   The plurality of bit test control signals are used for the plurality of test circuits for controlling the supply of the measurement application signal and the output of the measurement result in a test of each analog circuit block of the plurality of analog circuit blocks. 2. The semiconductor integrated circuit according to claim 1, comprising switch control bit information for controlling ON / OFF of a plurality of test switches constituting each of the switch circuits.   2. The semiconductor integrated circuit according to claim 1, wherein the plurality of bits of the test control signal includes test target bit information for designating which analog circuit block of the plurality of analog circuit blocks is a test target.   3. The semiconductor integrated circuit according to claim 2, wherein the plurality of bits of the test control signal include test target bit information for designating which analog circuit block of the plurality of analog circuit blocks is a test target. A plurality of test control circuits are connected between the test control interface circuit and the plurality of test switch circuits,
3. The semiconductor integrated circuit according to claim 2, wherein each of the plurality of test control circuits controls on / off of the plurality of test switches constituting each of the plurality of test switch circuits.   3. The test control signal of a plurality of bits serially transferred from the outside of the semiconductor integrated circuit to the test control interface circuit is transferred in synchronization with a clock signal having a substantially constant frequency from the outside of the semiconductor integrated circuit. A semiconductor integrated circuit according to 1.   In the operation mode of the test mode, when the test control signal of the plurality of bits is serially transferred from the outside to the test control interface circuit in synchronization with the clock signal having the substantially constant frequency, the test control interface 7. The semiconductor integrated circuit according to claim 6, wherein a strobe signal having a predetermined level is supplied to the circuit.   8. The semiconductor integrated circuit according to claim 7, wherein the strobe signal at the predetermined level is a chip selection signal at the predetermined level.   The external terminal of the test control interface circuit to which the test control signal of the plurality of bits is serially transferred in the operation mode of the test mode is shared with the external signal terminal of the normal circuit inside the semiconductor integrated circuit in the normal operation mode. 9. The semiconductor integrated circuit according to claim 2, wherein the semiconductor integrated circuit is a pin.   9. The plurality of analog circuit blocks can operate in parallel in the normal operation mode, and the plurality of analog circuit blocks can output a plurality of outputs in parallel by the parallel operation. A semiconductor integrated circuit according to any one of the above.   The semiconductor according to claim 9, wherein the plurality of analog circuit blocks can operate in parallel in the normal operation mode, and the plurality of analog circuit blocks can output a plurality of outputs in parallel by the parallel operation. Integrated circuit. The semiconductor integrated circuit has two operation modes, a normal operation mode and a test mode.
In response to a test mode designation signal supplied from the outside of the semiconductor integrated circuit, the semiconductor integrated circuit is set to an operation mode of the test mode,
The semiconductor integrated circuit includes a plurality of analog circuit blocks connected in non-series on one signal path in the normal operation mode,
The plurality of analog circuit blocks are connected to a plurality of test switch circuits for switching a signal path in the test mode and a signal path in the normal operation mode of the semiconductor integrated circuit,
The semiconductor integrated circuit includes a test control interface circuit connected to the plurality of test switch circuits.
In the operation mode of the test mode, the plurality of test switch circuits are controlled from outside the semiconductor integrated circuit via the test control interface circuit,
In the operation mode of the test mode, the test control interface circuit sequentially activates the plurality of test switch circuits connected to the plurality of analog circuit blocks, so that the plurality of analog circuit blocks sequentially The supply of the measurement application signal from the outside of the semiconductor integrated circuit and the control of the output of the measurement result to the outside of the semiconductor integrated circuit are executed,
In each test of the plurality of analog circuit blocks, the test control interface circuit receives a plurality of bits of a test control signal serially transferred from the outside.   The plurality of bit test control signals are used for the plurality of test circuits for controlling the supply of the measurement application signal and the output of the measurement result in a test of each analog circuit block of the plurality of analog circuit blocks. 13. The semiconductor integrated circuit according to claim 12, comprising switch control bit information for controlling on / off of a plurality of test switches constituting each of the switch circuits.   13. The semiconductor integrated circuit according to claim 12, wherein the plurality of bits of the test control signal include test target bit information for designating which analog circuit block of the plurality of analog circuit blocks is a test target.   The semiconductor integrated circuit according to claim 13, wherein the plurality of bits of the test control signal includes test target bit information for designating which analog circuit block of the plurality of analog circuit blocks is a test target. A plurality of test control circuits are connected between the test control interface circuit and the plurality of test switch circuits,
The semiconductor integrated circuit according to claim 13, wherein each of the plurality of test control circuits controls on / off of the plurality of test switches constituting each of the plurality of test switch circuits.   14. The multi-bit test control signal serially transferred from the outside of the semiconductor integrated circuit to the test control interface circuit is transferred in synchronization with a clock signal having a substantially constant frequency from the outside of the semiconductor integrated circuit. A semiconductor integrated circuit according to 1.   In the operation mode of the test mode, when the test control signal of the plurality of bits is serially transferred from the outside to the test control interface circuit in synchronization with the clock signal having the substantially constant frequency, the test control interface 18. The semiconductor integrated circuit according to claim 17, wherein a strobe signal having a predetermined level is supplied to the circuit.   19. The semiconductor integrated circuit according to claim 18, wherein the predetermined level strobe signal is the predetermined level chip selection signal.   The external terminal of the test control interface circuit to which the test control signal of the plurality of bits is serially transferred in the operation mode of the test mode is shared with the external signal terminal of the normal circuit inside the semiconductor integrated circuit in the normal operation mode. 20. The semiconductor integrated circuit according to claim 13, wherein the semiconductor integrated circuit is a pin.   In the operation mode of the test mode, the external terminal of the test control interface circuit to which the strobe signal of the predetermined level and the clock signal of the substantially constant frequency are supplied from the outside to the test control interface circuit, 19. The semiconductor integrated circuit according to claim 18, wherein the semiconductor integrated circuit is shared with an external signal terminal of the normal circuit inside the semiconductor integrated circuit in a normal operation mode. The semiconductor integrated circuit includes a D / A converter and an A / D converter connected to the test control interface circuit,
The D / A converter converts the digital information for measurement of the test control signal of the plurality of bits transferred serially supplied from the outside to the test control interface circuit into analog information for measurement. The measurement analog information is applied to one analog circuit block selected from the plurality of analog circuit blocks via one test switch circuit selected from the plurality of test switch circuits,
An analog measurement result from the selected one analog circuit block is converted into a digital measurement result by the A / D converter via the selected test switch circuit, and the converted digital measurement result 20. The semiconductor integrated circuit according to claim 13, wherein the test control interface circuit transfers the test output signal to the outside as a test output signal by a multi-bit serial signal.   The external terminal of the test control interface circuit to which the test control signal of the plurality of bits is serially transferred in the operation mode of the test mode is shared with the external signal terminal of the normal circuit inside the semiconductor integrated circuit in the normal operation mode. The semiconductor integrated circuit according to claim 22, wherein the semiconductor integrated circuit is a pin.   20. The plurality of analog circuit blocks can operate in parallel in the normal operation mode, and the plurality of analog circuit blocks can output a plurality of outputs in parallel by the parallel operation. A semiconductor integrated circuit according to any one of the above.   21. The semiconductor according to claim 20, wherein the plurality of analog circuit blocks can operate in parallel in the normal operation mode, and the plurality of analog circuit blocks can output a plurality of outputs in parallel by the parallel operation. Integrated circuit.   22. The semiconductor according to claim 21, wherein in the normal operation mode, the plurality of analog circuit blocks can operate in parallel, and the plurality of analog circuit blocks can output a plurality of outputs in parallel by the parallel operation. Integrated circuit.   23. The semiconductor according to claim 22, wherein in the normal operation mode, the plurality of analog circuit blocks can operate in parallel, and the plurality of analog circuit blocks can output a plurality of outputs in parallel by the parallel operation. Integrated circuit.   24. The semiconductor according to claim 23, wherein the plurality of analog circuit blocks can operate in parallel in the operation mode of the normal operation, and the plurality of analog circuit blocks can output a plurality of outputs in parallel by the parallel operation. Integrated circuit.

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