JP2930018B2 - Voltage conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a voltage conversion circuit, and more particularly to a voltage conversion circuit for generating a voltage to be supplied to an LSI.

[0002]

2. Description of the Related Art Conventionally, this kind of voltage conversion circuit has been
Are used for stabilizing the power supply voltage and generating the power supply voltage necessary for LSIs and the like. For example, “1989.12.1
5. “Analog technology for VLSI”, 246 to 24
See page 9 for a series regulator type that converts its voltage by comparing its output voltage with the voltage obtained by a constant voltage source and controlling the on-resistance of a transistor connected in series between the input and output terminals. Compared with the output voltage and the voltage obtained by the constant voltage source, the ratio of the period for turning on and off the transistor connected in series between the input and output by the pulse width modulation method is changed, and the ratio is accumulated during the on period. Two types of switching regulator type voltage conversion circuits that convert voltage by discharging power during an off period are described.

FIG. 16 is a block diagram showing an example of a conventional voltage conversion circuit, particularly a series regulator type voltage conversion circuit. The voltage Vcc obtained by the external power supply 6 connected to the terminal 101 is dropped by the ON resistance of the transistor 1, converted into a voltage Vdd required for the LSI circuit 7, and supplied to the LSI circuit 7 via the terminal 103. The voltage Vdd is divided by the resistors 71 and 72 and is supplied to the terminal 116. This terminal 116
Is amplified and compared by the operational amplifier 84 with the voltage at the terminal 117, which is the voltage generated by the constant voltage power supply circuit 20, whereby the on-resistance of the transistor 1 is controlled so that the voltage Vdd becomes constant. The capacitor 56 is used for stabilizing the voltage Vdd.

FIG. 17 is a block diagram showing an example of a conventional voltage conversion circuit, particularly a switching regulator type voltage conversion circuit. When transistor 1 is on, terminal 1
A voltage Vcc obtained from the external power supply 6 is applied to the power supply 18, and a current flows through the inductor 42. At this time, the voltage drops due to the AC impedance generated in the inductor 42, and is converted into a voltage Vdd required for the LSI circuit 7.
When the transistor 1 is turned off, a potential difference occurs between both ends of the inductor 42 due to the energy stored in the inductor 42 when the transistor 1 is turned on, and the voltage Vdd becomes LS.
It is supplied to the I circuit 7. The diode 46 is used to fix the lower end voltage of the terminal 118 to the ground level. The voltage Vdd is divided by a resistor 71 and a resistor 72 and is supplied to a terminal 116. The voltage at the terminal 116 is compared and amplified by the operational amplifier 84 with the voltage generated by the constant voltage power supply circuit 20, converted into a pulse duty ratio by the pulse width modulation circuit 15, and changes the ratio of the ON / OFF period of the transistor 1. . Since the average voltage of the voltage Vdd changes depending on the ratio of the ON and OFF periods of the transistor 1, the voltage Vdd is kept almost constant by using this mechanism.

[0005]

The above-described conventional voltage conversion circuit has the following problems.

The first problem is that it has been difficult to integrate the LSI. In other words, when a series regulator type voltage conversion circuit is mounted on an LSI,
Since the output voltage of a series regulator type voltage conversion circuit is changed by a series resistor, the power consumed by this resistor is extremely large, and cannot be used for applications requiring low power consumption. The voltage conversion circuit of the above has a large noise generated by the switching of the transistor and cannot be used for applications requiring low noise. Further, when a required voltage can be supplied from outside without using a voltage conversion circuit, it may be more effective to use the required voltage. Therefore, no matter which conventional voltage conversion circuit is incorporated, the LSI
Is limited in use. For these reasons,
A voltage conversion circuit is not built in the LSI,
A person using I has connected and used a voltage conversion circuit such as a series regulator or a switching regulator externally.

A second problem is that, in the conventional voltage conversion circuit, the output voltage of the voltage conversion circuit is referred to and compared with the voltage of the constant voltage source to determine the resistance value of the transistor and the ratio of the ON / OFF period. The output voltage is adjusted by changing the output voltage. However, in the LSI, the required voltage changes depending on the processing contents, the temperature, and the like. Therefore, only the comparison with the constant voltage source adjusts the output voltage to the voltage required by the LSI. That was impossible. Therefore, conventionally, the power supply voltage of the LSI circuit is high.
Positive LSI by utilizing the property that the delay time is smaller
In particular for supplying a voltage higher than the voltage required for the normal operation
To prevent erroneous operation due to fluctuations in the delay time of LSI circuits.
The law has been used. However, the LSI circuit has a power supply voltage.
The higher the power, the higher the power consumption, and this results in wasted power consumption.

An object of the present invention is to provide a voltage conversion circuit for a built-in LSI which is widely applicable.

Another object of the present invention is to provide a voltage conversion circuit for a built-in LSI which can realize low power consumption.

[0010]

A voltage conversion circuit according to the present invention is built in or external to an LSI, and has one end connected to an external power supply, one end connected to the other end of the transistor, Supplying the power supply voltage used by the LSI circuit to the LSI from the other end;
An external circuit unit externally connected to I, an external circuit detection unit built in the LSI for detecting a type of the external circuit unit, and the external circuit unit detected by the external circuit detection unit And a transistor control unit built in the LSI for controlling the transistor according to the type of the LSI.

Another voltage conversion circuit according to the present invention uses a transistor externally connected to an LSI, one end of which is connected to an external power supply, and one end of which is connected to the other end of the transistor. An external circuit unit external to the LSI, for supplying a power supply voltage to the LSI,
A setting circuit external to the LSI for setting the type of the external circuit unit, and controlling the transistor according to the type of the external circuit unit set by the setting circuit; built in the LSI Transistor control section.

According to the present invention, the control method of a transistor is changed according to the configuration (type) of an external circuit for supplying a power supply voltage to an LSI circuit, so that it can be used according to the purpose of use.

According to an embodiment of the present invention, the external circuit supplies the power supply voltage by a switching regulator operation, a series regulator operation, or from another power supply.

According to another embodiment of the present invention, the LS
A delay time measuring unit built in the LSI for artificially measuring a delay time of the LSI circuit using the same power supply voltage as the I circuit; and the transistor control unit further measures the magnitude of the delay time. The transistor is controlled by reference.

By controlling the transistor with reference to the delay time of the LSI circuit, the output voltage of the voltage conversion circuit can be optimized.

According to another embodiment of the present invention, when the external circuit section generates a power supply voltage by a switching regulator operation, the transistor control section alternately turns on the transistor with a transistor control signal having a pulse waveform. / Off and changes the duty ratio of the transistor control signal so that the delay time is constant, and when the external circuit unit generates a power supply voltage by a series regulator operation, the transistor performs a series regulator operation. Output a transistor control signal for changing the level of the transistor control signal so that the delay time is constant, and when the external circuit supplies a power supply voltage from another power supply, the transistor is always turned on. Do And it outputs the lunge static control signal to said transistor.

According to another embodiment of the present invention, the external circuit detecting unit outputs a voltage proportional to a result obtained by subtracting a voltage at the other end from a voltage at one end of the external circuit unit as a differential voltage. A first comparison circuit that compares the difference voltage with a first comparison voltage that is slightly higher than the difference voltage when the voltages at both ends are equal; and a difference when the two ends are equal. A second comparison circuit for comparing with a second comparison voltage slightly lower than the first comparison voltage;
A gate that outputs a signal of a first logic level when the comparison voltage is higher than the comparison voltage and a second logic level when the difference voltage is lower than the second comparison voltage. Including circuits.

According to another embodiment of the present invention, the transistor control unit includes: a pulse width modulation circuit that outputs a pulse signal having a duty ratio corresponding to the magnitude of the delay measurement signal of the delay time measurement unit; High level, the pulse signal, the delay measurement signal, ground level 4
A transistor control changeover switch for selecting one of the three signals, a buffer circuit for amplifying a signal selected by the transistor control changeover switch and outputting it as a transistor control signal, and the transistor control changeover switch for turning on the transistor To check the output of the external circuit detection unit, and switch the transistor control changeover switch so as to select the delay measurement signal when the output is at the second logic level, and when the output is at the first logic level. The transistor control changeover switch is switched so that the transistor is turned off, and the transistor control changeover switch is configured to select the pulse signal when the output is at the second logic level. Toggles comprises condition judging circuit the output to control said transistor control changeover switch such that the transistor when the first logic level to turn on.

According to another embodiment of the present invention, the delay time measuring section delays a clock signal using the power supply voltage, and outputs a delay signal; Comparing the phases, outputting an active up signal and an inactive down signal when the phase is smaller than one cycle of the clock signal, and outputting an inactive up signal when the phase is larger than one cycle of the clock signal; A first comparator connected at one end to a power supply, and turned on by the up signal; and a second transistor connected between the first transistor and ground and turned on by the down signal. And a capacitor connected between the connection point of the first and second transistors and the ground. Outputs a potential of capacitors as the delay time.

[0020]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a voltage conversion circuit according to a first embodiment of the present invention. The external power supply 6 supplies power to the LSI through the terminal 101. Transistor 1 is terminal 1
01 and the terminal 102 are connected such that the resistance value is controlled by the voltage applied to the terminal 106.
The external circuit unit 2 is connected to the terminals 102 and 103,
It is used to determine the operation of the voltage conversion circuit of the present invention. The voltage at the terminal 103 becomes the power supply voltage Vdd used by the LSI circuit 7. The delay time measuring unit 3 measures the delay time of the LSI circuit 7 using the same power supply voltage Vdd as that of the LSI circuit 7, and outputs the result to the terminal 104. The external circuit detection unit 4 checks the external state from the voltages of the terminals 102 and 103, and outputs the result to the terminal 105. The transistor control unit 5 changes the control method with reference to the voltage of the terminal 105, and changes the output value of the control signal according to the voltage of the terminal 104. The control signal of the transistor control unit 5 is output to the terminal 106.

Next, a detailed configuration of the external circuit section 2 will be described. FIGS. 2A, 2B, and 2C are circuit diagrams showing configuration examples of the external circuit unit 2 of the present invention.

FIG. 2A shows an example of the configuration of an external circuit used when the power supply voltage Vdd applied to the LSI circuit 7 is generated by the switching regulator operation, and is constituted by an inductor 41, a diode 45, and a capacitor 51. The inductor 41 is connected between the terminal 102 and the terminal 103, and the diode 45 is connected between the ground and the terminal 102.
, And are connected such that current flows from the ground to the terminal 102. The capacitor 51 is connected to the terminal 10
3, and is used to stabilize the voltage Vdd.

FIG. 2B shows an example of the configuration of an external circuit used when the power supply voltage Vdd to be applied to the LSI circuit 7 is generated by a series regulator operation. The terminals 102 and 103 are short-circuited, and the capacitor 52 is connected between the terminal 103 and the ground, and is used to stabilize the voltage Vdd.

FIG. 2C shows an example of the configuration of an external circuit portion used when a power supply voltage Vdd supplied to the LSI circuit 7 is supplied from another power supply.
It is constituted by a power supply 8. The capacitor 54 is connected to the terminal 10
2 and ground, the capacitor 53 is connected to the terminal 10
3 and the ground, the power supply 8 is connected between the terminal 103 and the ground, and the power supply voltage Vd applied to the LSI circuit 7
Supply d.

Next, the operation of the voltage conversion circuit of FIG. 1 will be described with reference to the drawings. First, in order to operate the switching regulator, the circuit of the external circuit unit 2 is shown in FIG.
The case of the circuit (a) will be described. When the switching regulator operates, the transistor 1 alternately repeats the saturation region operation and the cutoff region operation, that is, is turned on / off alternately. FIG. 3A shows operation waveforms when the switching regulator operates. Waveform 201,
A waveform 202 indicates the voltage of the terminal 102 and the voltage of the terminal 103, respectively. When the transistor 1 is turned on, the terminal 10
2 becomes high level, and the inductor 41
, An AC resistance occurs, and the voltage Vdd at the terminal 103 becomes lower by the voltage drop due to the AC resistance. Also,
At the same time, energy is stored in the inductor 41 during this period. When the transistor 1 is turned off, the voltage of the terminal 102 is clamped by the diode 45 and becomes close to the ground level. The voltage Vdd at the terminal 103 is higher than the ground level by the voltage generated in the inductor 41 due to the energy stored in the inductor 41 when the transistor 1 is on. Capacitor 51 is connected to terminal 1
The voltage of the voltage Vdd of 03 is averaged. The average voltage of the terminal 103 changes depending on the ratio of the on and off periods of the transistor 1, that is, the duty ratio. The voltage Vdd of the terminal 103 becomes the power supply voltage of the LSI circuit 7. The external circuit detection unit 4 detects the configuration of the external circuit unit 2, and here reports that the switching regulator operation is performed to the transistor control unit 5, and the transistor control unit 5 controls the control signal Tctrl for performing the switching regulator operation. That is, a control signal having a pulse waveform is output. The delay time measuring unit 3 uses a delay circuit that operates at the same power supply voltage as the LSI circuit 7 to artificially measure the delay signal of the LSI circuit 7. Delay time measurement unit 3
The delay time measurement signal Tdly obtained by the above is supplied to the transistor control unit 5, whereby the transistor control signal Tdly is controlled so that the delay time becomes constant.
The duty ratio of the ctrl pulse signal is changed.

Next, the case where the circuit of the external circuit section 2 is the circuit of FIG. 2B for operating the series regulator will be described. When operating the series regulator, the transistor 1 is operated in the linear region. FIG.
(B) shows an operation waveform when the series regulator is operated. Waveforms 203 and 204 are respectively connected to terminal 10
2, the voltage of the terminal 103 is shown. Since the terminals 102 and 103 are short-circuited, they have substantially the same voltage. The voltage Vout of the terminal 102 becomes lower than the voltage Vcc of the terminal 101 by the voltage drop due to the on-resistance of the transistor 1. The capacitor 52 is connected to the voltage Vdd of the terminal 103.
Are averaged. The voltage at the terminal 103 changes depending on the on-resistance of the transistor 1. Voltage Vd of terminal 103
d is the power supply voltage of the LSI circuit 7. External circuit detector 4
Detects the configuration of the external circuit unit 2 and reports here that the series regulator operation is to be performed to the transistor control unit 5, and the transistor control unit 5 has a control signal T for performing the series regulator operation.
ctrl is output. The delay time measuring unit 3 measures the delay time of the LSI circuit 7 using a delay circuit that operates at the same power supply voltage as the LSI circuit 7. Delay time measurement unit 3
The delay time measurement signal Tdly obtained by the above is supplied to the transistor control unit 5, whereby the transistor control signal Tdly is controlled so that the delay time becomes constant.
ctrl level is changed.

Next, the case where the circuit of the external circuit section 2 is the circuit shown in FIG. 2C for supplying the power supply voltage Vdd from another power supply will be described. When the power supply voltage Vdd is supplied from another power supply, there is no need to convert the power supply, and the transistor 1 does not need to be changed. FIG.
(C) shows an operation waveform when the other power supply is operated. Waveforms 205 and 206 correspond to terminals 102 and 103, respectively.
Are shown. The external circuit detection unit 4 detects the configuration of the external circuit unit 2, and here, reports to the transistor control unit 5 that another power supply operation is to be performed, and the transistor control unit 5 has a control signal Tctrl for performing another power supply operation. That is, a signal fixed so that the transistor 1 is turned on is output.

Next, a detailed configuration of the delay time measuring section 3 will be described. FIG. 4 is a block diagram illustrating a configuration example of the delay time measurement unit 3. Delay circuit 10 delays clock signal CLK applied to terminal 107 to generate a delayed signal DLY applied to terminal 108. The phase comparison circuit 9 has a terminal 10
In response to the phase difference between clock signal CLK applied to terminal 7 and delay signal DLY applied to terminal 108, up signal UP applied to terminal 109 and down signal DOWN applied to terminal 110 are generated. PMOS transistor 22 which is turned on when up signal UP is activated
And an nMOS transistor 23 that is turned on when the down signal DOWN becomes active, has one end connected to the power supply voltage and the ground, the other end connected to one another, and the other end connected to one end of the resistor 61. . The other end of the resistor 61 is connected to the terminal 104. The capacitor 55 has one end connected to the ground and the other end connected to the other end of the resistor 62. The other end of the resistor 62 is connected to the terminal 104.

FIG. 5 is a circuit diagram showing a configuration example of the delay circuit 10, and the delay time changes according to the power supply voltage Vdd.
FIG. 6 is a circuit diagram showing a configuration example of the phase comparison circuit 9. The delay circuit 10 includes pMOS transistors 24-27 and nMO
It is composed of S transistors 28 to 31. The phase comparison circuit 9 includes inverters 32-34, an OR circuit 35, and an AND
It comprises circuits 36 and 37 and NOR circuits 38-40.

Next, the operation of the delay time comparison circuit of FIG. 4 will be described with reference to the drawings. 7 and 8 show operation waveforms of the delay time comparison circuit of FIG. Clock signal CL
When K is applied to delay circuit 10, this clock signal C
The LK delay signal DLY is output from the delay circuit 10.
If the delay signal DLY of this delay circuit 10 is
Is greater than one cycle of the clock signal CLK and less than 1.5 cycles, the clock signal CLK and the delay signal DLY
Pulse signal corresponding to the phase difference is outputted as an up signal UP. At this time, the down signal DOWN is fixed at a low level. The pulse signal of the up signal UP is p
When applied to the MOS transistor 22, a current flows through the transistor 22, the resistor 61 and the resistor 62, the capacitor 55 is charged up, and the delay time measurement signal Td
The ly potential increases. Conversely, as shown in FIG. 8, when the delay time of the delay circuit 10 is smaller than one cycle of the clock signal CLK and larger than 0.5 cycle, the pulse signal corresponding to the phase difference between the clock signal CLK and the delay signal DLY is down. Output as signal DOWN. At this time, the up signal UP is fixed at a low level. Down signal DOW
When the N pulse signal is given to the nMOS transistor 23, the resistance 62, the resistance 61, the nMOS transistor 23
, The capacitor 55 is charged down, and the potential of the delay time measurement signal Tdly decreases. The delay time of the delay circuit 10 changes according to the power supply voltage Vdd.
Since there is a correlation with the delay time of the I circuit 7, the LSI circuit 7
Can be artificially measured.

Next, a detailed configuration of the external circuit detection section 4 will be described. FIG. 9 is a block diagram illustrating a configuration example of the external circuit detection unit 4. Two inputs of the subtraction circuit 11 are connected to a terminal 103 and a terminal 102. Subtraction circuit 11
From the voltage Vout of the terminal 102 to the voltage Vd of the terminal 103
A voltage proportional to the result of subtracting d is output to the terminal 111 as a difference signal Tdiff. The difference signal Tdiff output from the subtraction circuit 11 is input to the two comparison circuits 12 and 13 and compared with the reference potentials Tref1 and Tref2, respectively, and the result becomes two inputs of the XOR circuit 14 and the output of the XOR circuit 14 The result is the comparison signal Tchk
Is output to the terminal 105. The comparison circuits 12 and 13 output a high level when the input signal is smaller than the reference signal, and output a low level when the input signal is larger than the reference signal.

Next, the operation of the external circuit detector 4 of FIG. 9 will be described. The subtraction circuit 11 outputs a difference voltage Tdiff proportional to a voltage obtained by subtracting another input voltage Vdd from the voltage Vout input thereto. Differential voltage Tdiff
Is input to the comparison circuit 12 and the comparison circuit 13 and compared with the comparison voltage Tref1 and the comparison voltage Tref2, respectively. Here, the comparison voltage Tref1 is set by changing the ratio of the resistors 67 and 68 to a voltage slightly higher than the difference voltage Tdiff when the voltage Vout is equal to the voltage Vdd, and the comparison voltage Tref2 is set to the voltage Vout and the voltage Vd.
If the setting is performed by changing the ratio of the resistor 69 and the resistor 70 to a voltage slightly lower than the differential voltage Tdiff when d is equal, when the voltage Tdiff is lower than Tref2,
The outputs of the comparison circuits 12 and 13 are both at a high level, and the output Tchk of the XOR circuit 14 is at a low level. Tdiff is higher than Tref2 and Tref1
When it is lower, the output of the comparison circuit 12 becomes high level, the output of the comparison circuit 13 becomes low level, and the XOR circuit 14
Output Tchk attains a high level. Tdiff is Tr
When it is higher than ef1, the outputs of the comparison circuits 12 and 13 are both at a low level, and the output Tchk of the XOR circuit 14 is at a low level. FIG. 10 shows the relationship between these signals. As a result, the external circuit detection unit 4 is connected to the terminal 103
Is substantially equal to the voltage Vdd applied to the terminal 102, the output signal Tchk is at a high level; otherwise, the output signal Tchk is at a low level.

Next, a detailed configuration of the transistor control unit 5 will be described. FIG. 11 is a block diagram illustrating a configuration example of the transistor control unit 5. The pulse width modulation circuit 15 outputs a pulse signal T having a duty ratio corresponding to the delay measurement signal Tdly given to the terminal 104.
pls is output to the terminal 114. The transistor control changeover switch 17 is at a high level and the pulse signal T
pls, the delay measurement signal Tdly, and one of four signals of the ground level are selected and output to the input terminal of the buffer circuit 16. The buffer circuit 16 amplifies the input signal and outputs it as a transistor control signal Tctrl to the terminal 106.
Output to The condition determination circuit 18 sets the state of the transistor control changeover switch 17 according to the relationship between the state of the transistor control changeover switch 17 and the external circuit measurement signal Tchk supplied to the terminal 105.

Next, the operation of the transistor control section 5 will be described. First, when the circuit of the external circuit unit 2 in FIG. 1 is made to have the circuit shown in FIG.
External circuit measurement signal Tchk when ctrl is changed
Are shown in FIG. When the Tctrl signal goes high, the Vout signal goes high and Vdd
The signal changes to the middle level, and since the two potentials are different, the Tchk signal is at the low level. Next, Tct
When the rl signal is set to low level and waits for a sufficiently long time, Vo
The out signal and the Vdd signal both go low, and Tc
The hk signal goes high. FIG. 2 shows the circuit of the external circuit unit 2 of FIG. 1 for performing the series regulator operation.
In case (b), the Vout signal and the Vdd signal are short-circuited and therefore always equal, and the Tchk signal is always at the high level. When the circuit of the external circuit unit 2 in FIG. 1 is operated as shown in FIG. 2C to perform the separate power supply operation, the Vout signal is substantially the same as the voltage of the external power supply 6 when the transistor 1 is on, and when the transistor 1 is off. Means that this voltage is
4 stored. The Vdd signal becomes equal to the voltage of the external power supply 6, and when these voltages are different, Tchk is always a low level signal. Table 1 summarizes these relationships.

[0036]

[Table 1] The external circuit unit 2 is determined using this relationship, and a method of controlling the transistor can be selected. FIG. 13 is a flowchart showing the procedure of the determination by the condition determination circuit 18. When the condition determination circuit 18 starts setting, first, the changeover switch 17 is connected to SW1, and the transistor 1 is turned on (step 301). Next, the level of the signal Tchk is checked (step 302). When the value is high, the changeover switch 17 is connected to SW3 (step 303), and the setting ends. When the level of the signal Tchk is low, the switch 17 is connected to SW4, and the transistor 1 is turned off (step 304).
After a sufficient time, the signal Tchk is checked (step 3).
05), changeover switch 1 when the value is high level
7 is connected to SW2 (step 306), and the setting ends. When the value of the signal Tchk is at the low level, the switching switch is connected to SW1 (step 307), and the setting ends.

When the changeover switch 17 is connected to SW2, the delay measurement signal Tdly applied to the terminal 104
A pulse signal having a duty ratio corresponding to the terminal 106 is referred to as a transistor control signal Tctrl.
Given to. When the changeover switch 17 is connected to SW3, a transistor control signal Tctrl having a voltage proportional to the delay measurement signal Tdly is supplied to the terminal 106.
Given to. When the changeover switch 17 is connected to SW1, the transistor control signal Tctrl is fixed at a high level.

FIG. 14 is a block diagram of a voltage conversion circuit according to a second embodiment of the present invention. This embodiment is different from the first embodiment of FIG. 1 only in that the transistor 1 is provided outside the LSI 92. Transistor 1 is LSI92
Although there is a drawback that the number of external components is increased by connecting to the outside, there is also an advantage that the influence of heat generated by the power consumed by the transistor 1 is less likely to reach the LSI 92.

FIG. 15 is a block diagram of a voltage conversion circuit according to a third embodiment of the present invention. The present embodiment is different from the embodiment of FIG.
The difference is that the setting circuit 19 is provided outside the SI 93. The setting circuit 19 has a mechanism for notifying the configuration of the external circuit section 2 to the transistor control section 5, and can be realized by, for example, a combination of a 2-bit pull-up or pull-down circuit. By doing so, it is not necessary to perform the setting sequence shown in FIG. 13, so that the time for detecting the external circuit unit 2 can be reduced.

[0040]

As described above, the present invention has the following effects. (1) Since the control method of the voltage conversion circuit can be switched according to the purpose of use, the voltage conversion circuit can be built in the LSI while allowing a wide range of use. As a result, the external voltage conversion circuit can be simplified, and the device configuration can be simplified. (2) According to the third aspect of the present invention, the output voltage is controlled with reference to the result of the delay time measurement circuit prepared in the LSI, so that the output voltage of the voltage conversion circuit can be optimized.
As a result, unnecessary output voltage margin becomes unnecessary, and power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a voltage conversion circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating a configuration example of an external circuit unit 2.

FIG. 3 is a time chart illustrating an operation of the voltage conversion circuit of FIG. 1;

FIG. 4 is a block diagram illustrating a configuration example of a delay time measuring unit 3;

FIG. 5 is a circuit diagram showing a configuration example of a delay circuit 10;

FIG. 6 is a circuit diagram showing a configuration example of a phase comparison circuit 9;

FIG. 7 is a time chart illustrating an operation of the delay time measuring unit 3;

FIG. 8 is another time chart showing the operation of the delay time measuring unit 3;

FIG. 9 is a block diagram illustrating a configuration example of an external circuit detection unit 4.

FIG. 10 is a time chart illustrating an operation of the external circuit detection unit 4;

11 is a block diagram illustrating a configuration example of a transistor control unit 5. FIG.

FIG. 12 is a time chart illustrating a detection principle of the external circuit detection unit 4.

FIG. 13 is a flowchart showing an operation of the condition determination detection circuit 11;

FIG. 14 is a block diagram illustrating a voltage conversion circuit according to a second embodiment of the present invention.

FIG. 15 is a block diagram illustrating a voltage conversion circuit according to a third embodiment of the present invention.

FIG. 16 is a block diagram showing a conventional example of a voltage conversion circuit.

FIG. 17 is a block diagram showing another conventional example of a voltage conversion circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 transistor 2 external circuit section 3 delay time measurement section 4 external circuit detection section 5 transistor control section 6 external power supply 7 LSI circuit 8 power supply 9 phase comparison circuit 10 delay circuit 11 subtraction circuit 12 to 13 comparison circuit 14 XOR circuit 15 pulse width Modulation circuit 16 Buffer 17 Changeover switch 18 Condition judgment circuit 19 Setting circuit 20 Constant voltage power supply circuit 21 Inverter 22 pMOS transistor 23 nMOS transistor 24 to 27 pMOS transistor 28 to 31 nMOS transistor 32 to 33 inverter 35 OR circuit 36 to 37 AND circuit 38 -40 NOR circuit 41-42 Inductor 45-46 Diode 51-56 Capacitor 61-72 Resistance 81-84 Operational amplifier 91-93 LSI 101-118 terminal 201 terminal Waveform indicating the potential of terminal 202 202 Waveform indicating the potential of terminal 103 203 Waveform indicating the potential of terminal 102 204 Waveform indicating the potential of terminal 103 205 Waveform indicating the potential of terminal 102 206 Waveform indicating the potential of terminal 103 207 Terminal 107 Waveform indicating the potential 208 Waveform indicating the potential of the terminal 108 209 Waveform indicating the potential of the terminal 109 210 Waveform indicating the potential of the terminal 110 211 Waveform indicating the potential of the terminal 104 212 Waveform indicating the potential of the terminal 107 213 Waveforms shown 214 Waveforms showing the potential of terminal 109 215 Waveforms showing the potential of terminal 110 216 Waveforms showing the potential of terminal 104 217 Waveforms showing the potential of terminal 111 218 Waveforms showing the potential of terminal 112 219 Waveforms showing the potential of terminal 113 220 Waveform indicating potential of terminal 105 221 terminal Waveforms showing the potential of 06 222 Waveforms showing the potential of the terminal 102 223 Waveforms showing the potential of the terminal 103 224 Waveforms showing the potential of the terminal 105 225 Waveforms showing the potential of the terminal 106 226 Waveforms showing the potential of the terminal 102 227 Waveform indicating the potential 228 Waveform indicating the potential of the terminal 105 229 Waveform indicating the potential of the terminal 106 230 Waveform indicating the potential of the terminal 102 231 Waveform indicating the potential of the terminal 103 232 Waveform indicating the potential of the terminal 105 301 to 307 Steps

Claims (8)

(57) [Claims] 1. A voltage conversion circuit for generating a voltage to be supplied to an LSI circuit, comprising: a transistor built in or external to the LSI, one end of which is connected to an external power supply, and one end of which is the other end of the transistor. And from the other end,
An external circuit unit external to the LSI for supplying a power supply voltage used by the LSI circuit to the LSI; an external circuit detection unit built in the LSI for detecting a type of the external circuit unit A voltage conversion circuit having a transistor control unit built in the LSI, which controls the transistor according to a type of the external circuit unit detected by the external circuit detection unit. 2. The external circuit section comprises:
The voltage conversion circuit according to claim 1, wherein the voltage conversion circuit is supplied by a switching regulator operation, a series regulator operation, or from another power supply. 3. The method of claim 1, wherein the delay time of the LSI circuit is artificially measured using the same power supply voltage as that of the LSI circuit.
3. The voltage conversion circuit according to claim 1, further comprising a delay time measuring unit built in the SI, wherein the transistor control unit further controls the transistor by referring to the magnitude of the delay time. 4. The transistor control section, wherein when the external circuit section generates a power supply voltage by a switching regulator operation, the transistor control section turns on / off the transistor alternately by a transistor control signal having a pulse waveform, and the delay time Changing the duty ratio of the transistor control signal to be constant,
When the external circuit unit generates a power supply voltage by a series regulator operation, a transistor control signal for performing a series regulator operation is output to the transistor, and a level of the transistor control signal is set so that the delay time is constant. 4. The voltage conversion circuit according to claim 3, wherein when the external circuit supplies a power supply voltage from another power supply, the transistor outputs a transistor control signal that always turns on the transistor to the transistor. 5. An external circuit detecting unit, comprising: a subtraction circuit that outputs a voltage proportional to a result obtained by subtracting a voltage at one end of the external circuit unit from a voltage at another end as a differential voltage; A first comparison circuit for comparing the difference voltage with a first comparison voltage slightly higher than the difference voltage when the voltages at both ends are equal, and a second comparison voltage slightly lower than the difference voltage when the voltages at both ends are equal; A second comparison circuit for comparing the difference voltage with a first logic level when the difference voltage is larger than the first comparison voltage and when the difference voltage is smaller than the second comparison voltage; The voltage conversion circuit according to claim 1, further comprising a gate circuit that outputs a signal of a second logic level during the comparison voltage. 6. The pulse width modulation circuit for outputting a pulse signal having a duty ratio corresponding to the magnitude of the delay measurement signal of the delay time measurement unit, the transistor control unit including a high level signal, the pulse signal, and the delay signal. A transistor control changeover switch for selecting one of four signals of the measurement signal and the ground level; a buffer circuit for amplifying a signal selected by the transistor control changeover switch and outputting the amplified signal as a transistor control signal; The transistor control changeover switch is switched to check the output of the external circuit detection section, and when the output is at the second logic level, the transistor control changeover switch is switched so as to select the delay measurement signal. Switching the transistor control changeover switch so that the transistor is turned off when is at a first logic level, and switching the transistor control changeover switch so as to select the pulse signal when the output is at a second logic level; 6. The voltage conversion circuit according to claim 5, further comprising a condition determination circuit that controls said transistor control switch so that said transistor is turned on when an output is at a first logic level. 7. The delay time measuring section, using the power supply voltage, delays a clock signal and outputs a delay signal, and compares a phase of the clock signal with the phase of the delay signal . phase difference resulting in size than one period of the clock signal Itoki active up signal, and outputs an inactive down signal, the phase difference is smaller than one period of the clock signal Itoki inactive up signal,
A phase comparison circuit that outputs an active down signal, a first transistor that is connected at one end to a power supply, is turned on by the up signal, and is connected between the first transistor and ground and is turned on by the down signal. 2
And a capacitor connected between the connection point of the first and second transistors and the ground, and outputs the potential of the capacitor as the delay time.
The voltage conversion circuit as described. 8. A voltage conversion circuit for generating a voltage to be supplied to an LSI circuit, comprising: a transistor externally connected to the LSI and having one end connected to an external power supply; one end connected to the other end of the transistor; From the end,
An external circuit unit external to the LSI, which supplies a power supply voltage used by the LSI circuit to the LSI; a setting circuit external to the LSI, for setting a type of the external circuit unit; Controlling the transistor according to the type of the external circuit unit set by the setting circuit;
A voltage conversion circuit having a transistor control unit built in the device.