TW200424543A - A method and apparatus for detecting on-die voltage variations - Google Patents
A method and apparatus for detecting on-die voltage variations Download PDFInfo
- Publication number
- TW200424543A TW200424543A TW093103316A TW93103316A TW200424543A TW 200424543 A TW200424543 A TW 200424543A TW 093103316 A TW093103316 A TW 093103316A TW 93103316 A TW93103316 A TW 93103316A TW 200424543 A TW200424543 A TW 200424543A
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- Taiwan
- Prior art keywords
- voltage
- attenuation
- coupled
- detector
- frequency
- Prior art date
Links
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- 238000001514 detection method Methods 0.000 claims description 7
- 230000007423 decrease Effects 0.000 claims description 6
- 230000009467 reduction Effects 0.000 claims description 5
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 238000010168 coupling process Methods 0.000 claims description 3
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- 238000004519 manufacturing process Methods 0.000 description 7
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Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
- G01R19/16504—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the components employed
- G01R19/16519—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the components employed using FET's
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01K—MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR
- G01K7/00—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements
- G01K7/32—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements using change of resonant frequency of a crystal
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
- G01R19/16533—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application
- G01R19/16538—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application in AC or DC supplies
- G01R19/16552—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application in AC or DC supplies in I.C. power supplies
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
- G01R19/16566—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/27—Testing of devices without physical removal from the circuit of which they form part, e.g. compensating for effects surrounding elements
- G01R31/275—Testing of devices without physical removal from the circuit of which they form part, e.g. compensating for effects surrounding elements for testing individual semiconductor components within integrated circuits
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/08—Clock generators with changeable or programmable clock frequency
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Power Engineering (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Semiconductor Integrated Circuits (AREA)
- Measurement Of Current Or Voltage (AREA)
Abstract
Description
玖、發明說明： 【日月戶斤冷貝 背景 本發明貫施例係關於積體電路領域並且，尤其是，關 於檢測晶粒上溫度及/或電壓變化。 於咼頻率積體電路中，例如，微處理機，電壓及/或溫 度之變化可導致頻率惡化。目前，昂貴的資源可以被使用 以，例如，控制電壓變化而避免此類惡化。 I：發明内容3 一些實例中，為防止功能失效，電壓邊限被添加至供 應電壓使得對於最大供應電壓衰減，積體電路之操作頻率 仍然被保持。但是，這方法可能在大部份時間導致積體電发明, Description of the invention: [Sun, Moon, and Pound Cold Shell Background] The embodiments of the present invention relate to the field of integrated circuits and, in particular, to detecting changes in temperature and / or voltage on a die. In chirped frequency integrated circuits, such as microprocessors, changes in voltage and / or temperature can cause frequency degradation. Currently, expensive resources can be used, for example, to control voltage changes to avoid such deterioration. I: Summary of the Invention 3 In some examples, to prevent functional failure, a voltage margin is added to the supply voltage so that the maximum operating voltage is attenuated and the operating frequency of the integrated circuit is still maintained. However, this method may cause
路衣置彳木作之顯著功率增加，即使僅稀少地發生之電 減被補償。 I ^田，貝《电路裝置操作頻率持續增加時，衰減振幅同 二，包•之—比例持續增加。對於—些積體電路，复 供必需的電壓邊限以保護由於功率和成本限制: 、π- 6凡口月 ^ H明實施例利用範例而展示且不受限制於附圖 7二中相同之參考編號指示相似元件，並且其中. 塊圖第i圖是—實施例之適應式頻率時脈系统的高位 200424543 第2圖是可以被使用於第1圖之適應式頻率時脈系統中 的實施例之衰減（電壓）檢測器分解圖和方塊圖。 第3圖是可以被使用於第1圖之適應式頻率時脈系統中 的另一實施例之電壓檢測器分解圖和方塊圖。 5 第4圖是可以被被使用於第1圖之適應式頻率時脈產生 電路中的一實施例之衰減/電壓檢測器方塊圖。 第5圖是可以被使用於第4圖之衰減/電壓檢測器中的 實施例之數位類比至數位轉換器分解圖。 第6圖是更詳細地展示第4圖之衰減/電壓檢測器的分 10 解圖。 第7圖是展示第6圖衰減檢測器用以追蹤衰減歷史之另 一應用的方塊圖。 第8圖是可以被使用於，例如，衰減監視的另一實施例 之衰減檢測器分解圖和方塊圖。 15 第9圖是可以被使用以控制第8圖衰減檢測器中之環式 震盪器之反向電壓感應電路分解圖和方塊圖。 第10圖是可以被使用於，例如衰減監視之另一實施例 之衰減檢測器分解圖和方塊圖。 第11圖是可以被使用於一實施例中以追蹤衰減歷史之 20 電路製作方塊圖。 第12圖是使用一實施例之衰減及/或溫度檢測器的一 實施例之積體電路的高位準方塊圖。 第13圖是使用一實施例之一組或多組衰減監視電路的 一實施例之積體電路的高位準方塊圖。 6 200424543 第14圖是使用一實施例之衰減及/或溫度檢測器的一 實施例之系統方塊圖。 第15圖是一流程圖，其展示用以檢測晶粒上電壓衰減 及/或溫度變化之一實施例的方法。 第16圖是可以有利地被使用於第6圖之實施例中之充 電電晶體製作範例之分解圖。 【實施方式】 詳細之說明 用以數位地檢測積體電路晶粒上之電壓及/或溫度變 10化的方法和裝置被說明。下面的說明中，所說明之特定型 式的積體電路、電路組態、系統組態、等等僅為展示。但 是，應了解，其他的實施例亦可應用於其他型式的積體電 路、電路組態及/或系統組態中。 於一實施例中，檢測一溫度或者電壓位準之檢測器接 15 收一組大致固定之第一電壓並且反應於被檢測之第二電壓 的溫度或者位準而輸出-域碼錢。控制電路反應於該 數碼信號而決定-組時脈信號頻率。此檢測器可以被使 用’例如，於適應式頻率時脈產生電路中以決定輸出頻率， 例如參考下面第頂之說明。這些和其他實施例之進一步詳 細說明將在下面提供。 第1圖是依據-實施例之適應式 的高位準方塊圖。如下面更詳細之戈明丰日樣產生電路100 用以提供㈣《«或者其他㈣電路2料以被使 作所需的適應式時脈方法。 頻率操 20 200424543 適應式頻率時脈產生電路100包含一組同步時脈產生 為（相位鎖定迴路(PLL))l〇5、除N電路110、多工器（mux)115 以及電壓衰減(及/或溫度)檢測器12〇。操作中，pLL 1〇5在 輸入接收一組參考時脈信號(RefCLK)並且，配合產生回授 5日守脈信號(FBCLK)之除N電路11〇，提供具有第一頻率F1之 車父南頻率輸出時脈信號。應了解，除N電路110中之N值可 以是依據頻率F1對參考時脈信號RefCLK頻率之所需的多 組比率值之任何一組。 其他的時脈產生器（未展示出），單獨地或者配合時脈相 1〇除或者相乘電路(未展示出），以相似方式操作以產生具有不 同頻率，例如F2."Fn的時脈信號，如第i圖之展示。 同日守地’衰減檢測器120接收指示相關電壓位準，例 如’ Vcc及/或相關之溫度指示器之輸入信號。vcc輸入信號 可以彳文電壓供應被接收，而相關溫度之輸入信號可以從， 15例如，晶粒上溫度感知器被接收。依據被接收之輸入信號， 衰減檢測器120提供一組頻率數碼125或者其他的控制信號 以導致多工器115選擇地在輸出130輸出具有頻率F1…Fn之 其中一組的時脈信號OutCLK。被選擇之時脈信號〇utCLK 可以被使用於時脈核心電路，例如，於包含適應式頻率時 20脈電路100之主系統積體電路上。 依據包含’例如，輸出時脈信號OutCLK所需的特性之 因素範圍和製造主系統積體電路的處理程序，pLL 1〇5、除 N電路110以及多工器115各可以使用多種習知PL]L、除N及/ 或多工裔设计之任一種而被製作。 8 200424543 於一實施例中，第1圖之衰減檢測器120和多工器115可 以使用，例如，第2圖之衰減檢測器220和控制與多工電路 215而被製作。衰減檢測器220包含由串聯-耦合電阻器R1、 R2和R3所形成之分壓器22ι，各電阻器可以使用，例如， 5 n-型或者P-型金屬氧化物半導體(PMOS)電阻器被製作。被 使用的電阻器型式可以依據例如，分壓器所需的精確度、 可用的區域（面積）以及所需的複雜性等因素而被決定。其中 一組或多組電阻器Rl、R2及/或R3使用PMOS裝置被製作， PMOS裝置可以被估量尺寸大小以減少晶粒上變化效應。 10 於一實施例中，衰減檢測器220同時也包含引動裝置 222和比較器224、226與228，其可以使用多種習知的比較 裔設計之任何一種被製作以提供下面所說明之功能。 操作中，分壓器221從，例如，固定之類比電源供應23〇 而接收大致固定之參考電壓。該固定類比電源供應23〇也可 15以被使用作為一組供用於主系統積體電路晶片上的其他電 路之供應，例如一組或者多組PLL，以至於不需要提供衰減 檢測器220另外的電源供應。 當在引動裝置222之輸入被接收的引動信號為高位 時，引動裝置222被導通，因此，衰減檢測器221也被導通。 2〇 引動信號可以利用其他晶粒上電路（未展示出）被產生或者 可以從外部來源被接收。 比較器224、226和228各接收一組數位供應電壓vcc， 其同時也被提供至其他的周遭電路。於這實施例中，Vcc 是被衰減檢測器220所監視之電壓。反應於被引動之衰減檢 9 200424543 測器220，比較器224、226和228分別地比較Vcc與參考電壓 VI、V2和 V3 〇 於一實施例中，電路220可以被設計以至於 Vcc>V1>V2>V3。當Vcc衰減時，如果其下降至第一參考電 5 壓V1之下，則比較器224之輸出outi被確定。如果Vcc進一 步地衰減，以至於在第二參考電壓V2之下，則輸出信號〇m2 也被確定並且，如果Vcc衰減至第三參考電壓V3之下，則 輸出信號out3也被確定。 輸出信號outl、out2和out3被提供作為至控制和多工電 10 路215之選擇或者控制信號並且可以對應至檢測器220被使 用於適應式頻率時脈應用之實施例中的第1圖頻率數碼信 號。依據選擇信號outl、out2和out3值，多工器215選擇， 第2圖實施例範例中，如展示之具有頻率FI、F2、F3以及F4 之輸入信號的其中一組，以提供具有頻率Fout之輸出信號 15 OutCLK 〇具有頻率FI、F2、F3和F4之信號可以被產生，如 上述參考第1圖之說明。於這實施範例中，〇utCLK信號之 頻率可以依據表1而被選擇，例如： out3 out2 outl Fout 0 0 0 FI 0 0 1 F2 0 1 1 F3 1 1 1 F4 (表1) 參考電壓VI、V2和V3目標值和因此被選擇的電阻器 20 Rl、R2和R3值以及經由引動裝置222之電流是取決於電路 10 200424543 設計者所要求導致輸出時脈信號頻率被調整之目標行程 點。所需的行程點取決於，例如，供用於VCC之指定值、被 預期的電壓衰減、設計邊限以及熟習本技術者應了解的其 他技術方面的考慮等因素。 5 經由分壓器221之電流以及因此在分壓器221輸出之電 壓VI、V2和V3的振幅，利用經由引動裝置222之電流而被 決定。於一實施例中，為改變電壓V1、V2*V3，電流可以 數位地被規劃以依據電阻R1、R2和R3比率而調整電壓參考 值。電流可以利用有效地改變引動電晶體222之尺寸而被改 10變。這可利用，例如，各具有分別引動之併接NM〇s電晶 體以構成裝置222而被達成。電流利用熟習本技術者所習知 的一般技術方式操作那些致動中確定的一組或多組而被調 整。 於一實施例中，一組或多組參考電壓V1、V2&/4V3 15值可以在衣造之後利用調整一組或多組電阻R1、R2及/或R3 而刀別地或者另外地被操縱。例如，其中電阻器Rl、及 /或R3被製作作為PM0S電阻器，電阻值可利用簡單地將這 些PMOS衣置加上腳部（製作較小但併接之電晶體而取代一 組大電晶體)且連接或者不連接不同的腳部（僅經由金屬）而 20被調整以因此操縱實際的裝置尺寸以及電阻。 應了解’雖然三組參考電壓被使用於第2圖衰減檢測器 中，以在四組不同的信號頻率之間選擇，於另一實施例， -組不同的參考電壓數目可以被提供並且以相似方式被使 用以在不同的輸出信號頻率數目之間選擇。進一步地，雖 11 200424543 “、、▲方員比a源供應接收—組固定電壓的分壓器被使用以提 仏第2@之電路麥考電壓，其他的方法，例如，使用帶間隙 以產生參考電壓，可以被使用於其他的實施例中。 進一步地，雖然檢測器220檢測供應電壓Vcc之變化， 5具有相似組態之檢測器可另外地被使用以檢測溫度改變。 於此實施例中，與溫度相關的參考和可變化信號以相似方 式被比較以選擇一組輸出信號頻率。 第3圖展不，另一貫施例之電壓衰減檢測器320和相關 的多工器315可以被使用，例如，以提供第i圖檢測器12〇和 10多工器115。於第3圖展示之實施例中，衰減檢測器32〇包含 攸固疋電源供應330被供應一組固定供應電壓之第一延遲 元件鏈路322以及從數位電源供應接收一組供應電壓vcc之 第二延遲元件鏈路324。於這實施例中，供應電壓Vcc被衰 減檢測器320所監視並且固定電源供應，如上所述地，可以 15疋組類比電源供應，其被使用以供電給予相同積體電路 上的其他電路。一實施例之檢測器320也包含相位檢測器 332、334和336以及緩衝器338，其各可使用此類電路習知 的設計被製作，以提供此處說明的相關特點。 從固定供應330接收固定供應電壓之第一延遲元件鏈 20路322提供一組輸入信號(：尺之對於數位電源供應變化不敏 感的一組參考通道延遲Dref。對照地，經由第二延遲元件 鏈路324之延遲依據Vcc振幅而變化。 於一實施例中，於延遲元件鏈路324中間之分接頭提供 一組具有延遲D3之第一延遲信號，在延遲元件鏈路324中第 12 200424543 二延遲元件之後的分接頭提供一組具有延遲D2之第二延遲 "[口號並且鍵路324之輸出提供具有延遲di的第三延遲信 號。一實施例中之檢測器32〇可以被設計，以至於The significant power increase of the road clothes placed in the cypress is compensated even if the electricity reduction that occurs only rarely. When the operating frequency of the circuit device continues to increase, the attenuation amplitude is the same, and the ratio continues to increase. For some integrated circuits, the necessary voltage margins are provided to protect due to power and cost restrictions: π-6 where ^^ The embodiment is shown using examples and is not limited to the same as in Figure 7 The reference numbers indicate similar elements, and among them, the block diagram, figure i is-the high order of the adaptive frequency clock system of the embodiment 200424543. Figure 2 is an example of the adaptive frequency clock system that can be used in Figure 1 Exploded view and block diagram of the attenuation (voltage) detector. Fig. 3 is an exploded view and a block diagram of a voltage detector of another embodiment which can be used in the adaptive frequency clock system of Fig. 1. 5 Figure 4 is a block diagram of an embodiment of an attenuation / voltage detector that can be used in the adaptive frequency clock generation circuit of Figure 1. Figure 5 is an exploded view of a digital analog-to-digital converter of the embodiment that can be used in the attenuation / voltage detector of Figure 4. Figure 6 is a detailed diagram showing the attenuation / voltage detector of Figure 4 in more detail. Figure 7 is a block diagram showing another application of the attenuation detector of Figure 6 to track attenuation history. Fig. 8 is an exploded view and a block diagram of an attenuation detector which can be used, for example, in another embodiment of attenuation monitoring. 15 Figure 9 is an exploded and block diagram of the reverse voltage sensing circuit that can be used to control the ring oscillator in the attenuation detector of Figure 8. Fig. 10 is an exploded view and a block diagram of an attenuation detector which can be used in, for example, another embodiment of the attenuation monitoring. Figure 11 is a block diagram of a 20 circuit that can be used in an embodiment to track the attenuation history. Fig. 12 is a high-level block diagram of an integrated circuit of an embodiment using an attenuation and / or temperature detector of an embodiment. Fig. 13 is a high-level block diagram of an integrated circuit of an embodiment using one or more sets of attenuation monitoring circuits of an embodiment. 6 200424543 Figure 14 is a block diagram of a system using an embodiment of an attenuation and / or temperature detector. Fig. 15 is a flowchart showing a method for detecting one embodiment of voltage decay and / or temperature change on a die. Fig. 16 is an exploded view of an example of the fabrication of a charging transistor which can be advantageously used in the embodiment of Fig. 6. [Embodiment] Detailed description A method and an apparatus for digitally detecting a change in voltage and / or temperature on a chip of a integrated circuit are described. In the following description, the specific types of integrated circuits, circuit configurations, system configurations, etc. described are for illustration only. However, it should be understood that other embodiments may be applied to other types of integrated circuits, circuit configurations, and / or system configurations. In one embodiment, a detector that detects a temperature or voltage level receives a set of approximately first voltages and outputs a domain code money in response to the temperature or level of the detected second voltage. The control circuit determines the frequency of the group clock signal in response to the digital signal. This detector can be used, for example, in an adaptive frequency clock generation circuit to determine the output frequency. For example, refer to the description at the top of the following. Further detailed descriptions of these and other embodiments are provided below. FIG. 1 is a high-level block diagram of the adaptive type according to the embodiment. As described in more detail below, the Gemingfeng day sample generating circuit 100 is used to provide the "« or other "circuit materials to be used as the adaptive clock method required. Frequency operation 20 200424543 Adaptive frequency clock generation circuit 100 includes a set of synchronous clock generation (Phase Locked Loop (PLL)) 105, N division circuit 110, multiplexer (mux) 115, and voltage attenuation (and / Or temperature) detector 12o. In operation, pLL 105 receives a set of reference clock signals (RefCLK) at the input and cooperates with a divide-by-N circuit 11 which generates a feedback 5-day clock signal (FBCLK) to provide a car with a first frequency F1. Frequency output clock signal. It should be understood that the value of N in the divide-by-N circuit 110 may be any one of a plurality of sets of ratio values required according to the frequency F1 to the frequency of the reference clock signal RefCLK. Other clock generators (not shown), individually or in conjunction with a clock phase division of 10 or a multiplication circuit (not shown), operate in a similar manner to generate clocks with different frequencies, such as F2. &Quot; Fn Pulse signal, as shown in Figure i. The same-day ground-holding 'attenuation detector 120 receives input signals indicating related voltage levels, such as' Vcc and / or related temperature indicators. The vcc input signal can be received with a text voltage supply, and the temperature-dependent input signal can be received from, for example, a temperature sensor on the die. Based on the received input signal, the attenuation detector 120 provides a set of frequency digital 125 or other control signals to cause the multiplexer 115 to selectively output a clock signal OutCLK having a set of frequencies F1 ... Fn at the output 130. The selected clock signal OUTCLK can be used in a clock core circuit, for example, on a main system integrated circuit including an adaptive frequency clock 20 clock circuit 100. Depending on the range of factors including, for example, the characteristics required to output the clock signal OutCLK and the processing procedure for manufacturing the integrated circuit of the main system, pLL 105, the N-removing circuit 110, and the multiplexer 115 each can use a variety of conventional PLs] L, except for N and / or multi-worker designs. 8 200424543 In one embodiment, the attenuation detector 120 and the multiplexer 115 of FIG. 1 can be used. For example, the attenuation detector 220 and the control and multiplexing circuit 215 of FIG. 2 are manufactured. The attenuation detector 220 includes a voltage divider 22m formed by series-coupling resistors R1, R2, and R3. Each resistor can be used, for example, a 5 n-type or P-type metal oxide semiconductor (PMOS) resistor. Production. The type of resistor used can be determined based on factors such as the required accuracy of the voltage divider, the area (area) available, and the required complexity. One or more sets of resistors R1, R2, and / or R3 are fabricated using PMOS devices. The PMOS devices can be sized to reduce the effect of changes on the crystal grains. 10 In one embodiment, the attenuation detector 220 also includes an actuator 222 and comparators 224, 226, and 228, which can be made using any of a variety of conventional comparative designs to provide the functions described below. In operation, the voltage divider 221 receives a substantially fixed reference voltage from, for example, a fixed analog power supply 23. The fixed analog power supply 23 can also be used as a set of supplies for other circuits on the main system integrated circuit chip, such as one or more PLLs, so that it is not necessary to provide an attenuation detector 220. power supply. When the activation signal received at the input of the activation device 222 is high, the activation device 222 is turned on, and therefore, the attenuation detector 221 is also turned on. 20 The trigger signal can be generated using other on-die circuits (not shown) or can be received from an external source. Comparators 224, 226, and 228 each receive a set of digital supply voltages vcc, which are also provided to other surrounding circuits. In this embodiment, Vcc is the voltage monitored by the attenuation detector 220. In response to the induced attenuation test 9 200424543 detector 220, comparators 224, 226, and 228 respectively compare Vcc with reference voltages VI, V2, and V3. In one embodiment, circuit 220 may be designed so that Vcc > V1 > V2 > V3. When Vcc is attenuated, if it drops below the first reference voltage V1, the output outi of the comparator 224 is determined. If Vcc is further attenuated so that it is below the second reference voltage V2, the output signal 0m2 is also determined and if Vcc is attenuated below the third reference voltage V3, the output signal out3 is also determined. The output signals outl, out2, and out3 are provided as selection or control signals to the control and multiplexing circuit 10 215 and can correspond to the frequency digital figure 1 in the embodiment where the detector 220 is used for adaptive frequency clock applications. signal. According to the values of the selection signals outl, out2, and out3, the multiplexer 215 selects. In the example of the embodiment in FIG. 2, one of the input signals with frequencies FI, F2, F3, and F4 is shown to provide a signal with the frequency Fout Output signal 15 OutCLK. Signals with frequencies FI, F2, F3, and F4 can be generated, as described above with reference to Figure 1. In this example, the frequency of the OUTCLK signal can be selected according to Table 1, for example: out3 out2 outl Fout 0 0 0 FI 0 0 1 F2 0 1 1 F3 1 1 1 F4 (Table 1) Reference voltage VI, V2 The target value of V3 and the resistors 20 R1, R2, and R3 thus selected and the current through the actuator 222 are determined by the target stroke point required by the designer of circuit 10 200424543 to cause the frequency of the output clock signal to be adjusted. The required travel points depend on factors such as the specified value for VCC, the expected voltage attenuation, design margins, and other technical considerations that a person skilled in the art should understand. 5 The current through the voltage divider 221 and therefore the amplitudes of the voltages VI, V2 and V3 output at the voltage divider 221 are determined using the current through the actuator 222. In one embodiment, in order to change the voltages V1, V2 * V3, the current can be digitally planned to adjust the voltage reference value according to the ratio of the resistors R1, R2, and R3. The current can be changed by effectively changing the size of the driving transistor 222. This can be achieved using, for example, each having a parallel-connected NMOS electrical crystal which is separately activated to constitute the device 222. The current is adjusted by operating one or more of the groups identified in the actuation using general techniques known to those skilled in the art. In one embodiment, one or more sets of reference voltages V1, V2 & / 4V3 15 values can be manipulated separately or additionally by adjusting one or more sets of resistors R1, R2 and / or R3 after clothing is manufactured. . For example, where the resistors R1 and / or R3 are made as PM0S resistors, the resistance value can be simply added to these PMOS clothes with feet (make smaller but connected transistors instead of a group of large transistors) ) And with or without different feet (via metal only) 20 is adjusted to thus manipulate the actual device size and resistance. It should be understood that 'though three sets of reference voltages are used in the attenuation detector of Fig. 2 to choose between four different sets of signal frequencies, in another embodiment,-the number of different sets of reference voltages can be provided and similar The mode is used to choose between different numbers of output signal frequencies. Further, although 11 200424543 ",, ▲ square member than a source supply receiving-a set of fixed voltage divider is used to increase the 2 @ circuit McCao voltage, other methods, for example, using a gap to generate The reference voltage may be used in other embodiments. Further, although the detector 220 detects a change in the supply voltage Vcc, a detector with a similar configuration may be additionally used to detect a temperature change. In this embodiment The temperature-dependent reference and changeable signals are compared in a similar manner to select a set of output signal frequencies. Figure 3 shows that the voltage decay detector 320 and the related multiplexer 315 of another embodiment can be used. For example, to provide detector i and detector 10 and multiplexer 115 in Fig. 3. In the embodiment shown in Fig. 3, attenuation detector 32 includes a first power supply 330 which is supplied with a set of fixed supply voltages. The delay element link 322 and a second delay element link 324 that receives a set of supply voltages vcc from the digital power supply. In this embodiment, the supply voltage Vcc is monitored by the attenuation detector 320 and fixed. The fixed power supply, as described above, can be 15 groups of analog power supplies, which are used to supply power to other circuits on the same integrated circuit. The detector 320 of an embodiment also includes phase detectors 332, 334, and 336 and Buffers 338, each of which can be made using a known design of this type of circuit, to provide the relevant features described herein. The first delay element chain 20 receiving 322 from a fixed supply 330 provides a set of input signals ( : A set of reference channel delays Dref that are not sensitive to changes in digital power supply. In contrast, the delay through the second delay element link 324 varies according to the Vcc amplitude. In one embodiment, in the middle of the delay element link 324 The tap provides a set of first delay signals with a delay of D3, the 12th 200424543 in the delay element link 324 after the second delay element provides a set of second delays with a delay of D2 " [slogan and key 324 The output provides a third delayed signal with a delay di. The detector 32 in one embodiment may be designed so that
Dref>Dl>D2>D3 〇 5 操作中，輸入信號CK同時地被發射進入延遲通道322 和324。各相位檢測器332、334和336接著檢測參考延遲通 道322之輸出是否領先或者延遲其他延遲通道324的輸出並 且分別地提供一組對應的輸出信號outl、〇ut2或者〇ut3。例 如，如果Vcc衰減至延遲D1超出Dref之限度，則來自相位檢 10 測裔332之輸出# 5虎〇utl被確定。如果Vcc衰減以至於^一组 或者兩者延遲D2及/或03超出Dref，則對應的輸出信號out2 及/或out3被確定。 輸出信號outl、out2和out3被提供作為至多工和控制電 路315之選擇信號，其接收具有頻率Fi、p2、F3和F4之信號。 15 電路315之組態和操作可以是相似於上述之多工和控制電 路215，而一實施例之電路315則進一步地包含正反器（未展 示出）以在它們被確定之後從相位檢測器332、334和336取 樣輸出信號，以便在時脈信號轉移至低位狀態之前捕獲它 們的值。進一步地，於一實施例中，多工器315依據上述之 2〇 表1而選擇具有頻率Fout之輸出信號。 應了解，雖然電路320使用三組不同的延遲以在四組信 號頻率之間選擇，於另一實施例中，一不同數目的延遲可 以以相似方式被使用及/或信號頻率被選擇。 接著參看第4圖，其展示另一實施例之全面數位檢測器 13 200424543 420高位準方塊圖。於一實施例中’檢測器420可以被使用 以提供第1圖檢測器12〇給予一組適應式頻率時脈系統。於 另一實施例中，檢測器420可以被使用，例如，作為衰減歷 史電路之部份。如所展示，檢測器420包含環式震盈哭 5 (ROSC)422、頻率至電壓轉換器（FVC)424以及數位式類比 至數位轉換器（DADC)426。 在高位準時，環式震盪器422產生一組具有成比例於電 壓和溫度之頻率的輸出信號，其被提供至^^：： 424,如所展 示。頻率至電壓轉換器424接著產生一組輸出信號，其具有 10 成比例於從ROSC 422被接收之輸入信號頻率的電壓。於一 實施例中，R0SC 422和FVC 424—起操作之方式如同電壓/ 溫度放大器和位準移位器428，其放大電路上之電壓/溫度 效應並且置放產生之輸出信號電壓在一位準，其是大致地 在DADC 426能力中間範圍内，下面將更詳細地說明。 15 反應於從FVC 424接收輸出信號，DADC 426接著提供 一組成比例於溫度和電壓之輸出數碼信號，將參考第6圖而 更詳細地說明。於一實施例中，檢測器420之潛伏期是兩個 時脈週期，但可以是不同於其他的實施例。 20 第5圖是一實施例的分解圖，其更詳細展示全面數位气 類比至數位轉換器426。DADC 426包含η組串列地連接反才目 器之鏈路501，於這實施例中之η組鏈路各包含三組反相 器。此處，_列地連接反相器之η組鏈路各可以不同地被稱 為反相器感知器501。 第5圖展示之η組反相器感知器501各組被設計以j^有 14 200424543 如展示之Vthl至Vthn的一組不同切換臨限電壓Vth並且分 別地提供一組對應的輸出信號Voutl至Voutn。臨限電壓經 由仔細選擇之相對p和η電晶體裝置尺寸，如所習知的技術 和下面所展示之方程式，於感知器501的各反相器中被變 5 化。Dref > Dl > D2 > D3 05 In operation, the input signal CK is simultaneously transmitted into the delay channels 322 and 324. Each phase detector 332, 334, and 336 then detects whether the output of the reference delay channel 322 leads or delays the output of the other delay channels 324 and provides a corresponding set of output signals outl, ut2, or ut3, respectively. For example, if Vcc is attenuated until the delay D1 exceeds the limit of Dref, the output # 5 虎 〇utl from the phase detector 10 332 is determined. If Vcc is attenuated so that one or both delays D2 and / or 03 exceed Dref, the corresponding output signals out2 and / or out3 are determined. The output signals outl, out2, and out3 are provided as selection signals to the multiplexing and control circuit 315, which receive signals having frequencies Fi, p2, F3, and F4. 15 The configuration and operation of the circuit 315 may be similar to the multiplexing and control circuit 215 described above, while the circuit 315 of an embodiment further includes a flip-flop (not shown) to remove the phase detector after they are determined. 332, 334, and 336 sample the output signals to capture their value before the clock signal transitions to the low state. Further, in an embodiment, the multiplexer 315 selects an output signal having a frequency Fout according to the above 20 Table 1. It should be understood that although circuit 320 uses three different sets of delays to select between four sets of signal frequencies, in another embodiment, a different number of delays may be used in a similar manner and / or signal frequencies are selected. Referring next to Fig. 4, there is shown a high-level block diagram of a comprehensive digital detector 13 200424543 420 of another embodiment. In one embodiment, the 'detector 420 can be used to provide the detector 120 of Figure 1 to give a set of adaptive frequency clock systems. In another embodiment, the detector 420 may be used, for example, as part of an attenuation history circuit. As shown, the detector 420 includes a ring-shaped Vibration Cry 5 (ROSC) 422, a frequency-to-voltage converter (FVC) 424, and a digital analog-to-digital converter (DADC) 426. At high levels, the ring oscillator 422 generates a set of output signals having frequencies proportional to voltage and temperature, which are provided to ^^ :: 424, as shown. Frequency-to-voltage converter 424 then generates a set of output signals having a voltage that is 10 proportional to the frequency of the input signal received from ROSC 422. In one embodiment, the ROSC 422 and FVC 424 operate together like a voltage / temperature amplifier and a level shifter 428, which amplifies the voltage / temperature effect on the circuit and places the output signal voltage generated at one level. , Which is roughly in the middle of the DADC 426 capability, as explained in more detail below. 15 In response to receiving the output signal from FVC 424, DADC 426 then provides an output digital signal that is proportional to temperature and voltage, which will be described in more detail with reference to FIG. In one embodiment, the latency of the detector 420 is two clock cycles, but may be different from other embodiments. 20 FIG. 5 is an exploded view of an embodiment showing a full-scale digital gas analog-to-digital converter 426 in more detail. The DADC 426 includes n groups of links 501 connected in series to the anti-inverter. In this embodiment, the n groups of links each include three groups of inverters. Here, the n groups of links connected to the inverters in the column can be referred to as inverter inverters 501, respectively. Each of the n groups of inverter perceptron 501 shown in FIG. 5 is designed to have a set of 14 200424543 such as a set of different switching threshold voltages Vth from Vthl to Vthn and provide a corresponding set of output signals Voutl to Voutn. The threshold voltage is changed in each inverter of the sensor 501 through carefully selected relative p and n transistor device sizes, as is known in the art and the equations shown below.
。 μηε W βη =1-. μηε W βη = 1-
tox Ltox L
^ μηε W βρ = ---Γ^ μηε W βρ = --- Γ
tox Ltox L
VDD +VDD +
Vth =-Vth =-
其中μ電子遷移率（如所指示p或者η，ε是分別閘絕緣體之介 10 電係數，tox是氧化物厚度，W是分別的電晶體寬度，L是 分別的電晶體長度，Vth是切換臨限電壓，Vtn是NM0S電 晶體之臨限電壓並且Vtp是PM0S電晶體之臨限電壓。 為了減少或者使反相器感知器501之Vth的任何裝置影 響或者電壓變化影響最小化，一組穩定的電源供應，例如， 15 上述之固定電壓供應，可以被使用於DADC 426。進一步 地，用於各反相器之小心裝置尺寸估量也可以被實施以減 少習知方式的Vth變化。 通常提供DADC 426反相器感知器數目，以及DADC 426所需的切換臨限各取決於所需的精確度以及被監視之 20 信號變化的預期範圍。反相器感知器使用數目愈大，則精 15 200424543 確度愈高。因為Vin利用操作反相器感知器之切換臨限電 壓、增加反相感知器數目而被感應，各被調諧較好的切 換臨限’因此導致較高的解析度和檢測精確度。 第6圖是分解圖，其更詳細展示第4圖之檢測器42〇。如 5所展示，於一實施例中，ROSC 422包含或者具有一組被耦 合至除2電路602的輸出。頻率至電壓轉換器（Fvc)424包含 一組脈波產生為605、一組回授延遲通道61〇、一組p型充電 電晶體615、一組η型放電電晶體620以及一組rc通道，其 包含如第6圖展示地被耦合之電容器625、630和電阻器 10 635。於一實施例中，充電電晶體615具有一端點，其被耦 石以接收固疋電源供應電壓VFIXED，例如從一組類比電源供 應，如上述之其他參考實施例。 操作時，ROSC 422產生一組具有成比例於溫度和供用 於如上所述之ROSC 422的供應電壓之頻率的時脈信號。 15 R〇SC 422疋反應於溫度和電壓而變化，但是因為電壓變化 更快於溫度，ROSC 422主要地反應於電壓改變。這在被控 制的測試環境中尤其是正確的，其中溫度被測試設備所控 制。 時脈信號被除2電路602除以二以在線路64〇上提供一 20 組信號divCLK。當divCLK信號轉移至低位時，充電電晶體 615被引動，導致節點vin被充電。當充電電晶體被引動時 被達成的最後電壓Vin是成比例於I*T/C，其中I是充電電晶 體615電流，T是divCLK信號之時脈週期且C是節點Vin的總 計電容。 16 200424543 當divCLK信號轉移至高位時，充電電晶體不被引動。 Vin值決定上述之DADC 426輸出，其接著使用由脈波產生 |§ 605產生的脈波時脈信號pclk而被取樣以進入鎖定637。鎖 定輸出數碼代表一組電壓及/或溫度值並且可以被使用，例 5如，以調整如第1圖展示之適應式頻率時脈系統的信號頻 率，或者被儲存於衰減歷史暫存器中以指示一組電壓衰減 位準，如下面參考第7圖之說明。 繼續參考第6圖，延遲元件610提供一組pcl]^f號之延 遲版至放電電晶體620。反應於被引動，放電電晶體620將 10節點Vin放電以備用於接著之監視週期中。 熟習本技術者應了解，在節點Vin之電荷是控制充電和 放電之信號頻率之函數。於一實施例中，校正操作被執行 以辨識供電荷Vin從DADC 426導出一組輸出數碼之頻率， 其是大致地在DADC 426輸出能力的中間範圍，如下面更詳 15 細地說明。 於一些實施例中，充電電晶體615是一組可調整充電電 晶體以提供鎖定器之啟始設定。第16圖展示可以被使用於 一實施例中之充電電晶體615的製作範例。於這製作中，電 晶體615強度可利用增加被確定之引動信號eni " enn數目而 2〇 被增加。 上述之校正操作可以被進行，例如，在解除重置传號 之後的一些週期中。於一實施例中，校正過程如下所示· 1)電壓Vcc被感應且結果利用掃瞄出被DADC 426輸出之數 碼而被監視（例如，使用一組配合掃瞄鏈路之測試存取 17 200424543 (TAP)相關之接腳（未展示出））；2)pM〇s裝置615之強度依據 被掃瞄出貧料利用增加或者減少被引動之PMOS電晶體數 目而被凋整，及3) 1和2被重複直至數碼是在中間範圍為止。 於其他的實施例中，雖然一組特定全面數位式類比至 5數位轉換器組態是如上所述，包含具有一些類比電路之類 比至數位轉換器之一組不同型式的類比至數位轉換器可以 替代地被使用。 第7圖是電路700之方塊圖，其可以使用第4_6圖衰減檢 測器以提供衰減歷史。電路700包含一組比較器7〇5和衰減 10歷史暫存器710和715。於一實施例中，衰減歷史暫存器71〇 可以被啟始化至所有為〇並且衰減歷史暫存器715可以被啟 始化至所有為1。 #作中’比較705從DADC 426接收被鎖定之數碼並 且比較它與被儲存於衰減歷史暫存器71〇和715中之值。如 15果數碼是大於被儲存於暫存器710中之值，則暫存器71〇被 更動至新的值。如果數碼是較小於被儲存於暫存器715中之 值，則暫存器715被更動至新的值。以此方式，最高和最低 電壓位準之歷史可被追蹤。應了解，供用於各種實施例之 衰減檢測器的其他應用皆在各種實施例範_之内。 20 第8圖是另一貫施例之衰減檢測器800的方塊圖。衰減 檢測器800可以被使用，例如，作為第只圖電路n〇〇之衰減 監視器。衣減檢測為800的其他應用皆在各種實施例範嘴之 内0 衰減檢測器800包含兩組環式震盪器R〇scl和 18 200424543 ROSC2 ’其中ROSC1(快速的）提供一組比R〇SC2(慢的）較高 的頻率"ί§ 5虎。衣減檢測800同時也包含一組計數哭805和 一組脈波產生器810。 爹看第8、9、10和11圖，操作時，快的環式震盪器R〇sci 5利用第8圖範例中被監視之電源供應Vcc而供應電力。第8 圖之慢的環式震盪器ROSC2可以三種方式之一種被製作： 1)以一低電壓敏感組態，其中閘和Rc(電阻_電容）兩電路被 使用以習知的方式而製作震盪器，2)以不（或者大致地不） 破感組怨，其疋藉由使用第1〇圖展示之固定匯流排時脈， 10或者藉著使用分別固定電源供應源，例如類比電源供應或 者不易感受電壓或者溫度變化之帶間隙（未展示出）而供應 R0SC2電力，或者3)藉著使用一反向敏感組態，如第9圖之 展示並且下面將更詳細地說明。其中慢的環式震盪器 R0SC2被製作之方式是取決於多種因素，其包含電路所需 15 的解析度。 於上述之低電壓-敏感和大致地無電壓敏感組態中，第 8圖之R0SC2可使用閘和rc兩電路以習知的方式被組態。 於反向-敏感組態中，參看第9圖，電路，例如電路9〇〇可以 被使用於一貫施例中以提供R〇SC2。電路9〇〇包含一組環式 2〇震盪器905，其僅僅使用閘電路（亦即無RC電路)被製作以至 於其對於電壓變化之敏感性被反向。電路9〇〇利用從電路 910被接收之電壓VCCR而被供應電力。 電路910包含一組p型偏壓電晶體915，其具有耦合以接 收由偏壓產生器920所提供之偏麼電壓的閘極以及耗合以 19 200424543 於這範例之Vcc接收被監視之電壓之一端點。偏壓產生器 920可以包含一組分壓器，其被耦合以從固定電源供應例如 類比電源供應或者帶間隙而接收一組大致被固定之電壓。 電路910進一步地包含被耦合於電流鏡組態和電阻器r中之 5 引動電晶體925和930、電晶體935和940。 電阻值R被選擇，以至於在標稱情況下之VCCR是較低 於VCC而使得ROSC2頻率較低於ROSC1頻率。該選擇是依 據方程式：VCCR=VCC-I2*R。例如，如果VCC=1.2V且12 被設計為0.5mA，且VCCR之目標是0.9V，則R被設計為600 10 歐姆。因為I2和1可被設計為相等，電晶體935和940可被設 計為有效地相等。偏壓電壓和電晶體915接著可選擇，以至 於於此範例中L等於0.5mA。如果選擇偏壓為VCC/2，則915 被估量大小以至於11是〇.5111八。Where μ electron mobility (as indicated by p or η, ε is the dielectric constant of the gate insulator, tox is the thickness of the oxide, W is the width of the respective transistor, L is the length of the respective transistor, and Vth is the switching threshold. Limiting voltage, Vtn is the threshold voltage of NMOS transistor and Vtp is the threshold voltage of PM0S transistor. In order to reduce or minimize any device influence or voltage change influence of Vth of inverter sensor 501, a set of stable Power supply, for example, the fixed voltage supply described above, can be used for DADC 426. Further, careful device size estimation for each inverter can be implemented to reduce Vth variations in conventional ways. DADC 426 is usually provided The number of inverter perceptrons and the switching threshold required by DADC 426 each depend on the required accuracy and the expected range of the 20 signal changes being monitored. The larger the number of inverter perceptrons used, the finer 15 200424543 accuracy The higher. Because Vin is sensed by operating the switching threshold voltage of the inverter sensor and increasing the number of inverter sensors, each has a better tuning threshold. This results in higher resolution and detection accuracy. Figure 6 is an exploded view showing detector 42 of Figure 4 in more detail. As shown in Figure 5, in one embodiment, ROSC 422 includes or has a set of Coupled to the output of the divide-by-2 circuit 602. The frequency-to-voltage converter (Fvc) 424 contains a set of pulse wave generation 605, a set of feedback delay channels 61, a set of p-type charge transistors 615, and a set of n-type discharges Transistor 620 and a set of rc channels, which include capacitors 625, 630 and resistors 10 635 coupled as shown in Figure 6. In one embodiment, the charging transistor 615 has an endpoint which is coupled to the stone to receive The fixed power supply voltage VFIXED, for example, is supplied from a set of analog power supplies, as in the other reference embodiments described above. In operation, ROSC 422 generates a set of frequencies that are proportional to the temperature and supply voltage for ROSC 422 as described above. 15 R〇SC 422 疋 changes in response to temperature and voltage, but because the voltage changes faster than temperature, ROSC 422 mainly responds to voltage changes. This is especially true in a controlled test environment, The medium temperature is controlled by the test equipment. The clock signal is divided by 2 and the circuit 602 is divided by two to provide a set of 20 signals divCLK on line 64. When the divCLK signal is shifted to the low position, the charging transistor 615 is activated, causing the node vin Is charged. The final voltage Vin reached when the charging transistor is activated is proportional to I * T / C, where I is the current of the charging transistor 615, T is the clock period of the divCLK signal and C is the total of the node Vin Capacitance. 16 200424543 When the divCLK signal is transferred high, the charging transistor is not activated. The Vin value determines the above-mentioned DADC 426 output, which is then sampled to enter lock 637 using the pulse wave clock signal pclk generated by the pulse wave generation | § 605. The locked output number represents a set of voltage and / or temperature values and can be used, for example, 5 to adjust the signal frequency of the adaptive frequency clock system as shown in Figure 1, or stored in the attenuation history register to Indicates a set of voltage attenuation levels, as described below with reference to FIG. 7. Continuing to refer to FIG. 6, the delay element 610 provides a set of delayed versions pcl] ^ f to the discharge transistor 620. In response to being activated, the discharge transistor 620 discharges 10-node Vin for use in subsequent monitoring cycles. Those skilled in the art should understand that the charge at the node Vin is a function of the frequency of the signal controlling charge and discharge. In one embodiment, a calibration operation is performed to identify the frequency of a set of output digits derived from the DADC 426 for the charge Vin, which is approximately in the middle range of the output capability of the DADC 426, as described in more detail below. In some embodiments, the charging transistor 615 is a set of adjustable charging transistors to provide the initial setting of the lock. FIG. 16 shows a manufacturing example of a charging transistor 615 that can be used in an embodiment. In this production, the intensity of the transistor 615 can be increased by increasing the number of determined trigger signals eni " enn and 20. The above-mentioned correction operation may be performed, for example, in some cycles after the reset signal is released. In one embodiment, the calibration process is as follows: 1) The voltage Vcc is sensed and the result is monitored by scanning out the digital output by the DADC 426 (for example, using a set of test accesses with scanning links 17 200424543 (TAP) related pins (not shown)); 2) The strength of the pM0s device 615 is trimmed based on the use of lean materials being scanned to increase or decrease the number of PMOS transistors driven, and 3) 1 And 2 are repeated until the number is in the middle range. In other embodiments, although a specific set of comprehensive digital to analog converters is configured as described above, a set of different types of analog to digital converters including an analog to digital converter with some analog circuits may be Used instead. Figure 7 is a block diagram of circuit 700, which can use the attenuation detector of Figures 4-6 to provide attenuation history. The circuit 700 includes a set of comparators 705 and attenuation 10 history registers 710 and 715. In one embodiment, the decay history register 71o may be initialized to all zeros and the decay history register 715 may be initialized to all ones. # 作 中 ’compare 705 receives the locked number from DADC 426 and compares it with the values stored in the attenuation history registers 71 and 715. If the 15-digit number is greater than the value stored in the register 710, the register 71 is changed to the new value. If the number is smaller than the value stored in the register 715, the register 715 is changed to the new value. In this way, the history of the highest and lowest voltage levels can be tracked. It should be understood that other applications of the attenuation detector for use in the various embodiments are within the scope of the various embodiments. 20 FIG. 8 is a block diagram of an attenuation detector 800 according to another embodiment. The attenuation detector 800 can be used, for example, as an attenuation monitor for the circuit of the first figure. Other applications of the clothing reduction detection 800 are within the scope of various embodiments. 0 The attenuation detector 800 includes two sets of ring oscillators Roscl and 18 200424543 ROSC2 'where ROSC1 (faster) provides a set of ratios more than RoSC2. (Slow) Higher frequency " ί 5 Tigers. The clothing reduction detection 800 also includes a set of counting cries 805 and a set of pulse wave generators 810. Daddy see Figures 8, 9, 10, and 11. In operation, the fast ring oscillator Rosci 5 uses the monitored power supply Vcc in the example in Figure 8 to supply power. The slow ring oscillator ROSC2 in Figure 8 can be made in one of three ways: 1) In a low-voltage sensitive configuration, the two circuits of the gate and Rc (resistance_capacitance) are used to make the oscillator in a conventional manner Device, 2) Do not (or roughly do not) break the sense of grievance, by using the fixed bus clock shown in Figure 10, or by using a fixed power supply, such as analog power supply or Supply ROSC2 power with a gap (not shown) that is not susceptible to voltage or temperature changes, or 3) by using a reverse-sensitive configuration, as shown in Figure 9 and described in more detail below. The way in which the slow ring oscillator R0SC2 is made depends on a number of factors, including the 15 resolution required by the circuit. In the above-mentioned low voltage-sensitive and substantially voltage-free configuration, ROSC2 of FIG. 8 can be configured in a conventional manner using two circuits, a gate and an rc. In a reverse-sensitive configuration, referring to Figure 9, a circuit, such as circuit 900, can be used in conventional embodiments to provide ROSC2. Circuit 900 includes a set of ring-shaped 20 oscillators 905, which are made using only a gate circuit (ie, no RC circuit) so that its sensitivity to voltage changes is reversed. The circuit 900 is supplied with power using the voltage VCCR received from the circuit 910. The circuit 910 includes a set of p-type bias transistors 915, which have a gate coupled to receive the bias voltage provided by the bias generator 920, and a Vcc receiving 19 200424543 in this example receives the monitored voltage. An endpoint. The bias generator 920 may include a set of voltage generators coupled to receive a set of approximately fixed voltages from a fixed power supply such as an analog power supply or a gap. The circuit 910 further includes 5 driving transistors 925 and 930, and transistors 935 and 940 coupled to a current mirror configuration and a resistor r. The resistance value R is selected so that the VCCR is lower than VCC in the nominal case so that the ROSC2 frequency is lower than the ROSC1 frequency. The choice is based on the equation: VCCR = VCC-I2 * R. For example, if VCC = 1.2V and 12 is designed as 0.5mA, and the target of VCCR is 0.9V, then R is designed as 600 10 ohms. Because I2 and 1 can be designed to be equal, transistors 935 and 940 can be designed to be effectively equal. The bias voltage and transistor 915 are then selectable so that in this example L is equal to 0.5 mA. If the bias voltage is selected as VCC / 2, then 915 is estimated so that 11 is 0.5111111.
操作中，如當Vcc值改變時，電晶體915閘極至源極電 15 壓Vgs改變，導致電流h改變。例如，當Vcc增加時，Vgs 增加導致電流h增加。由於電晶體935和94〇之電流鏡組態， 當Ιι增加時’電流I2同時也增加而導致跨越電阻器R之電壓 降增加。一組跨越電阻器r之較大電壓降導致一組至環式震 盈為905的較低VCCR。因為環式震盪器905頻率是成比例於 20電壓VCCR，當VCCR被降低時，來自環式震盪器905之輸 出信號頻率Fout因而也是被降低。vcc減少導致電壓VCCR 之互補反應並且因此，利用來自環式震盪器9〇5之輸出信號 頻率Fout亦然。 因此，如上所述，電路9〇〇提供一反向電壓敏感電路， 20 200424543 其中Vcc之增加導致VCCR之減少，並且因此，來自環式震 盪器905之輸出信號頻率減少。 繼續參考第8和11圖，快的環式震盪器ROSC1提供計數 器805時脈，而慢的環式震盪器ROSC2產生一組脈波同步重 5 置。慢的環式震盪器基本上定義來自快的環式震盛器之時 脈脈波數目被計數時的時間週期。在重置脈波之間被產生 的時脈脈波數目取決於Vcc值，被使用以供應RQSC1電力之 被監視的電壓而變化。 被選擇以供用於慢的環式震盪器r0SC2之特定製作是 10取決於包含監視電路所需的解析度之多種因素。例如，當 需一相對高的解析度時，設計者可以選擇提供反向電壓敏 感性之ROSC2的組態。 Ί續參考第8和11圖’剛好於重置前，成比例於來自快 的環式震盪器ROSC1之輸出信號頻率和來自慢的環式震盪 15 ^R〇SC2(或者固定匯流排時脈）之輸出信號頻率之間關係 的計數器805之輸出，利用鎖定器11〇5被鎖定並且被提供至 比較器1110。比較器1110可以如上述參考第？圖之操作以比 較被鎖定之數碼與先前被儲存於衰減歷史暫存器1115和 1120中之值。 20 於一實施例中，例如，衰減歷史暫存器1115可以被啟 始化至所有為i並且衰減歷史暫存器112〇可以被啟始化至 所有為0如果被鎖定之數碼是較低於被儲存於暫存器ms 中之值及/或較高於賴存於暫存器m时之值，則適當的 暫存杰被更動以儲存新的數碼。以此方式，衰減歷史暫存 21 讀存對應至在所給予的時間週期時之Vcc的最大和最小 值之數碼。 夕。第8和u圖之電路提供用於每一週期之輸 ^多數個此類電路可被交錯(未展示出）以至於—輸出可被 5提供於更快時脈信號之每-週期。 /夕第1—2圖是積體電路12〇〇之高位準方塊圖，於其上一組 或:、且貝苑例之一組或多組衰減檢測器1205可以被製作。 於第12圖展不之實施例，一組衰減檢測器，例如依據第2、 或者4圖其中之一的衰減檢測器被製作接近pa ，以 1〇至於適應式財控制可以如上所述地被提供。 第13圖是一實施例之積體電路1300的高位準方塊圖， ;”上夕數個衰減監視器電路1305，例如依據第7-11圖之 一組或多組衰減監視器電路可以被製作。於第13圖實施例 中，衰減監視器電路1305可以被製作在積體電路13〇〇附近 之各位置，其監視供用於特徵化、除錯及/或其他的目所需 的電壓衰減及/或溫度變化。 於一貫施例中，例如，與一組或多組衰減監視器電路 相關的衰減歷史暫存器被設計以儲存在所給予時間週期的 最大和最小電壓及/或溫度值。於一實施例中，衰減監視器 2〇電路1305以掃瞄鏈路組態被連接。接著，在測試、特徵化 或者除錯操作時，例如，被儲存於衰減歷史暫存器中之值 可以經由掃瞄鏈路被讀取出。其他用於讀取被儲存於衰減 歷史暫存器中之值的方法皆在各種實施例範疇之内。 第14圖是一實施例系統1400之高位準方塊圖，系統 22 200424543 1400包含經由匯流排141〇被耦合至一組或多組輸入/輸出 構件1415之處理器1405、一組或多組大量儲存裝置1425以 及一組或多組其他的系統構件142〇。於一實施例中，處理 器1405依據一組或多組實施例而包含一組或多組衰減檢測 5 為及/或衣減監視^§ 1430。於一些實施例中，'一組或多组衰 減檢測器可以被包含在系統14〇〇内之不同的積體電路上。 第15圖是一組高位準流程圖，其展示用於提供時脈信 號之一實施例的方法。在方塊1505，晶粒上檢測器檢測一 溫度和電壓位準並且在方塊1510提供相關於被檢測溫度的 10 數碼信號作為一組輸出。在方塊1515，控制電路反應於數 碼信號而決定時脈信號頻率。 應了解，於其他的實施例中，另外的動作可以被包含。 因此’於咼頻率時脈系統中數位地檢測電壓和溫度變 化之方法及裝置被說明。於上述說明中，本發明已利用參 15 考其特定實施範例被說明。應了解，本發明可有各種修改 和改變而不脫離本發明所附加之申請專利範圍的精神和範 疇。因此說明和圖形被認為只供展示而不是用於限制。 【圖式簡單說明3 第1圖是一實施例之適應式頻率時脈系統的高位準方 2〇 塊圖。 第2圖是可以被使用於第1圖之適應式頻率時脈系統中 的實施例之哀減（電壓）檢測器分解圖和方塊圖。 第3圖是可以被使用於第1圖之適應式頻率時脈系統中 的另一實施例之電壓檢測器分解圖和方塊圖。 23 200424543 第4圖是可以被被使用於第1圖之適應式頻率時脈產生 電路中的一實施例之衰減/電壓檢測器方塊圖。 第5圖是可以被使用於第4圖之衰減/電壓檢測器中的 實施例之數位類比至數位轉換器分解圖。 5 第6圖是更詳細地展示第4圖之衰減/電壓檢測器的分 解圖。 第7圖是展示第6圖衰減檢測器用以追蹤衰減歷史之另 一應用的方塊圖。 第8圖是可以被使用於，例如，衰減監視的另一實施例 10 之衰減檢測器分解圖和方塊圖。 第9圖是可以被使用以控制第8圖衰減檢測器中之環式 震盪器之反向電壓感應電路分解圖和方塊圖。 第10圖是可以被使用於，例如衰減監視之另一實施例 之衰減檢測器分解圖和方塊圖。 15 第11圖是可以被使用於一實施例中以追蹤衰減歷史之 電路製作方塊圖。 第12圖是使用一實施例之衰減及/或溫度檢測器的一 實施例之積體電路的高位準方塊圖。 第13圖是使用一實施例之一組或多組衰減監視電路的 20 一實施例之積體電路的高位準方塊圖。 第14圖是使用一實施例之衰減及/或溫度檢測器的一 實施例之系統方塊圖。 第15圖是一流程圖，其展示用以檢測晶粒上電壓衰減 及/或溫度變化之一實施例的方法。 24 200424543 第16圖疋可以有利地被使用於第6圖之實施例中之充 電電晶體製作範例之分解圖。 【圖式之主要元件代表符號表】 100…適應式頻率時脈產生電路 105…同步時脈產生器(相位鎖 定迴路(ΡΙΧΧ) 110···除Ν電路 115···多工器 120…電壓衰減(及/或溫度)檢 測器 125…頻率數碼 130···輸出時脈 215…控制與多工電路 221…分壓器 222…引動裝置 224…比較器 226···比較器 228…比較器 230…類比電源供應 315···多工器 320…電壓衰減檢測器 322…延遲元件 324…延遲元件 330···固定電_應 332···相位檢測器 334···相位檢測器 336···相位檢測器 420···檢測器 422·.·環式震盪器(ROSC) 424…頻率至電壓轉換器(FVC) 426…數位類比至數位轉換器 (DADC) 428…電壓/溫度放大器和位準 移位器 501···反相器感知器 602…除2電路 605…脈波產生器 610…延遲元件 615···ρ型充電電晶體 620···η型放電電晶體 625…電容器 630···電容器 635···電容器 640…線路 700…電路 25 200424543 705···比較器 1115…衰減歷史暫存器 710…衰減歷史暫存器 1120…衰減歷史暫存器 715…衰減歷史暫存器 1200…積體電路 800···衰減檢測器 1205…衰減檢測器 805…計數器 1210…PLL電路 810…脈波產生器 1300…積體電路 900…電路 1305…衰減監視器電路 905···環式震盪器 1400···系統 910···電路 1405···處理器 915…閘極 1410…匯流排 920…偏壓產生器 1415…輸入輸出裝置 925…電晶體 1420···系統構件 930···電晶體 1425…儲存裝置 935···電晶體 1430…衰減檢測器及/或衰減 940…電晶體 監視器 1100···比較器 1505-1515…時脈信號高位準 1105…鎖定器 流程圖步驟 1110···比較器 26In operation, for example, when the value of Vcc is changed, the voltage Vgs of the gate-source voltage of the transistor 915 is changed, which causes the current h to be changed. For example, when Vcc increases, the increase in Vgs causes the current h to increase. Due to the current mirror configuration of transistors 935 and 94, the current I2 also increases as Im increases, resulting in an increase in the voltage drop across resistor R. A larger set of voltage drops across resistor r results in a lower set of VCCRs with a ring-shaped shock of 905. Because the frequency of the ring oscillator 905 is proportional to the 20-voltage VCCR, when the VCCR is lowered, the frequency Fout of the output signal from the ring oscillator 905 is also reduced. The reduction in vcc results in a complementary reaction of the voltage VCCR and therefore, the output signal frequency Fout from the ring oscillator 905 is also used. Therefore, as mentioned above, the circuit 900 provides a reverse voltage sensitive circuit, 20 200424543, where an increase in Vcc causes a decrease in VCCR, and therefore, the frequency of the output signal from the ring oscillator 905 decreases. Continuing to refer to Figures 8 and 11, the fast ring oscillator ROSC1 provides the counter 805 clock, while the slow ring oscillator ROSC2 generates a set of pulse resets. A slow ring oscillator basically defines the time period when the number of pulse waves from the fast ring oscillator is counted. The number of clock pulses generated between reset pulses depends on the value of Vcc, and the monitored voltage used to supply RQSC1 power varies. The particular fabrication chosen for the slow ring oscillator r0SC2 is 10 depending on a number of factors including the resolution required by the monitoring circuit. For example, when a relatively high resolution is required, the designer can choose a configuration of ROSC2 that provides reverse voltage sensitivity. Continued to refer to Figures 8 and 11 'Just before reset, proportional to the frequency of the output signal from the fast ring oscillator ROSC1 and from the slow ring oscillator 15 ^ R〇SC2 (or fixed bus clock) The output of the counter 805 which is related to the frequency of the output signal is locked by the lock 1105 and provided to the comparator 1110. Comparator 1110 can be referenced as above? The operation of the map is to compare the locked number with the value previously stored in the attenuation history registers 1115 and 1120. 20 In an embodiment, for example, the attenuation history register 1115 may be initialized to all i and the attenuation history register 112 may be initialized to all 0 if the locked number is lower than The value stored in the register ms and / or higher than the value stored in the register m, then the appropriate register is modified to store the new number. In this way, the attenuation history is temporarily stored. 21 The numbers corresponding to the maximum and minimum values of Vcc at the given time period are stored. Xi. The circuits in Figures 8 and u provide inputs for each cycle. ^ Most of these circuits can be interleaved (not shown) so that the output can be provided by 5 for each cycle of the faster clock signal. Figures 1 and 2 are high-level block diagrams of the integrated circuit 1200. On the previous set or :, and one or more sets of attenuation detectors 1205 can be made. In the embodiment shown in Fig. 12, a set of attenuation detectors, for example, according to one of Figs. 2 or 4 is made close to pa, and the adaptive financial control can be adjusted as described above. provide. FIG. 13 is a high-level block diagram of the integrated circuit 1300 of an embodiment; “Several attenuation monitor circuits 1305 on the eve, for example, one or more groups of attenuation monitor circuits according to FIGS. 7-11 can be made. In the embodiment of FIG. 13, the attenuation monitor circuit 1305 can be made at various positions near the integrated circuit 1300, which monitors the voltage attenuation and required for characterization, debugging, and / or other purposes. / Or temperature change. In conventional embodiments, for example, an attenuation history register associated with one or more sets of attenuation monitor circuits is designed to store the maximum and minimum voltage and / or temperature values for a given time period. In one embodiment, the attenuation monitor 20 circuit 1305 is connected in a scan link configuration. Then, during a test, characterization, or debugging operation, for example, the value stored in the attenuation history register may be It is read out via the scanning link. Other methods for reading the values stored in the attenuation history register are within the scope of various embodiments. FIG. 14 is a high-level block of the system 1400 of an embodiment Figure, System 22 2004245 43 1400 includes a processor 1405 coupled to one or more sets of input / output components 1415, one or more sets of mass storage devices 1425, and one or more sets of other system components 1420 via a bus 1410. In one In an embodiment, the processor 1405 includes one or more sets of attenuation detection according to one or more sets of embodiments 5 and / or clothing monitoring ^ § 1430. In some embodiments, 'one or more sets of attenuation detection The device can be included on different integrated circuits within the system 1400. Figure 15 is a set of high level flowcharts showing one embodiment of a method for providing a clock signal. At block 1505, the die The upper detector detects a temperature and voltage level and provides 10 digital signals related to the detected temperature as a set of outputs at block 1510. At block 1515, the control circuit determines the clock signal frequency in response to the digital signals. It should be understood that In other embodiments, additional actions may be included. Therefore, a method and apparatus for digitally detecting voltage and temperature changes in a chirped frequency clock system are described. In the above description, the present invention has been beneficial Reference is made to a specific implementation example with reference to it. It should be understood that the present invention may be modified and changed without departing from the spirit and scope of the scope of the patent application attached to the present invention. Therefore, the descriptions and figures are to be considered for display only and not for Restrictions. [Schematic description 3 Figure 1 is a high-level square block diagram of an adaptive frequency clock system of an embodiment. Figure 2 is a diagram that can be used in the adaptive frequency clock system of Figure 1. Exploded view and block diagram of the reduced (voltage) detector of the embodiment. Figure 3 is an exploded view and block diagram of the voltage detector of another embodiment that can be used in the adaptive frequency clock system of Figure 1. 23 200424543 Figure 4 is a block diagram of an attenuation / voltage detector according to an embodiment that can be used in the adaptive frequency clock generation circuit of Figure 1. Figure 5 is an exploded view of a digital analog-to-digital converter of the embodiment that can be used in the attenuation / voltage detector of Figure 4. 5 Figure 6 is an exploded view showing the attenuation / voltage detector of Figure 4 in more detail. Figure 7 is a block diagram showing another application of the attenuation detector of Figure 6 to track attenuation history. Fig. 8 is an exploded view and a block diagram of an attenuation detector which can be used, for example, in another embodiment 10 of attenuation monitoring. Figure 9 is an exploded and block diagram of the reverse voltage sensing circuit that can be used to control the ring oscillator in the attenuation detector of Figure 8. Fig. 10 is an exploded view and a block diagram of an attenuation detector which can be used in, for example, another embodiment of the attenuation monitoring. 15 Figure 11 is a block diagram of a circuit that can be used in an embodiment to track the attenuation history. Fig. 12 is a high-level block diagram of an integrated circuit of an embodiment using an attenuation and / or temperature detector of an embodiment. FIG. 13 is a high-level block diagram of the integrated circuit of one embodiment using one or more sets of attenuation monitoring circuits according to one embodiment. Fig. 14 is a system block diagram of an embodiment using an embodiment of the attenuation and / or temperature detector. Fig. 15 is a flowchart showing a method for detecting one embodiment of voltage decay and / or temperature change on a die. 24 200424543 FIG. 16 is an exploded view of a manufacturing example of a charging transistor which can be advantageously used in the embodiment of FIG. 6. [Representative symbol table of main components of the figure] 100 ... Adaptive frequency clock generation circuit 105 ... Synchronous clock generator (Phase Locked Loop (PIXX) 110 ··· In addition to N circuit 115 ··· Multiplexer 120… Voltage Attenuation (and / or temperature) detector 125 ... frequency digital 130 ... output clock 215 ... control and multiplexing circuit 221 ... voltage divider 222 ... actuating device 224 ... comparator 226 ... comparator 228 ... comparator 230 ... analog power supply 315 ... multiplexer 320 ... voltage decay detector 322 ... delay element 324 ... delay element 330 ... fixed power_should 332 ... phase detector 334 ... phase detector 336 ... · Phase Detector 420 · · Detector 422 · · · Ring Oscillator (ROSC) 424 ... Frequency to Voltage Converter (FVC) 426 ... Digital Analog to Digital Converter (DADC) 428 ... Voltage / Temperature Amplifier and Level shifter 501 ... Inverter sensor 602 ... Division 2 circuit 605 ... Pulse wave generator 610 ... Delay element 615 ... P-type charge transistor 620 ... N-type discharge transistor 625 ... Capacitor 630 ... capacitor 635 ... capacitor 640 ... line 700 ... circuit 25 200424 543 705 ··· Comparer 1115 ... Falling history register 710 ... Falling history register 1120 ... Falling history register 715 ... Falling history register 1200 ... Integrated circuit 800 ... Fade detector 1205 ... Fade Detector 805 ... Counter 1210 ... PLL circuit 810 ... Pulse wave generator 1300 ... Integrated circuit 900 ... Circuit 1305 ... Attenuation monitor circuit 905 ... Ring oscillator 1400 ... System 910 ... Circuit 1405 ... Processor 915 ... gate 1410 ... bus 920 ... bias generator 1415 ... input / output device 925 ... transistor 1420 ... system component 930 ... transistor 1425 ... storage device 935 ... transistor 1430 ... Attenuation detector and / or attenuation 940 ... Transistor monitor 1100 ... Comparator 1505-1515 ... Clock signal high level 1105 ... Locker flowchart step 1110 ... Comparator 26
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- 2004-02-06 WO PCT/US2004/003386 patent/WO2004095240A2/en active Application Filing
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| CN104136928A (en) * | 2012-02-21 | 2014-11-05 | 高通股份有限公司 | A circuit for detecting a voltage change using a time-to-digital converter |
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| CN103995169A (en) * | 2014-04-25 | 2014-08-20 | 嘉兴泰鼎光电集成电路有限公司 | Test circuit for testing voltages of internal nodes of chips |
| CN103995169B (en) * | 2014-04-25 | 2016-07-20 | 嘉兴泰鼎光电集成电路有限公司 | The test circuit of inter-chip traces voltage |
| CN109477861A (en) * | 2016-03-14 | 2019-03-15 | 安培计算有限责任公司 | Self-reference on piece voltage declines detector |
| CN109477861B (en) * | 2016-03-14 | 2022-03-25 | 安培计算有限责任公司 | Self-reference on-chip voltage droop detector |
| TWI723182B (en) * | 2016-09-09 | 2021-04-01 | 南韓商三星電子股份有限公司 | Apparatus, method of calibrating, method of manufacturing apparatus, and method of constructing an integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2004095240A3 (en) | 2005-06-02 |
| EP1631890A2 (en) | 2006-03-08 |
| US7133751B2 (en) | 2006-11-07 |
| US20040183613A1 (en) | 2004-09-23 |
| WO2004095240A2 (en) | 2004-11-04 |
| US20050184764A1 (en) | 2005-08-25 |
| TWI247124B (en) | 2006-01-11 |
| US6882238B2 (en) | 2005-04-19 |
| KR100819954B1 (en) | 2008-04-07 |
| KR20050112109A (en) | 2005-11-29 |
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