JP3043716B2 - Semiconductor device test result determination circuit and test result determination method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a test circuit and a test method for a semiconductor integrated circuit. More specifically, a semiconductor device characterized in that a test result output signal output from each functional block constituting a semiconductor integrated circuit is input to a comparison circuit, and the presence or absence of a failure in the functional block is determined based on a current value of the comparison circuit. The present invention relates to a test circuit and a test method for an integrated circuit.

[0002]

2. Description of the Related Art Test apparatuses for semiconductor integrated circuits have been developed with higher integration and higher speed of semiconductor integrated circuits. At present, various dedicated test equipment and general-purpose test equipment (LSI testers) can be used for VLSI, depending on the purpose of use, such as R & D, production line, acceptance inspection, and reliability evaluation. ing. A comparison circuit applied to this type of test apparatus is particularly configured for a semiconductor integrated circuit having a failure detection function using the comparison circuit. In this conventional device, the means for comparing the signals usually takes an exclusive OR, but in order to confirm the comparison result, the logical value of the output signal is monitored to determine the result. Had gone.

[0003]

The operation of the above-mentioned semiconductor integrated circuit using an LSI tester is generally confirmed by monitoring the output terminal of the semiconductor integrated circuit.
The self-test function (Build In
When a plurality of memories having a Self Test (hereinafter, BIST) are mounted, the outputs of the BIST circuits are output to the output terminals of the semiconductor integrated circuit by the number of the memories. However, in recent years, as the density of semiconductor integrated circuits has increased, the number of memories to be mounted has also increased, and the number of input / output terminals has been required due to the higher functionality of semiconductor integrated circuits. Have been. On the other hand, when configuring a wired output to reduce the number of terminals, turning on all transistor switches and shorting the outputs is prohibited because excessive current may flow and damage the chip. ing.

In order to address these problems, for example,
As disclosed in Japanese Patent Application Laid-Open No. Hei 4-10040, a plurality of memory modules are connected to NAND
It has been proposed to share a test output with a normal I / O port in a configuration having a gate and an OR gate and a transistor switch for switching an I / O port. The technique disclosed in this prior art document has a problem in that since a plurality of memory modules are bundled by logic gates, as the number of memory modules increases, more logic gates are required.

Further, as disclosed in Japanese Patent Application Laid-Open No. Hei 9-197012, a memory macro has a holding circuit for holding the state when there is an expected value mismatch as a result of a memory macro test. There has been proposed a configuration having a circuit connected to a user logic circuit and forcibly stopping the operation of the user logic circuit. This configuration does not have a dedicated test output terminal in order to hold the mismatched state as a result of the memory test and to stop the user logic circuit at that logic level. As in Japanese Unexamined Patent Publication No. Hei 4-10040, there is a problem that a logic gate is required and the number of elements increases.

Although the present invention employs the above-described prohibited configuration, that is, a wired connection configuration, even if the chip is destroyed by turning on all the transistor switches and short-circuiting the outputs, the current can be reduced. As described in the following “Embodiment of the invention”, it is assumed that there is no problem because the chip is already defective, and all transistor switches are turned on to determine the test result. The main object of the present invention is to make a transistor switch have a wired OR function to perform fault detection, thus eliminating the need to provide an output terminal of a test circuit in a semiconductor integrated circuit and reducing the number of elements compared to the number of comparison circuits. An object of the present invention is to provide a comparison circuit which does not greatly increase.

[0007]

According to the present invention, one terminal is connected to each of a plurality of input signal lines.
Connected, and the other terminal is wired
A plurality of transistor switches and the plurality of transistors.
When the transistor switch is turned on at the same time,
The through current flowing between the transistors of
Determine whether multiple input signal lines are high level or low level
It is characterized by that. The invention described in claim 2 is a half
Output of test circuits for functional blocks that constitute conductor integrated circuits
Force signal to a comparison circuit composed of transistor switches
Input and the value of the current flowing through the comparison circuit
In the determination circuit for determining the presence or absence of a failure,
Lock test circuit test result output signal input
Number of input signal parts and one terminal is
Connected to each other, and the other terminal is wired
A plurality of connected transistor switches, and
Simultaneous on / off control of multiple transistor switches
And an enable signal section for issuing a signal for performing
A comparison circuit, and the enable signal
When a plurality of transistors are turned on,
The plurality based on whether the force signal line is high level or low level
The through current value between the transistor switches
Detects whether a functional block has failed
Test result determination circuit for semiconductor device. Claim 3
Akira said that one memory mounted on a semiconductor integrated circuit
Output and has a self-test function connected to the memory
The output of the BIST section is composed of a transistor switch.
Input to the comparison circuit, and the current value flowing through the comparison circuit
A test circuit for determining the presence or absence of a memory failure
Connected to the memory where the presence or absence of
BIST unit for outputting an expected value signal to the comparison circuit
And the output signal of the memory and the output signal of the BIST unit
A comparison circuit for inputting and determining whether or not the memory has a failure;
A clock that generates a clock signal for starting the above determination test
Block and a plurality of transistor switches of the comparison circuit.
Signal that enables on / off control of the switches simultaneously.
And an enable signal section for
You. The invention according to claim 4 is mounted on a semiconductor integrated circuit.
Of the BIST unit connected to the plurality of memories
Compare output with multiple transistor switches
Input to the circuit and store the current value in the memory
In the judgment circuit that judges the presence or absence of
Of multiple memories for which the presence or absence of a failure is determined
Output the expected value signal to the comparison circuit
A BIST section and an output signal of the BIST section are input and
A comparing circuit for determining whether or not the memory has a failure;
A clock signal for generating a clock signal for starting a test
Section and a plurality of transistor switches of the comparison circuit.
To generate an enable signal for on / off control
Cable signal section. Claim
Item 5 is mounted on a semiconductor integrated circuit.
An output signal from the specific function macro, and the specific function macro
From the memory that stores the expected output value for the function test
Comparison of the output signal with the transistor switch
Input to the circuit and the current value flowing through the comparison circuit
In the judgment circuit that judges the presence or absence of
A specific function macro that determines whether there is a failure
Memory that stores expected output values for functional test
And the output signal of the specific function macro and the expected output value
And the output signal of the memory storing the
Circuit that determines the presence or absence of a failure based on the presence or absence of through current
And the plurality of transistor switches of the comparison circuit
To generate an enable signal for on / off control
Cable signal section. Claim 7
Akira describes the test of each functional block that constitutes a semiconductor integrated circuit.
Input signal to one terminal and the other terminal
Multiple transistors connected by wires between terminals
The above function having a comparison circuit composed of a star switch
In the determination method by the block failure determination circuit,
Set the enable signal of the
Simultaneously turning on the transistor switches;
Test on the transistor switches that make up the above comparison circuit
Inputting the output signal of the circuit;
Flows through the comparison circuit based on the level or low level
The through current value is used to determine whether there is a failure in the functional block.
And a process of

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, a comparison circuit provided in a judgment circuit according to a first embodiment will be described below. This comparison circuit is provided in a determination circuit that determines whether a functional block constituting a semiconductor integrated circuit has a failure. This comparison circuit includes transistor switches 5 and 6 having one terminal connected to each other, and
And the input signals 3 and 4 input to the other terminals of the transistor switches 5 and 6, respectively. The comparison circuit 1 has an input signal 3,
4 is wired-connected via the transistor switches 5 and 6. When comparing the input signals 3 and 4, the transistor switches 5 and 6 are turned on by activating the enable signal 2.
In this state, when the input signal 3 and the input signal 4 have the same potential,
There is no current path. However, in the case of different potentials, for example, when the input signal 3 is “1” and the input signal 4 is “0”, the current flows through the path of the input signal 3 → the transistor switch 5 → the transistor switch 6 → the input signal 4. Flows. When the input signal 3 is “0” and the input signal 4 is “1”, the current flows through the path of the input signal 4 → the transistor switch 6 → the transistor switch 5 → the input signal 3. Thus, the operation of determining the comparison result based on the amount of current flowing through the transistor switch is performed.

Next, the operation of the comparison circuit 1 of this embodiment will be described with reference to the truth table of FIG. First, when the enable signal 2 is in an active state, the comparison circuit starts operation. The active state here depends on the transistors constituting the transistor switches 5 and 6. For example, when the transistor switches 5 and 6 are N-MO
In the case of the S transistor, the enable signal is active at a high level. When the transistor switches 5 and 6 are P
-In the case of MOS, it becomes active at low level. When both the input signals 3 and 4 are at the low level, the wired terminals of the transistor switches 5 and 6 have the same potential and no current flows. Similarly, when the input signals 3 and 4 are both at the high level, the wired terminals of the transistor switches 5 and 6 have the same potential and no current flows. Next, when the input signal 3 is at a high level and the input signal 4 is at a low level, the transistor switches 5, 6
The high level and the low level of the wired-connected terminal are short-circuited. During this time, the through current Idd is connected between VDD and GND.
Flows. Also, when the input signal 3 is at the low level and the input signal 4 is at the high level, the high level and the low level of the wired terminals of the transistor switches 5 and 6 are short-circuited, and a through current Idd flows between VDD and GND during this time.

Further, a second embodiment of the present invention will be described with reference to FIGS. Referring to FIG.
A comparison circuit to which a memory having an IST is connected is shown. In the present embodiment, one memory 14 mounted on the semiconductor integrated circuit 11 and the BIST 1 connected to the memory 14 are connected.
5, a clock signal 12 and an enable signal 13 as input signals of the BIST 15, an output signal 18 of an expected value generation unit of the BIST 15, an output 17 of the memory 14, and a comparison circuit 16 which receives the enable signal 13 as inputs. Having. The comparison circuit 16 is provided with the BIST 15
In this configuration, the output signal 18 of the expected value generator and the output 17 of the memory 14 are wired-connected via a transistor switch. When the enable signal 13 is activated, the transistor switch is turned on. When the clock signal 12 is input, a test of the memory 14 is started, and an expected value is generated by the BIST 15.

Here, as shown in FIG.
If there is no failure, the output signals 18 of the expected value generation unit of the BIST 15 all have the same potential at the same timing. Therefore, even if the transistor switch of the comparison circuit 16 is wired-connected, no through current flows, and Charge and discharge only. However, if there is a failure in the memory 14, a potential different from the output signal 18 of the expected value generation unit of the BIST 15 is output, so that a through current flows through the transistor switch of the comparison circuit 16. As described above, when there is a failure in the memory having the BIST, the comparison circuit in the semiconductor integrated circuit flows a large amount of current. By monitoring this current value, a failure is detected.

Next, a third embodiment of the present invention will be described with reference to FIGS. 5, 6, and 7. FIG. Referring to FIG.
In this embodiment, a comparison circuit in which outputs of a plurality of BISTs are connected in a semiconductor integrated circuit equipped with a memory having a plurality of BISTs is shown. In the present embodiment, four memories 24a to 24d mounted on the semiconductor integrated circuit 21 are used.
And BIST2 connected to the memories 24a to 24d.
5a to 25d, and a clock signal 22 and an enable signal 23 which are input signals of the BISTs 25a to 25d.
And a comparison circuit 26 to which the output signals of the BISTs 25a to 25d and the enable signal 23 are input.
The comparison circuit 26 has a configuration in which the output signals of the BISTs 25a to 25d are wired-connected via transistor switches. When the enable signal 23 becomes active, the transistor switches are turned on. When the clock signal 22 is input, a test of the memories 24a to 24d is started, and the BIST2
Test results are output by 5a to 52d. here,
When there is no failure in the memories 24a to 24d, the BIS
Since the outputs of T25a to 25d all have the same potential at the same timing, a through current does not flow even if the transistor switches of the test circuit 26 are wired. However, if any of the memories 24a to 24d has a failure, the BISTs 25a to 25d output different potentials, and a through current flows through the transistor switch of the comparison circuit 26. As described above, when a certain part of the plurality of memories has a failure, a large amount of current flows to the comparison circuit in the semiconductor integrated circuit. Therefore, the operation of monitoring the current value to detect the failure is performed.

Referring to FIG. 6, the comparison circuit 26 of FIG. 5 is configured as follows. That is, the comparison circuit 26 has transistor switches 26a to 26d having the enable signal 23 as a gate input. The output signals of the BISTs 25a to 25d are input to one input, and the other is wired. When the enable signal 23 becomes active, the transistor switches 26a to 26d are turned on. That is,
When the clock signal 22 is input, the memory 24a
To 24d are started, and the BIST 25a to
25d outputs a test result. Here, as shown in FIG. 7, when there is no failure in the memories 24a to 24d, the outputs of the BISTs 25a to 25d all have the same potential at the same timing.
Even if the transistor switch is wired-connected, no through current flows and only charging and discharging of the transistor is performed. However, if any of the memories 24a to 24d has a failure, the BISTs 25a to 25d output different potentials, so that a through current flows through the transistor switch portion of the test circuit 26. As described above, when a certain portion of the plurality of memories has a failure, a large amount of current flows through the semiconductor integrated circuit. When a failure occurs in the memory having the self-test function as described above, a large amount of current flows in the comparison circuit in the semiconductor integrated circuit. An operation of detecting a failure is performed by monitoring the current value.

Referring to FIG. 8, there is shown, as a fourth embodiment of the present invention, a comparison circuit in which a specific function macro and a memory storing an expected output value at the time of the function test are connected. In the present embodiment, a specific function macro 34 mounted on the semiconductor integrated circuit 31, a memory 35 storing an expected output value of the specific function macro 34 during a function test, an output signal 38 of the memory 35, A comparison circuit 36 to which the output 37 of the function macro 34 and the enable signal 33 are input
Having. The comparison circuit 36 has a configuration in which an output signal 38 of the memory 35 and an output 37 of the specific function macro 34 are wired-connected via a transistor switch. When the enable signal 33 becomes active, the transistor switch is turned on. State. Activating the specific function macro 34 and outputting the result to the memory 3
Then, the failure detection is performed by comparing the output with the output of FIG. Here, when there is no failure in the specific function macro 34, the output signals 38 of the memory 35 all have the same potential, so that no through current flows even if the transistor switch of the comparison circuit 36 is wired-connected. However, if there is a failure in the specific function macro 34, the potential becomes different from the output signal 38 of the memory 35, so that a through current flows through the transistor switch of the comparison circuit 36. As described above, when there is a failure in the specific function macro, the comparison circuit in the semiconductor integrated circuit flows a large amount of current. An operation of detecting a failure is performed by monitoring the current value.

[0015]

As described above, since the transistor switch is provided with the function of the wired OR to detect the value of the flowing current, it is not necessary to provide the output terminal of the test circuit in the semiconductor integrated circuit. Further, in the embodiment, the MO
Since the input signal is received by one S transistor, the number of elements does not increase significantly. Conventionally, at the time of testing with an LSI tester, a test pattern to be compared with the output of the semiconductor integrated circuit has been required. However, the present invention does not require the test pattern, and a good product can be determined only by measuring the current value of the test execution time. It is possible.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a comparison circuit used for determining a test result of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a truth table for explaining the operation of the comparison circuit of FIG. 1;

FIG. 3 shows a self-test function (BI) according to a second embodiment.
FIG. 3 is a circuit diagram for determining whether a memory having a failure (ST) has a failure.

FIG. 4 is a time chart for explaining the operation of the determination circuit of FIG. 3;

FIG. 5 is a circuit diagram for judging the presence or absence of a failure in a plurality of memories as a third embodiment of the present invention;

6 is a configuration diagram of a comparison circuit in the determination circuit of FIG.

FIG. 7 is a time chart for explaining the operation of the determination circuit of FIG. 5;

FIG. 8 is a circuit diagram for judging the presence or absence of a failure of a specific function macro in a fourth embodiment.

[Explanation of symbols]

1: comparison circuit 2: enable signal 3:
Input signal 4 ... Input signal 5 ... Transistor switch 6 ...
Transistor switch 11 Semiconductor integrated circuit 12 Clock signal 13 Enable signal 14 RAM 15 BIST 16 Comparison circuit 17 RAM output 18 BIS
T expected value output 21 ... Semiconductor integrated circuit 22 ... Clock signal 23 ... Enable signal 24a, 24b, 2
4c, 24d: memory 25a, 25b, 25c, 25d: BIST 26
... Comparator circuits 26a, 26b, 26c, 26d ... Transistor switches 27a, 27b, 27c, 27d ... BIST output 31 ... Semiconductor integrated circuit 33 ... Enable signal 34 ... Specific function macro 35 ... Memory 36 ... Comparator circuit 37 ... Specific function macro output 38… Memory output

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-52899 (JP, A) JP-A-5-180909 (JP, A) JP-A-5-87890 (JP, A) JP-A-10-108 115672 (JP, A) JP-A-9-326473 (JP, A) JP-A-9-166644 (JP, A) JP-A-8-50164 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G01R 31/28-31/3193

Claims (6)

(57) [Claims] A terminal is connected to each of a plurality of input signal lines.
The other terminal is wired
A plurality of transistor switches connected to each other;
When several transistor switches are turned on at the same time,
Depending on the value of the through current flowing between the plurality of transistors,
Whether the plurality of input signal lines are at a high level or a low level.
And a test result determination circuit for a semiconductor device. 2. An output signal of a test circuit of a functional block forming a semiconductor integrated circuit is input to a comparison circuit formed by a transistor switch, and the presence or absence of a failure in the function block is determined based on a current value flowing through the comparison circuit. In the determination circuit, a plurality of input signal units for inputting a test result output signal of the test circuit of the functional block, one terminal is connected to each of the plurality of input signal lines,
The other terminal includes a comparison circuit including: a plurality of transistor switches that are wired and connected to each other; and an enable signal unit that issues a signal for simultaneously performing on / off control of the plurality of transistor switches . The plurality of transistors are enabled by the enable signal.
When turned on, check whether the above input signal lines are high level.
The plurality of transistor switches based on low level.
Depending on the value of the through current between switches,
A test result determination circuit for a semiconductor device, characterized by detecting absence . 3. An output of one memory mounted on the semiconductor integrated circuit and an output of a BIST unit connected to the memory and having a self-test function are input to a comparison circuit composed of a transistor switch; A determination circuit for determining the presence / absence of a failure in the memory based on a current value flowing through the comparison circuit;
A comparison circuit that receives an output signal of the memory and an output signal of the BIST unit and determines whether there is a failure in the memory; a clock signal unit that generates a clock signal for starting the determination test; 3. The test result determination circuit for a semiconductor device according to claim 2 , further comprising: an enable signal unit for issuing an enable signal for performing on / off control of a plurality of transistor switches of the circuit at the same time . 4. An output of a BIST unit connected to a plurality of memories mounted on the semiconductor integrated circuit is inputted to a comparison circuit composed of a plurality of transistor switches.
A determination circuit that determines the presence or absence of a failure in the memory based on a current value flowing through the comparison circuit; a BIST unit for outputting a determining comparator circuit whether a fault of the memory by inputting the output signal of the BIST unit, a clock signal unit to emit a clock signal for the determination test start, a plurality of the comparison circuit 3. The test result determination circuit for a semiconductor device according to claim 2 , further comprising: an enable signal unit that issues an enable signal for simultaneously turning on and off the transistor switches. 5. An output signal from a specific function macro mounted on a semiconductor integrated circuit and an output signal from a memory storing an expected output value for a function test of the specific function macro are configured by transistor switches. A determination circuit for determining whether or not a failure has occurred in the specific function macro based on a current value flowing through the comparison circuit. A memory that stores an expected output value, an output signal of the specific function macro, and an output signal of a memory that stores the expected output value, and determines whether there is a failure in the memory based on the presence or absence of a through current. And an enable signal unit for issuing an enable signal for performing on / off control of a plurality of transistor switches of the comparison circuit at the same time. 5. The test result judging circuit for a semiconductor device according to claim 2, further comprising: 6. A comparison circuit comprising an output signal of a test circuit of each functional block constituting a semiconductor integrated circuit, which is inputted to one terminal and the other terminal is constituted by a plurality of transistor switches which are connected by terminals. In the method for determining whether or not a failure has occurred in the functional block including a circuit, a step of setting an enable signal of the determination circuit to an active state and simultaneously turning on the transistor switches; A step of inputting an output signal of the test circuit, and a step of determining whether there is a failure in the functional block based on a through current value flowing through the comparison circuit based on whether the output signal is at a high level or a low level. A method for determining a test result of a semiconductor device.