JPH06140485A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH06140485A
JPH06140485A JP28803792A JP28803792A JPH06140485A JP H06140485 A JPH06140485 A JP H06140485A JP 28803792 A JP28803792 A JP 28803792A JP 28803792 A JP28803792 A JP 28803792A JP H06140485 A JPH06140485 A JP H06140485A
Authority
JP
Japan
Prior art keywords
semiconductor chip
semiconductor
chip
measurement
pad electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28803792A
Other languages
Japanese (ja)
Inventor
Hidetoshi Honda
秀俊 本田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP28803792A priority Critical patent/JPH06140485A/en
Publication of JPH06140485A publication Critical patent/JPH06140485A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To reduce an area of a semiconductor chip by providing pad electrodes for measurement having larger sizes on a semiconductor wafer on the outside of the chip and reducing the sizes of pad electrodes for connecting outside on the semiconductor chip. CONSTITUTION:When pad electrodes 4 for measurement having larger sizes are provided on a semiconductor wafer 1 outside a semiconductor chip area and the electrodes 4 are connected to pad electrodes 3 for connecting outside on a semiconductor chip 2 through metallic wires 5, the sizes of the electrodes 3 can be reduced. At the time of performing measurement on the chip 2, the pad electrodes 4 are used and, at the time of incorporating the chip 2 in a package, the pad electrodes 3 are used. Therefore, the area of the semiconductor chip 2 can be reduced, since the need of providing the pad electrodes for measurement which require large sizes on the semiconductor chip is eliminated.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置に関し、特に
半導体チップの外部接続用電極に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to an external connection electrode for a semiconductor chip.

【0002】[0002]

【従来の技術】従来の半導体装置は、図3に示すよう
に、半導体ウェーハ1に形成した半導体チップ2のそれ
ぞれに外部接続用パッド電極3が設けられており、半導
体チップ2が設計どおり動作するかを確認するために、
半導体ウェーハ1上の各半導体チップ2に設けた複数の
外部接続用パッド電極3のそれぞれに、多数の針状の電
極を有する測定用治具の各電極を接触させて、テスト信
号を印加し、得られた半導体チップ2の出力信号により
良否の判定をしていた。
2. Description of the Related Art In a conventional semiconductor device, as shown in FIG. 3, each semiconductor chip 2 formed on a semiconductor wafer 1 is provided with an external connection pad electrode 3, and the semiconductor chip 2 operates as designed. To see if
Each of a plurality of external connection pad electrodes 3 provided on each semiconductor chip 2 on the semiconductor wafer 1 is brought into contact with each electrode of a measurement jig having a large number of needle-shaped electrodes, and a test signal is applied, The pass / fail judgment was made based on the obtained output signal of the semiconductor chip 2.

【0003】[0003]

【発明が解決しようとする課題】この従来の半導体装置
は、各半導体チップの測定を行うために、半導体チップ
の外部接続用パッド電極のひとつひとつについて位置合
せを行ってから測定用治具の電極を接触させる必要があ
る。
In this conventional semiconductor device, in order to measure each semiconductor chip, each of the external connection pad electrodes of the semiconductor chip is aligned and then the electrodes of the measuring jig are mounted. Need to make contact.

【0004】そのため、位置合せに高精度が要求される
とともに、半導体チップの外部接続用パッド電極を小さ
くできなかった。
Therefore, high precision is required for alignment, and the external connection pad electrode of the semiconductor chip cannot be made small.

【0005】このため、外部接続用パッド電極の数が多
くなるとチップ面積が増大して製造コストが上昇した
り、半導体チップを小形のパッケージに実装する事がで
きないなどの問題点があった。
Therefore, when the number of pad electrodes for external connection increases, the chip area increases, the manufacturing cost rises, and the semiconductor chip cannot be mounted in a small package.

【0006】[0006]

【課題を解決するための手段】本発明の半導体装置は、
半導体ウェーハに形成して外部接続用パッド電極を有す
る半導体チップと、前記半導体チップ領域以外の半導体
ウェーハ上に設けて前記外部接続用パッド電極との間を
金属配線により接続する測定用パッド電極とを備えてい
る。
The semiconductor device of the present invention comprises:
A semiconductor chip having a pad electrode for external connection formed on a semiconductor wafer, and a measurement pad electrode provided on the semiconductor wafer other than the semiconductor chip region and connected to the pad electrode for external connection by metal wiring. I have it.

【0007】[0007]

【実施例】次に、本発明について図面を参照して説明す
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

【0008】図1は本発明の第1の実施例を示すレイア
ウト図である。
FIG. 1 is a layout diagram showing a first embodiment of the present invention.

【0009】図1に示すように、半導体ウェーハ1に形
成した半導体チップ2のそれぞれに設けた外部接続用パ
ッド電極3と半導体ウェーハ1の半導体チップ2の領域
以外の領域に設けた面積の大きい測定用パッド電極4と
の間を金属配線5により接続している。
As shown in FIG. 1, the pad electrode 3 for external connection provided on each of the semiconductor chips 2 formed on the semiconductor wafer 1 and the large area provided on a region other than the region of the semiconductor chip 2 of the semiconductor wafer 1 are measured. The metal pad 5 is connected to the pad electrode 4 for use.

【0010】図2は本発明の第2の実施例を示すレイア
ウト図である。
FIG. 2 is a layout diagram showing a second embodiment of the present invention.

【0011】図2に示すように、半導体チップ2のそれ
ぞれに隣接して測定端子領域6を設け、その測定端子領
域6内に配置した測定用パッド電極4と、半導体チップ
2の内部に設けた外部接続用パッド電極3との間を金属
配線5により接続している。
As shown in FIG. 2, a measurement terminal region 6 is provided adjacent to each of the semiconductor chips 2, and the measurement pad electrode 4 arranged in the measurement terminal region 6 and the inside of the semiconductor chip 2 are provided. A metal wiring 5 connects the external connection pad electrode 3 to each other.

【0012】なお、半導体チップ2は測定用パッド電極
3により良否を判定後それぞれ分割され、測定用パッド
電極3とは切りはなされる。
The semiconductor chip 2 is divided by the measuring pad electrodes 3 after the quality is judged, and is separated from the measuring pad electrodes 3.

【0013】[0013]

【発明の効果】以上説明したように本発明は、半導体チ
ップ内に設けた外部接続用パッド電極と金属配線を介し
て接続する測定用パッド電極を半導体チップ領域以外の
半導体ウェーハ上に設けることにより、大きなサイズが
必要な測定用パッド電極をチップ内に設ける必要がなく
なり、半導体チップ上の外部接続用パッド電極のサイズ
を小さくできる。
As described above, according to the present invention, the measuring pad electrode, which is connected to the external connecting pad electrode provided in the semiconductor chip through the metal wiring, is provided on the semiconductor wafer other than the semiconductor chip region. It is not necessary to provide a measurement pad electrode that requires a large size in the chip, and the size of the external connection pad electrode on the semiconductor chip can be reduced.

【0014】このため、チップ面積を小さくでき、製造
コストを削減できるという効果がある。
Therefore, the chip area can be reduced and the manufacturing cost can be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例を示すレイアウト図。FIG. 1 is a layout diagram showing a first embodiment of the present invention.

【図2】本発明の第2の実施例を示すレイアウト図。FIG. 2 is a layout diagram showing a second embodiment of the present invention.

【図3】従来の半導体装置の一例を示すレイアウト図。FIG. 3 is a layout diagram showing an example of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 半導体ウェーハ 2 半導体チップ 3 外部接続用パッド電極 4 測定用パッド電極 5 金属配線 6 測定端子領域 1 semiconductor wafer 2 semiconductor chip 3 pad electrode for external connection 4 pad electrode for measurement 5 metal wiring 6 measurement terminal area

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体ウェーハに形成して外部接続用パ
ッド電極を有する半導体チップと、前記半導体チップ領
域以外の半導体ウェーハ上に設けて前記外部接続用パッ
ド電極との間を金属配線により接続する測定用パッド電
極とを備えたことを特徴とする半導体装置。
1. A measurement in which a semiconductor chip having a pad electrode for external connection formed on a semiconductor wafer and a pad provided for external connection provided on a semiconductor wafer other than the semiconductor chip region are connected by metal wiring. A semiconductor device, comprising: a pad electrode for a semiconductor device.
【請求項2】 測定用パッド電極を半導体チップのそれ
ぞれに隣接して設けた接続端子領域内に設けた請求項1
記載の半導体装置。
2. The measuring pad electrode is provided in a connection terminal region provided adjacent to each of the semiconductor chips.
The semiconductor device described.
JP28803792A 1992-10-27 1992-10-27 Semiconductor device Pending JPH06140485A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28803792A JPH06140485A (en) 1992-10-27 1992-10-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28803792A JPH06140485A (en) 1992-10-27 1992-10-27 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH06140485A true JPH06140485A (en) 1994-05-20

Family

ID=17725014

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28803792A Pending JPH06140485A (en) 1992-10-27 1992-10-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH06140485A (en)

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