JPH06252234A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device wherein a test device formed on a test chip is useable also after dicing and hence the cost of an evaluating apparatus for the test device is limited. CONSTITUTION:A transistor chip 2 and a TEG chip 6 are formed with the same size and the same, and they are disposed in a regular matrix whereby a dicing line 1 is provided without extending over the TEG chip. In each TEG chip 6, the positional relation of the TEG electrode 7 in the TEG chip 6 is adapted so as to coincide with the positional relation of a transistor electrode 4 in the transistor chip 2. A test device is prevented from being broken even after a semiconductor wafer is cut, of that use of the test device after the dicing becomes possible and hence an exclusive prober for a test device is made unnecessary, to result correspondingly in a low cost evaluating apparatus for a test device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a semiconductor wafer is provided with a plurality of semiconductor chips each having a semiconductor integrated circuit and a test chip having a test element formed thereon.

[0002]

2. Description of the Related Art FIG. 2 is a plan view showing a part of a semiconductor device in which a plurality of transistor chips each having a semiconductor integrated circuit are arranged and formed on a semiconductor wafer (not shown). As shown in the figure, a plurality of transistor chips 2 are arranged. A semiconductor integrated circuit to be actually used is formed on each transistor chip 2, and input / output with an external signal is possible through the transistor electrode 4 for actual operation. A dicing line 1 is provided between these transistor chips 2 and 2.

In addition, one T
An EG (Test Element Group) chip 3 is provided, and a test element group for verifying the quality of the semiconductor wafer is formed on the TEG chip 3. Then, it can be electrically connected to an external measuring device via the TEG electrode 5 to measure the electrical characteristics such as the resistance value and the voltage-current characteristic of the test element group. The dicing line 1 is also provided between the TEG chip 3 and the transistor chip 2.

By dicing (cutting) the semiconductor device in which a plurality of transistor chips 2 and one TEG chip 3 are formed on a semiconductor wafer in this way along a dicing line 1, a plurality of individual chips are obtained. The transistor chip 2 can be obtained.

[0005]

The test element group is formed for the purpose of testing various electrical characteristics.
The chip size of the G chip 3 is larger than that of the transistor chip 2.

Therefore, the transistor chip 2 and the TE
The chip size is different from that of the G chip 3, and the transistor chip 2 on which a semiconductor integrated circuit to be an actual product is formed is preferentially provided with the dicing line 1. Therefore, as shown in 1A of FIG. A dicing line will be provided.

Therefore, since the test element group formed on the TEG chip 3 is destroyed after the dicing (cutting) of the semiconductor wafer, the TEG chip 3 is diced after the dicing.
There was a problem that you could not use.

Further, the positional relationship between the transistor electrode 4 of the transistor chip 2 and the TEG electrode 5 of the TEG chip 3 is usually different, and the electrical connection between the TEG electrode 5 and an external measuring device is different from that for the transistor chip 2. Since the prober cannot be diverted and the prober dedicated to the TEG chip 3 is separately required, there is a problem that the test device of the test element group formed on the TEG chip 3 requires extra cost.

The present invention has been made to solve the above problems, and the test element formed on the test chip can be used even after dicing, and the cost of the apparatus for evaluating the test element before dicing can be reduced. An object is to obtain a semiconductor device which can be suppressed.

[0010]

According to another aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor wafer; and a plurality of semiconductor chips each having a semiconductor integrated circuit provided on the semiconductor wafer and performing a predetermined operation. And a plurality of test chips provided on the semiconductor wafer, each having a test element for evaluation of electrical characteristics formed thereon, wherein the plurality of semiconductor chips and the plurality of test chips are the same. It is formed in a size and shape, and is regularly arranged on the semiconductor wafer via dicing lines.

A semiconductor device according to a second aspect of the present invention is provided with a semiconductor wafer and the semiconductor wafer,
A plurality of semiconductor chips on which semiconductor integrated circuits each having a plurality of electrodes for actual operation for performing a predetermined operation are formed, and a plurality of test electrodes for connecting an external signal, which are provided on the semiconductor wafer. Having a plurality of test chips each formed with a test element for evaluation of electrical characteristics, in each of the plurality of test chips, the relative position of the arrangement of all the plurality of test electrodes The relationship matches the relative positional relationship of at least a part of the arrangement of the plurality of actual operation electrodes in any of the plurality of semiconductor chips.

[0012]

According to the present invention, the plurality of semiconductor chips and the plurality of test chips of the semiconductor device according to the present invention are formed in the same size and shape, and are regular on the semiconductor wafer via dicing lines. Therefore, even if the semiconductor wafer is cut along the dicing line, not only the semiconductor integrated circuit formed on each of the plurality of semiconductor chips but also the test element formed on each of the plurality of test chips are destroyed. There is no such thing.

In a semiconductor device according to a second aspect of the present invention, in each of the plurality of test chips, the relative positional relationship of the arrangement of all of the plurality of test electrodes is plural in at least one of the plurality of semiconductor chips. The prober for testing the semiconductor integrated circuit of the semiconductor chip is diverted for testing the test element formed on each test chip because it matches the relative positional relationship of at least a part of the actual operation electrodes can do.

[0014]

1 is a plan view showing a part of a semiconductor device according to an embodiment of the present invention, in which a plurality of transistor chips each having a semiconductor integrated circuit are arranged and formed on a semiconductor wafer (not shown). It is a figure. As shown in the figure, a plurality of transistor chips 2 having exactly the same internal configuration are arranged. A semiconductor integrated circuit to be actually used is formed in each transistor chip 2, and it is possible to exchange with external input / output signals via a plurality of transistor electrodes 4 for actual operation. A dicing line 1 is provided between these transistor chips 2 and 2.

A TEG (Test) having the same size and shape as the transistor chip 2 is formed on a part of the semiconductor wafer.
Element Group) Four chips 3 are provided, and these T
A test element for verifying the quality of the semiconductor wafer is formed on each of the EG chips 6. Usually, the TEG chips 6 that are combined into one chip are separated into four chips, so that the chip size of each TEG chip 6 can be reduced. Therefore, each TEG chip 6 is the same as each transistor chip 2. It can be formed in the same size and shape. Further, by forming the TEG chips 6 separately, the TEG electrodes 7 required for each TEG chip 6 are formed.
The number of can also be reduced.

The dicing line 1 is also provided between the TEG chip 6 and the transistor chip 2. Since the transistor chips 2 and the TEG chips 6 have the same size and the same shape, the transistor chips 2 and the TEG chips 6 can be arranged in a regular matrix as shown in FIG. Therefore, as shown in FIG. 1, the dicing line 1 can be provided along the row direction and the column direction of the transistor chip 2 and the TEG chip 6 without passing over the TEG chip 3.

Further, in each TEG chip 6,
The relative positional relationship of the arrangement of the TEG electrodes 7 in the TEG chip 6 is formed to match the relative positional relationship of the transistor electrodes 4 in the transistor chip 2.

Taking FIG. 1 as an example, assuming that the transistor electrode 4a of the transistor chip 2 and the TEG electrode 7a of the TEG chip 6 are reference electrodes (origins), the coordinates of the transistor electrode 4b and the TEG electrode 7b with respect to the origin. It means that the positions match. Each TEG chip 6
Each of them can be electrically connected to an external measuring instrument via these TEG electrodes 7 to measure the electrical characteristics such as the resistance value and voltage-current characteristics of the test element.

In the semiconductor device of this embodiment, since the transistor chip 2 and the TEG chip 6 are formed in the same size and the same shape, they do not pass over the TEG chip 3,
The dicing line 1 can be provided, and after dicing, not only the semiconductor integrated circuits formed on the transistor chips 2 individually divided but also the TEGs individually divided.
The test element group of the chip 6 can also be obtained without being destroyed. As a result, even after dicing, the TEG
Electrical characteristics can be evaluated using the test element group of the chip 6 (first effect).

The semiconductor device of this embodiment is a TEG.
Since the relative positional relationship of the arrangement of all the TEG electrodes 7 in the chip 6 is formed to match the relative positional relationship of the arrangement of the transistor electrodes 4 in the transistor chip 2, the operation of the semiconductor integrated circuit of the transistor chip 2 is performed. The prober for measurement can be used for measurement of the test element of the TEG chip 6 performed before dicing.
Since the test element of the TEG chip 6 can be measured without using a G-dedicated prober, the TEG evaluation device can be constructed at low cost (second effect).

If the chip size and shape of the TEG chip 6 can be formed to be the same as the chip size and shape of the transistor chip 2, the first effect can be obtained regardless of the arrangement of the TEG electrodes 7 of the TEG chip 6.

Further, even if the chip size or shape of the TEG chip 6 is different from the chip size or shape of the transistor chip 2, the relative positional relationship of all the TEG electrodes 7 of each TEG chip 6 is calculated as follows. If the relative positional relationship of at least a part of the transistor electrode 4 can be matched, the second effect can be obtained.

In this embodiment, a plurality of semiconductor chips having the same internal structure (electrode arrangement) are arranged on the semiconductor wafer, but a plurality of types of semiconductor chips having different internal structures (electrode arrangement) are arranged on the semiconductor wafer. It is also possible to arrange a plurality of them. In this case, the relative positional relationship of all the TEG electrodes of each TEG chip is calculated from among the plurality of types of semiconductor chips.
The second effect can be obtained by matching the relative positional relationship of at least a part of at least one of the semiconductor chips.

[0024]

As described above, the plurality of semiconductor chips and the plurality of test chips of the semiconductor device according to the first aspect of the present invention are formed in the same size and shape, and on the semiconductor wafer. Since the semiconductor wafers are regularly arranged through the dicing lines, even if the semiconductor wafer is cut along the dicing lines, not only the semiconductor integrated circuit formed on each of the plurality of semiconductor chips but also each of the plurality of test chips are formed. The tested test element is not destroyed.

As a result, the test element formed on each test chip can be used even after cutting along the dicing line.

Further, in the semiconductor device according to the second aspect of the present invention, in each of the plurality of test chips, the relative positional relationship of the arrangement of all the plurality of test electrodes is plural in at least one of the plurality of semiconductor chips. The prober for testing the semiconductor integrated circuit of the semiconductor chip is diverted for testing the test element formed on each test chip because it matches the relative positional relationship of at least a part of the actual operation electrodes can do.

As a result, since a prober dedicated to the test element is not required, the evaluation device for the test element can be constructed at low cost.

[Brief description of drawings]

FIG. 1 is a plan view showing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a plan view showing a conventional semiconductor device.

[Explanation of symbols]

 1 Dicing line 2 Transistor chip 4 Transistor electrode 6 TEG chip 7 TEG electrode

Claims (2)

[Claims] 1. A semiconductor wafer, a plurality of semiconductor chips provided on the semiconductor wafer, each having a semiconductor integrated circuit performing a predetermined operation, and a test provided on the semiconductor wafer for evaluating electrical characteristics. And a plurality of test chips each having a test element formed thereon, wherein the plurality of semiconductor chips and the plurality of test chips are formed in the same size and shape, and a dicing line is formed on the semiconductor wafer. A semiconductor device characterized in that the semiconductor device is arranged with regularity. 2. A semiconductor wafer, a plurality of semiconductor chips provided on the semiconductor wafer, each performing a predetermined operation, and forming a semiconductor integrated circuit having a plurality of electrodes for actual operation for external signal connection, respectively. Provided on a semiconductor wafer, having a plurality of test electrodes for external signal connection, a plurality of test chips each having a test element for evaluation of electrical characteristics formed, and a plurality of the test chips In each of them, the relative positional relationship of the arrangement of all of the plurality of test electrodes matches the relative positional relationship of at least a part of the arrangement of the plurality of actual operation electrodes in at least one of the plurality of semiconductor chips. A semiconductor device characterized by the above.