JPH08316407A - Manufacture of composite semiconductor package - Google Patents

Manufacture of composite semiconductor package

Info

Publication number
JPH08316407A
JPH08316407A JP13989295A JP13989295A JPH08316407A JP H08316407 A JPH08316407 A JP H08316407A JP 13989295 A JP13989295 A JP 13989295A JP 13989295 A JP13989295 A JP 13989295A JP H08316407 A JPH08316407 A JP H08316407A
Authority
JP
Japan
Prior art keywords
semiconductor
package
composite
semiconductor chip
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13989295A
Other languages
Japanese (ja)
Inventor
Kazunori Kishimoto
一徳 岸本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP13989295A priority Critical patent/JPH08316407A/en
Publication of JPH08316407A publication Critical patent/JPH08316407A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Testing Of Individual Semiconductor Devices (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE: To perform selection test of built-in semiconductor chips by using the same method used for a single semiconductor chip, in a composite semiconductor package. CONSTITUTION: In a composite semiconductor package in which a plurality of semiconductor chips 12, 13 are included, signal 16 which directly connects the part between the internal semiconductor chips 12, 13 is led out by a lead frame 15 of a divided shape, as individual signals of chips, to the outside as terminals, and selection test is performed. After the selection test, the divided lead frames are short-circuitted by a method like soldering, and signal connection between the semiconductor chips is performed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、複合形半導体パッケー
ジの製造方法に関し、特に半導体集積回路の複数の半導
体チップを納めた複合形半導体パッケージの製造方法に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a composite semiconductor package, and more particularly to a method for manufacturing a composite semiconductor package containing a plurality of semiconductor chips of a semiconductor integrated circuit.

【0002】[0002]

【従来の技術】半導体は一つのパッケージに一つの半導
体チップを納めるものが一般的であるが、半導体を使用
する装置側からの要求として複数の半導体を小型化・薄
型化したものを求められる場合がある。こういう場合の
解決方法の一例として、一つのパッケージに複数の半導
体チップを納める複合形半導体と呼ばれるものがある。
また、通常の半導体では、リードフレームと呼ばれる導
電性のフレームによって半導体チップとパッケージの端
子とを接続することで半導体チップの信号をパッケージ
外部に取り出している。
2. Description of the Related Art Generally, a semiconductor is one in which one semiconductor chip is housed in one package. However, in the case where a plurality of semiconductors are required to be miniaturized and thinned as a request from a device using the semiconductor. There is. As an example of a solution to such a case, there is a so-called compound semiconductor in which a plurality of semiconductor chips are housed in one package.
In addition, in a normal semiconductor, a signal of the semiconductor chip is taken out of the package by connecting the semiconductor chip and the terminal of the package with a conductive frame called a lead frame.

【0003】従来例1の複合形半導体について図5に示
す。、図5は従来例1の複合形半導体パッケージの内部
を示した図で、複合形半導体は、パッケージ(51)に
半導体チップ(52)と半導体チップ(53)が納めら
れている。半導体チップ(52)と半導体チップ(5
3)からパッケージ外部につながる信号は、通常の半導
体パッケージと同様にリードフレーム(54)によって
パッケージ端子と接続されるが、半導体チップ(52)
と半導体チップ(53)間で直接接続する信号(55)
に関しては、パッケージ内部で直接接続されパッケージ
(51)の外部に端子として取り出されない。この複合
形半導体は、複数の半導体が1つのパッケージにまとま
っており、また半導体パッケージ間の信号を基板上で接
続しており、半導体パッケージ内に収まるため基板上の
配線を少なくなるといった利点もある。
FIG. 5 shows a composite semiconductor of Conventional Example 1. FIG. 5 is a view showing the inside of the composite semiconductor package of the first conventional example. In the composite semiconductor, a package (51) includes a semiconductor chip (52) and a semiconductor chip (53). The semiconductor chip (52) and the semiconductor chip (5
The signal from 3) to the outside of the package is connected to the package terminal by the lead frame (54) as in a normal semiconductor package.
Signal (55) for direct connection between the semiconductor chip (53) and
With regard to (2), it is directly connected inside the package and is not taken out as a terminal to the outside of the package (51). This composite semiconductor has an advantage that a plurality of semiconductors are integrated into one package and signals between the semiconductor packages are connected on the substrate, and the signals are accommodated in the semiconductor package, so that the wiring on the substrate is reduced. .

【0004】また、従来例2の複合形半導体について図
7に示す。図7の特開昭62−85457で提案されて
いる従来例の複合形半導体パッケージの内部を示した図
で、ピングリットアレイ構造の半導体パッケージの場合
に複数の半導体チップを納たものである。半導体チップ
(73)をパッケージ(71)に実装し、半導体チップ
(74)をパッケージ(72)に実装し、その後パッケ
ージ(71)と(72)を組合わせることで複合形半導
体パッケージを構成する。半導体チップ(73)の信号
は端子(75)に、半導体チップ(74)の信号は端子
(76)に、それぞれ接続されるようになおり、半導体
チップの信号を端子としてパッケージ外部に取り出すこ
とができるものである。
FIG. 7 shows a composite semiconductor of Conventional Example 2. FIG. 7 is a diagram showing the inside of a conventional composite type semiconductor package proposed in Japanese Patent Laid-Open No. 62-85457 of FIG. 7, in which a plurality of semiconductor chips are housed in the case of a semiconductor package having a pin grid array structure. The semiconductor chip (73) is mounted on the package (71), the semiconductor chip (74) is mounted on the package (72), and then the packages (71) and (72) are combined to form a composite semiconductor package. The signal of the semiconductor chip (73) is connected to the terminal (75), and the signal of the semiconductor chip (74) is connected to the terminal (76). The signal of the semiconductor chip can be taken out as a terminal to the outside of the package. It is possible.

【0005】[0005]

【発明が解決しようとする課題】上述したように従来例
1の複合形半導体では、一つのパッケージに収まった複
数半導体チップの信号のうち、半導体チップ間で直接接
続される信号に関しては、パッケージ内で直接接続が行
われている。通常、半導体は完成時に良品か不良品かを
選別するため検査を行う必要があるが、単体の半導体で
は半導体テスタと呼ばれる検査機によって、その半導体
のパッケージ端子に対し入力端子に信号を入力し、出力
端子の信号を検査することにより、半導体の良/不良を
判定を行う。
As described above, in the composite semiconductor of Conventional Example 1, among the signals of a plurality of semiconductor chips contained in one package, the signals directly connected between the semiconductor chips are in the package. A direct connection is made in. Normally, it is necessary to inspect a semiconductor to determine whether it is a good product or a defective product at the time of completion, but with a single semiconductor, an inspection machine called a semiconductor tester inputs a signal to the input terminal for the package terminal of the semiconductor, By checking the signal at the output terminal, it is determined whether the semiconductor is good or bad.

【0006】ところが、上述した従来例1の複合形半導
体では、半導体チップ間で直接つながれた信号に関して
は、パッケージ端子として外部に取り出されないため、
半導体テスタでは、この信号に対し入力を与えたり出力
を検査することができないものである。そのため、単体
の半導体を選別検査するために作成した選別手段は、従
来例1の複合形半導体の選別検査には、そのまま使用す
ることができないという問題があり、複合形半導体とし
て外部に取り出されている信号だけを使用して行う選別
手段を新たに作成しなければならないという問題があ
る。
However, in the above-described composite semiconductor of the first conventional example, the signal directly connected between the semiconductor chips is not taken out as a package terminal to the outside.
A semiconductor tester cannot give an input to this signal or inspect its output. Therefore, there is a problem that the sorting means created for the sorting inspection of the single semiconductor cannot be used as it is for the sorting inspection of the composite semiconductor of Conventional Example 1, and it is taken out to the outside as the composite semiconductor. There is a problem in that it is necessary to newly create a sorting means that uses only existing signals.

【0007】すなわち、通常の単体半導体として製造さ
れていた半導体をパッケージの小型化をはかるため複合
形半導体として新たに開発する場合でも、すでに作成済
みの選別方法をそのまま流用して利用することができ
ず、選別方法まで新たに開発しなければいけないという
問題がある。このため従来の複合形半導体では、通常の
単体半導体を複合形半導体として開発する際の設計・評
価等に関わる時間・手間が増えてしまうという欠点があ
る。
That is, even when a semiconductor manufactured as an ordinary single semiconductor is newly developed as a composite semiconductor in order to reduce the size of a package, the sorting method already prepared can be used as it is. First, there is the problem that a selection method must be newly developed. Therefore, the conventional composite type semiconductor has a drawback in that the time and effort involved in designing / evaluating etc. when developing an ordinary single semiconductor as a composite type semiconductor increases.

【0008】また、図7に示す従来例2の複合形半導体
では、半導体チップ(73)の信号は端子(75)に接
続され、半導体チップ(74)の信号は端子(76)に
接続されるため、それぞれ独立して選別検査を行うこと
ができる。しかし、ピングリットアレイパッケージは構
造が複雑であるため製造コストが高く、さらにパッケー
ジの構造が複雑となり、組立作業も複雑であるため製造
コストが高くなってしまう欠点がある。
Further, in the composite type semiconductor of Conventional Example 2 shown in FIG. 7, the signal of the semiconductor chip (73) is connected to the terminal (75) and the signal of the semiconductor chip (74) is connected to the terminal (76). Therefore, the selection inspection can be performed independently. However, the pingrit array package has a disadvantage that the manufacturing cost is high due to its complicated structure, and the structure of the package is complicated and the assembling work is also complicated, resulting in a high manufacturing cost.

【0009】[0009]

【課題を解決するための手段】本発明は、複数の半導体
チップを納めた複合形半導体パッケージの製造方法にお
いて、複合形半導体パッケージの複数の半導体チップに
所定のリードフレームを接続し外部に端子として取り出
し、かつ前記半導体チップ間を直接接続する信号を分割
した形状を持つリードフレームに個々に接続し外部に端
子として取り出し、次いで前記分割した形状を持つリー
ドフレームを短絡させることによって、半導体チップ間
を直接接続する信号の接続を行うことを特徴とする複合
形半導体パッケージの製造方法である。また本発明は、
半導体チップ間を直接接続する信号を分割した形状を持
つリードフレームに個々に接続し外部に端子として取り
出し、半導体チップの選別検査を前記半導体チップの全
信号に対し行い、次いで前記分割した形状を持つリード
フレームを短絡させることを特徴とする複合形半導体パ
ッケージの製造方法である。
According to the present invention, in a method of manufacturing a composite type semiconductor package containing a plurality of semiconductor chips, a predetermined lead frame is connected to the plurality of semiconductor chips of the composite type semiconductor package to serve as external terminals. By taking out and connecting the signals for directly connecting the semiconductor chips individually to lead frames having a divided shape and taking them out as terminals to the outside, and then short-circuiting the lead frames having the divided shapes, the semiconductor chips are separated from each other. A method of manufacturing a composite type semiconductor package is characterized in that a signal for direct connection is connected. The present invention also provides
Signals that directly connect between semiconductor chips are individually connected to lead frames having a divided shape and taken out as terminals, and the semiconductor chips are selected and inspected for all signals of the semiconductor chip, and then have the divided shape. A method of manufacturing a composite type semiconductor package, characterized in that a lead frame is short-circuited.

【0010】[0010]

【作用】本発明は、複合形半導体パッケージにおいて内
蔵する複数の半導体チップの信号をチップ個々の信号と
してパッケージ外部に端子として取り出すための分割し
たリードフレームを有しているものであり、この分割さ
れたリードフレームを半田付け等の手段で短絡させ半導
体チップ間の信号を接続する手段を有するもので、複合
形半導体の利点のひとつであるパッケージの外での信号
配線を減らすことができ、また半導体の選別検査を半導
体チップ個々に行うことができるものである。
The present invention has a divided lead frame for taking out the signals of a plurality of semiconductor chips contained in the composite type semiconductor package as the individual signals of the chips to the outside of the package as terminals. Since it has a means for connecting signals between semiconductor chips by shorting the lead frame by means such as soldering, it is possible to reduce the signal wiring outside the package, which is one of the advantages of the composite type semiconductor. It is possible to perform the sorting inspection of each semiconductor chip.

【0011】[0011]

【実施例】次に、本発明の実施例について図面を参照し
て説明する。 [実施例1]本発明の第1の実施例を図1、図2、図3
で説明する。図1は本発明の実施例の複合形半導体パッ
ケージ内部の状態を示した図、図2はパッケージ斜視
図、図3は複合形半導体パッケージの端子の拡大図であ
る。図1、図2に示すように、半導体チップ(12)と
半導体チップ(13)は、複合形半導体パッケージ(1
1)に実装されている。通常の信号(17)は、リード
フレーム(14)と導電性のワイヤによって接続するこ
とで複合形半導体パッケージ(11)の外部に端子とし
て取り出す。
Embodiments of the present invention will now be described with reference to the drawings. [Embodiment 1] A first embodiment of the present invention is shown in FIGS.
Described in. FIG. 1 is a diagram showing an internal state of a composite semiconductor package according to an embodiment of the present invention, FIG. 2 is a perspective view of the package, and FIG. 3 is an enlarged view of terminals of the composite semiconductor package. As shown in FIG. 1 and FIG. 2, the semiconductor chip (12) and the semiconductor chip (13) are composed of a composite semiconductor package (1
It is implemented in 1). A normal signal (17) is taken out as a terminal to the outside of the composite type semiconductor package (11) by connecting it to the lead frame (14) by a conductive wire.

【0012】半導体チップ(12)と半導体チップ(1
3)を直接接続する信号(16)は、半導体チップ(1
2)に接続するリードフレーム(15)と、半導体チッ
プ(13)に接続するリードフレーム(15)とに分割
した形状にされている。すなわち、半導体チップ(1
2)と半導体チップ(13)を直接接続する信号(1
6)は、分割した形状のリードフレーム(15)のそれ
ぞれのフレームに接続を行い、パッケージ外部に2本の
端子として取り出す。このようにして、半導体チップ
(12)及び半導体チップ(13)の信号全てを複合形
半導体パッケージ(11)の外部に端子として取り出し
ている。
The semiconductor chip (12) and the semiconductor chip (1
The signal (16) for directly connecting 3) is applied to the semiconductor chip (1
The lead frame (15) connected to 2) and the lead frame (15) connected to the semiconductor chip (13) are divided into shapes. That is, the semiconductor chip (1
2) The signal (1) that directly connects the semiconductor chip (13)
6) is connected to each frame of the lead frame (15) having the divided shape, and is taken out as two terminals to the outside of the package. In this way, all the signals of the semiconductor chip (12) and the semiconductor chip (13) are taken out as terminals to the outside of the composite type semiconductor package (11).

【0013】次に、半導体チップの選別検査について説
明する。図6は単体半導体パッケージの内部を示した図
で、半導体チップ(12)が単体の製品としてすでに存
在している場合の半導体チップの選別検査考えると、半
導体チップ(12)の全信号がリードフレーム(62)
と接続されパッケージ(61)の外部に取り出されてい
る。この場合の選別検査は外部に取り出された全信号に
対し、信号の入力信号あるいは出力信号の観測すること
で行う。
Next, a semiconductor chip selection inspection will be described. FIG. 6 is a view showing the inside of a single semiconductor package. Considering the semiconductor chip sorting inspection when the semiconductor chip (12) already exists as a single product, all signals of the semiconductor chip (12) are lead frames. (62)
And is taken out of the package (61). In this case, the selection inspection is performed by observing the input signal or output signal of all the signals taken out.

【0014】本実施例の図1に示す複合形半導体パッケ
ージ(11)では、半導体チップ(12)と半導体チッ
プ(13)を直接接続する信号(16)は、分割した形
状のリードフレーム(15)のそれぞれに接続されてお
り、半導体チップ(12)及び半導体チップ(13)の
信号全てを複合形半導体パッケージ(11)の外部に端
子として取り出しているので、上記図6に示すような、
単体半導体の選別検査で使用していた方法が、半導体チ
ップの選別検査にそのまま流用することが可能である。
そのため新たな選別検査方法を開発する必要がないもの
である。
In the composite type semiconductor package (11) of this embodiment shown in FIG. 1, the signal (16) for directly connecting the semiconductor chip (12) and the semiconductor chip (13) has a divided lead frame (15). Since all the signals of the semiconductor chip (12) and the semiconductor chip (13) are connected to the outside of the composite semiconductor package (11) as terminals, as shown in FIG.
The method used in the sorting inspection of the single semiconductors can be used as it is in the sorting inspection of the semiconductor chips.
Therefore, it is not necessary to develop a new screening inspection method.

【0015】次いで、図3の複合形半導体パッケージの
端子の拡大図に示すように分割されているリードフレー
ムを接合(短絡)する。上述したように半導体チップの
選別検査を行った後、図3(a)に示すように分割され
ているリードフレーム(15)を半田付け等の手段で短
絡することにより、図3(b)に示すような通常のリー
ドフレーム(14)と同様なリードフレーム(31)と
して仕上げる。これにより半導体チップ(12)と半導
体チップ(13)を直接接続する信号(16)のチップ
間の接続が行われ、複合形半導体としての所定の機能を
実現する。
Next, as shown in the enlarged view of the terminals of the composite type semiconductor package of FIG. 3, the divided lead frames are joined (short-circuited). After the semiconductor chips are selected and inspected as described above, the divided lead frames (15) are short-circuited by means such as soldering as shown in FIG. Finish as a leadframe (31) similar to the normal leadframe (14) as shown. As a result, the semiconductor chip (12) and the semiconductor chip (13) are directly connected between the chips of the signal (16), and a predetermined function as a compound semiconductor is realized.

【0016】[実施例2]図4は、第2の実施例4の複
合形半導体パッケージの内部を示した図である。半導体
チップ(12)と半導体チップ(13)の間を直接接続
する信号(16)が、それぞれに4本ある場合で、分割
した形状のリードフレーム(15)に接続を行い、パッ
ケージ外部にそれぞれに4本の端子として取り出し、半
導体チップ(12)及び半導体チップ(13)の信号全
てを複合形半導体パッケージの外部に端子として取り出
している。このように、上記実施例1では、半導体チッ
プ間を直接接続する信号が2本である例について説明し
たが、半導体チップ(12)と(13)の間を直接接続
する信号(16)が4本ある場合に関しても、図4に示
すような例で実現することが可能である。また信号の数
が5本以上となった場合でも同様にして実現可能であ
る。
[Embodiment 2] FIG. 4 is a view showing the inside of a composite type semiconductor package of the second embodiment 4. In the case where there are four signals (16) for directly connecting between the semiconductor chip (12) and the semiconductor chip (13), the lead frame (15) having a divided shape is connected to the outside of the package. Four terminals are taken out, and all signals of the semiconductor chip (12) and the semiconductor chip (13) are taken out as terminals to the outside of the composite type semiconductor package. As described above, in the first embodiment, an example in which the number of signals directly connecting between the semiconductor chips is two has been described, but the number of signals (16) directly connecting between the semiconductor chips (12) and (13) is four. Even in the case where there is a book, it can be realized by an example as shown in FIG. Further, even when the number of signals is five or more, it can be similarly realized.

【0017】[0017]

【発明の効果】以上説明したように本発明によれば、複
合形半導体のパッケージにおいて内蔵する半導体チップ
間を直接接続する信号に対し、分割したリードフレーム
によって個々の半導体チップの信号を別々な端子として
パッケージ外部に取り出すことによって半導体の選別検
査を半導体チップ個々に行うことができる。このため従
来単体半導体であった選別検査の手段を使用して、複合
形半導体として新たなものを開発する場合でも、その選
別検査を行うことができるので、開発にかかる時間・手
間を短縮することが可能となる効果がある。また、選別
検査終了後、分割されたリードフレームの端子を半田付
け等の手段で短絡することにより半導体チップ間の信号
を直接接続することができ、複合形半導体の利点のひと
つであるパッケージの外での信号配線を減らす効果が得
られる。また、本発明の複合形半導体に使用するリード
フレームは、構造は比較的簡単であるため、従来のリー
ドフレームと同程度の価格で作成することが可能であ
り、複合形半導体生産時のコストも押さえることができ
るという効果もある。
As described above, according to the present invention, the signals of the individual semiconductor chips are separated from each other by the divided lead frames for the signals which directly connect the semiconductor chips incorporated in the composite semiconductor package. As a result, the semiconductors can be individually inspected for inspection by taking them out of the package. For this reason, even when a new compound semiconductor is developed by using the sorting inspection method that was conventionally a single semiconductor, the sorting inspection can be performed, so that the time and effort required for development can be shortened. There is an effect that can be. In addition, after completion of the selection inspection, signals between semiconductor chips can be directly connected by short-circuiting the divided lead frame terminals by means such as soldering, which is one of the advantages of composite semiconductors. It is possible to obtain the effect of reducing the signal wiring in. Further, since the lead frame used for the composite semiconductor of the present invention has a relatively simple structure, it can be manufactured at a price comparable to that of the conventional lead frame, and the manufacturing cost of the composite semiconductor is also low. It also has the effect of being able to hold down.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の複合形半導体パッケージの内部を示し
た図
FIG. 1 is a diagram showing the inside of a composite semiconductor package of the present invention.

【図2】本発明の複合形半導体パッケージの斜視図FIG. 2 is a perspective view of a composite semiconductor package of the present invention.

【図3】本発明の複合形半導体パッケージの端子の拡大
FIG. 3 is an enlarged view of terminals of the composite semiconductor package of the present invention.

【図4】本発明の複合形半導体パッケージの内部を示し
た図
FIG. 4 is a diagram showing the inside of a composite semiconductor package of the present invention.

【図5】従来の複合形半導体パッケージの内部を示した
FIG. 5 is a view showing the inside of a conventional composite semiconductor package.

【図6】単体半導体パッケージの内部を示した図FIG. 6 is a diagram showing the inside of a single semiconductor package.

【図7】従来の複合形半導体パッケージの内部を示した
FIG. 7 is a diagram showing the inside of a conventional composite semiconductor package.

【符号の説明】[Explanation of symbols]

11 複合形半導体パッケージ 12 半導体チップ 13 半導体チップ 14 リードフレーム 15 リードフレーム 16 信号 17 信号 31 リードフレーム 51 複合形半導体パッケージ 52 半導体チップ 53 半導体チップ 54 リードフレーム 55 信号 61 半導体パッケージ 62 リードフレーム 71 半導体パッケージ 72 半導体パッケージ 73 半導体チップ 74 半導体チップ 75 端子 76 端子 11 composite type semiconductor package 12 semiconductor chip 13 semiconductor chip 14 lead frame 15 lead frame 16 signal 17 signal 31 lead frame 51 composite type semiconductor package 52 semiconductor chip 53 semiconductor chip 54 lead frame 55 signal 61 semiconductor package 62 lead frame 71 semiconductor package 72 Semiconductor package 73 Semiconductor chip 74 Semiconductor chip 75 terminal 76 terminal

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 複数の半導体チップを納めた複合形半導
体パッケージの製造方法において、複合形半導体パッケ
ージの複数の半導体チップに所定のリードフレームを接
続し外部に端子として取り出し、かつ前記半導体チップ
間を直接接続する信号を分割した形状を持つリードフレ
ームに個々に接続し外部に端子として取り出し、次いで
前記分割した形状を持つリードフレームを短絡させるこ
とによって、半導体チップ間を直接接続する信号の接続
を行うことを特徴とする複合形半導体パッケージの製造
方法。
1. A method of manufacturing a composite type semiconductor package containing a plurality of semiconductor chips, wherein a predetermined lead frame is connected to a plurality of semiconductor chips of the composite type semiconductor package and is taken out as a terminal to the outside, and between the semiconductor chips. Signals for direct connection are connected between the semiconductor chips by individually connecting the signals to be directly connected to the lead frame having a divided shape and taking out as terminals to the outside, and then short-circuiting the lead frame having the divided shape. A method of manufacturing a composite semiconductor package, comprising:
【請求項2】 半導体チップ間を直接接続する信号を分
割した形状を持つリードフレームに個々に接続し外部に
端子として取り出し、半導体チップの選別検査を前記半
導体チップの全信号に対し行い、次いで前記分割した形
状を持つリードフレームを短絡させることを特徴とする
請求項1に記載の複合形半導体パッケージの製造方法。
2. A signal for directly connecting between semiconductor chips is individually connected to a lead frame having a divided shape and taken out as a terminal, and a semiconductor chip selection inspection is performed on all signals of the semiconductor chip, The method of manufacturing a composite type semiconductor package according to claim 1, wherein lead frames having a divided shape are short-circuited.
JP13989295A 1995-05-15 1995-05-15 Manufacture of composite semiconductor package Pending JPH08316407A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13989295A JPH08316407A (en) 1995-05-15 1995-05-15 Manufacture of composite semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13989295A JPH08316407A (en) 1995-05-15 1995-05-15 Manufacture of composite semiconductor package

Publications (1)

Publication Number Publication Date
JPH08316407A true JPH08316407A (en) 1996-11-29

Family

ID=15256043

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13989295A Pending JPH08316407A (en) 1995-05-15 1995-05-15 Manufacture of composite semiconductor package

Country Status (1)

Country Link
JP (1) JPH08316407A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001065605A1 (en) * 2000-03-03 2001-09-07 Hitachi, Ltd. Semiconductor device
JP2010278471A (en) * 2001-03-19 2010-12-09 Renesas Electronics Corp Semiconductor device, and module

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58128754A (en) * 1982-01-27 1983-08-01 Nec Corp Hybrid integrated circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58128754A (en) * 1982-01-27 1983-08-01 Nec Corp Hybrid integrated circuit

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001065605A1 (en) * 2000-03-03 2001-09-07 Hitachi, Ltd. Semiconductor device
US6492727B2 (en) 2000-03-03 2002-12-10 Hitachi, Ltd. Semiconductor device
US6501173B2 (en) 2000-03-03 2002-12-31 Hitachi, Ltd. Semiconductor device
US6531773B2 (en) 2000-03-03 2003-03-11 Hitachi, Ltd. Semiconductor device
KR100828855B1 (en) * 2000-03-03 2008-05-09 가부시키가이샤 히타치세이사쿠쇼 Semiconductor device
KR100842140B1 (en) * 2000-03-03 2008-06-27 가부시키가이샤 히타치세이사쿠쇼 Semiconductor device
JP2010278471A (en) * 2001-03-19 2010-12-09 Renesas Electronics Corp Semiconductor device, and module

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