JPH06232295A - Integrated circuit - Google Patents

Abstract

PURPOSE:To provide an integrated circuit and a circuit substrate small-size with high testability by dissolving size-up caused by an increased number of testing terminals and testing circuits. CONSTITUTION:A circuit substrate 1 can be also small-sized since the increase in the quantity of bottom pins 3 can be suppressed by providing testing terminals 4 on the top of a package 2 and an integrated circuit can be small-sized while requiring no arrangement of a testing circuit on a circuit substrate 1 in the integrated circuit having the structure to be connected to the circuit substrate 1 by a bottom pin 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit such as a semiconductor and a high-density mounting technique and high testability technique for a circuit in which they are mounted.

[0002]

2. Description of the Related Art In recent years, electronic devices have been remarkably reduced in size and weight, and have been improved in function. As a result, the circuit mounting technology and the degree of integration of integrated circuits have been dramatically improved. Therefore, the development of test methods for these circuits is also proceeding at the same time. Even when a failure location is specified in a test, if the circuit scale is small and the focus is on analog, it was often possible to specify the waveform by monitoring the waveform of the signal line during actual operation of the entire circuit. In recent years, as the functions have been further improved and the circuit scale has been increased, it has become very difficult to identify a failure point in the test of the entire circuit. Therefore, the test method is currently shifting from a method of testing the entire circuit to a method of testing individual circuit components. For that purpose, it is necessary to input and output signals to and from most of the pins of individual parts, and therefore, it has been necessary to provide countless test rounds on the circuit board. In addition, integrated circuits, etc. need to have additional functions such as high impedance of output terminals so that they can be tested individually, so in many cases pins dedicated for testing are added and the number of test rounds tends to increase. This is a factor that hinders the miniaturization of circuit boards. However, recently, as a method for solving these problems, IEEEstd. A boundary scanning test method represented by 1149-1 has been developed, and it is becoming possible to secure testability while reducing the number of test rounds.

[0003]

However, although the above-described boundary scan test method can reduce the number of test rounds, it is necessary to add dedicated pins for test such as test data input / output, test clock, and mode switching. However, there is a problem in that the size of the semiconductor increases as the number of pins increases, and the size of the board also increases because it is necessary to add a circuit dedicated to the test onto the circuit board.

An object of the present invention is to solve the above-mentioned conventional problems, and an object thereof is to provide an integrated circuit capable of realizing a circuit board having a small size, a high density, and good testability.

[0005]

To achieve this object, the present invention has a structure in which a test terminal is provided on the upper surface of an integrated circuit.

[0006]

With this structure, it is not necessary to add a pin to the bottom surface of the integrated circuit, and the increase in size can be suppressed. Also, since the test probe is brought into direct contact with the test terminal of the integrated circuit to perform the test, the test circuit on the circuit board which is not needed except during the test can be omitted, so that the circuit board size can be reduced and the cost can be reduced. Can be achieved. When adding a new test function to an existing circuit, the test terminals can be concentrated on the top surface of an integrated circuit that has not been used until now, so it is possible to make the pins on the bottom of the circuit board or integrated circuit compatible. It is possible.

[0007]

EXAMPLES Example 1 Examples of the present invention will be described below.
A description will be given with reference to the drawings.

FIG. 1 is a sectional view of an integrated circuit according to a first embodiment of the present invention. In FIG. 1, 1 is a circuit board, 2 is an integrated circuit package, 3 is bottom pins, 4 is a test terminal, and 5 is a test terminal.
Is a test probe.

The integrated circuit inside the package 2 mounted on the circuit board 1 is connected to the external circuit of the circuit board 1 by the bottom surface pins 3. The test terminal 4 is provided on the upper surface of the package 2 and has a structure capable of directly contacting the test probe 5. A test signal generator, a signal reader, etc. are connected to the test probe 5, and the integrated circuit and the external circuit are tested while the test probe 5 is in contact with the test terminal 4, and the contact is released when the test is completed. Test terminal 4
Is disposed above the package 2 which has not been used so far, the size of the package 2 does not increase. Moreover, since the circuit board 1 is in direct contact with the test probe 5, it is not necessary to provide a test circuit on the circuit board 1.

As described above, according to this embodiment, by providing the test terminal of the integrated circuit on the upper surface of the package,
The size of the integrated circuit can be suppressed and the size of the circuit board can be reduced.

(Second Embodiment) A second embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a sectional view of a multi-chip module (hereinafter referred to as MCM) circuit according to the second embodiment of the present invention. Figure 2
1 is a circuit board, 7 is an integrated circuit chip, 6 is an MCM board, 4 is a test terminal, 3 is a bottom pin, 8 is a resin mold, and 5 is a test probe.

A plurality of chips 7 and other circuit elements are arranged and wired on the MCM substrate 6 and connected to an external circuit by bottom surface pins 3. The test terminal 4 is provided on the upper surface of the MCM substrate, and the test probe 5 is in contact therewith. MC
M has been developed especially for the purpose of miniaturization, and it is important to suppress the number of pins on the bottom surface pins 3 as much as possible, so that the wirings of the internal chips are often not drawn to the outer peripheral portion. In order to improve the testability of the MCM, it is important to be able to perform a test with a single chip, so providing the test terminals 4 on the upper surface of the MCM board 6 is very important for achieving both miniaturization and testability. It turns out to be advantageous.

As described above, according to this embodiment, since the test terminals 4 are arranged on the upper surface of the MCM board 6, the MCM
The board 6 can be downsized and the circuit board 1 can also be downsized.

In the second embodiment, the circuit board 1 is described, but the MCM alone is tested (for example, shipping inspection).
Also in the above, it goes without saying that there is an effect that the testing of the internal chip 7 can be sufficiently performed by the testing terminal 4.

[0016]

As described above, according to the present invention, by providing the test terminals on the upper surfaces of the package and the MCM board, it is possible to realize an integrated circuit and a circuit board which are small in size and have high testability.

[Brief description of drawings]

FIG. 1 is a sectional view of an integrated circuit according to a first embodiment of the present invention.

FIG. 2 illustrates an integrated circuit (MC according to a second embodiment of the present invention.
Cross section of M)

[Explanation of symbols]

 1 Circuit Board 2 Package 3 Bottom Pin 4 Test Terminal 5 Test Probe 6 MCM Board 7 Chip 8 Resin Mold

Claims (1)

[Claims] 1. An integrated circuit package or substrate having one or a plurality of circuit elements and a circuit chip mounted thereon, and having terminals for connecting to an external circuit on a bottom surface portion of the integrated circuit package or substrate. An integrated circuit with terminals for arranging on the top.