JPH0252262A - Electric inspecting method for multi-chip package - Google Patents

Electric inspecting method for multi-chip package

Info

Publication number
JPH0252262A
JPH0252262A JP63203421A JP20342188A JPH0252262A JP H0252262 A JPH0252262 A JP H0252262A JP 63203421 A JP63203421 A JP 63203421A JP 20342188 A JP20342188 A JP 20342188A JP H0252262 A JPH0252262 A JP H0252262A
Authority
JP
Japan
Prior art keywords
electrodes
chip components
chip
input
dedicated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63203421A
Other languages
Japanese (ja)
Inventor
Minoru Futai
二井 稔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP63203421A priority Critical patent/JPH0252262A/en
Publication of JPH0252262A publication Critical patent/JPH0252262A/en
Pending legal-status Critical Current

Links

Landscapes

  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To take a measurement in a short time inspection at low cost by inspecting individual chip components including mounted dedicated LSIs through exposed electrodes and input/output leads connected electrically to the electrodes of the respective chips. CONSTITUTION:A cap 2 seals the IC chip components mounted and packaged on a specific surface of an insulating substrate 1. Then the input/output lead terminals and exposed electrodes 4 are connected electrically to the electrodes of the IC chip components. When electric connections among the electrodes of the IC chip components and of the input/output terminals are inspected, the electric inspection of the individual IC chip components except the dedicated LSIs is performed by inputting and outputting electric signals which are controlled by a specific test program through the electrodes 4 and terminals 3. Then the electric inspection of the individual dedicated LSI elements is carried out similarly by inputting and outputting electric signals which are controlled by test programs for the time of the manufacturing of the LSI elements and the time of design specifications.

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明はマルチチップパッケージの電気検査方法に係り
、特に専用LSI素子をチップ部品として搭載封有して
成るマルチチップパッケージの電気的機能や電気的接続
を検査する方法に関する。
[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to an electrical inspection method for a multi-chip package, and particularly to a method for electrically inspecting a multi-chip package in which a dedicated LSI element is mounted and sealed as a chip component. Concerns methods for testing electrical function and electrical connections.

(従来の技術) 電気回路乃至電気部品の小形化及び高性能化を目的とし
て、専用LSI素子を含む複数個のICチップ部品を搭
載、封有して成るマルチチップパッケージが開発されて
いる。即ち電極相互及び電極と入出カソード端子とを電
気的に接続した状態で超LSI素子を含むICチップ部
品を絶縁基板の所定面に搭載乃至実装し、これらICチ
ップ部品を例えばキャップで覆うように封有するととも
に前記搭載封有せしめたICチップ部品の電極と電気的
に接続する露出電極を前記絶縁基板の裏面に配設した構
造のマルチチップパッケージが開発されている。しかし
て前記マルチチップパッケージについては、マルチチッ
プパッケージの人カソードを介して所定の信号パターン
を入力し、出カソードを介して出カバターンを検査する
ことによって所要の電気検査を行っている。
(Prior Art) For the purpose of downsizing and improving the performance of electrical circuits and electrical components, multi-chip packages have been developed in which a plurality of IC chip components including dedicated LSI elements are mounted and sealed. That is, IC chip components including a VLSI element are mounted or mounted on a predetermined surface of an insulating substrate with the electrodes electrically connected to each other and the electrodes and input/output cathode terminals, and these IC chip components are sealed by covering them with, for example, a cap. A multi-chip package has been developed in which exposed electrodes are disposed on the back surface of the insulating substrate and are electrically connected to the electrodes of the mounted and sealed IC chip components. As for the multi-chip package, required electrical tests are carried out by inputting a predetermined signal pattern through the cathode of the multi-chip package and inspecting the output cover pattern through the output cathode.

(発明が解決しようとする課題) ところで最近の半導体技術の進歩に伴い高集積化された
LSIが開発されて来ており、専用LSI素子を搭載し
たマルチチップパッケージにおいてはその回路規模も膨
大化して来ている一方、マルチチップパッケージの信頼
性を確保すべく十分に不良を検出しうる電気検査方法が
要望されている。つまり上記入カソードを介して所定の
信号パターンを入力し、出カソードを介して出力される
出カバターンから電気検査を行う方法に準拠した場合に
は信号パターンが長大且つ複雑なものとなるためその信
号パターンの開発選択に多くの時間と労力を要するため
マルチチップパッケージの製品開発の遅延、開発費の増
大を招来しているのが現状である。
(Problem to be solved by the invention) By the way, with recent advances in semiconductor technology, highly integrated LSIs have been developed, and the circuit scale of multi-chip packages equipped with dedicated LSI elements has become enormous. At the same time, there is a need for an electrical inspection method that can sufficiently detect defects in order to ensure the reliability of multi-chip packages. In other words, if a predetermined signal pattern is input through the input cathode and electrical inspection is performed from the output cover pattern output through the output cathode, the signal pattern will be long and complicated, so the signal The current situation is that development and selection of patterns requires a lot of time and effort, resulting in delays in product development of multi-chip packages and increased development costs.

[発明の構成コ (課題を解決するための手段) 本発明方法によれば前記マルチチップパッケージの電気
検査を行うに当り、搭載されている専用LSIを含む各
チップ部品の電極と電気的に接続された露出電極及び入
出カソードを介してチップ部品例々の電気検査を行うと
ともに電極相互及び入出カソードの電気的接続の検査を
行うに当り専用超LSI素子についてはその専用LSI
素子開発時のソフトウェア(テストプログラム、接続デ
ータなど)を適用することを骨子とする。
[Structure of the Invention (Means for Solving the Problems) According to the method of the present invention, when electrically inspecting the multi-chip package, it is possible to electrically connect the electrodes of each chip component including the dedicated LSI mounted thereon. In order to conduct electrical inspections of each chip component through exposed electrodes and input/output cathodes, and to inspect the electrical connections between electrodes and input/output cathodes, the dedicated LSI
The main point is to apply software (test programs, connection data, etc.) during device development.

(作用) 専用LSI素子を含む複数個のICチップ部品を搭載乃
至実装して成る上記構成のマルチチップパッケージにつ
いて露出電極を介して各ICチップ部品の電気検査、電
気的接続の検査を行うに当り、特に専用LSI素子の電
気検査にはその専用LSI素子の初期データを適用する
。つまり専用LSI素子について新規なテストプログラ
ム乃至ソフトの開発を要せずに所要の電気検査を簡略化
して行う。
(Function) When electrically inspecting each IC chip component and inspecting the electrical connection through exposed electrodes for a multi-chip package having the above configuration in which a plurality of IC chip components including a dedicated LSI element are mounted or mounted. In particular, the initial data of the dedicated LSI element is applied to the electrical inspection of the dedicated LSI element. In other words, necessary electrical inspections for dedicated LSI devices can be performed simply without requiring the development of new test programs or software.

(実施例) 以下本発明の詳細な説明する。先ず専用LSI素子を含
む複数個のICチップ部品を搭載乃至実装して成る例え
ば第1図乃至第3図に示すようなマルチチップパッケー
ジを用意する。第1図は上面図、第2図は側面図、第3
図は下面図であり、1は絶縁基板、2はキャップで前記
絶縁基板1の所定面に搭載、実装されたICチップ部品
を封有する役割を果している。また3は前記ICチップ
部品の電極にそれぞれ電気的に接続した人出カリード端
子、4は同じ<ICチップ部品の電極にそれぞれ電気的
に接続する露出電極である。次いて前記マルチチップパ
ッケージについてICチップ部品の電極相互の電気的接
続の検査及び人出カリードの電気的接続の検査を行う一
方、前記ICチップ部品中、専用LSI素子以外のIC
チップ部品個々について前記露出電極4及び入出力リド
端子3を介して所定の電気検査を行う。つまり所定のテ
ストプログラムによって制御された電気信号(信号パタ
ーン)を入出力にそれらICチップ部品個々(専用LS
I素子を除く)の電気検査を行う。しかる後残りのIC
チップ部品即ち専用LSI素子個々について、各専用L
SI素子自体の製品化時点乃至設計仕様時点におけるテ
ストプログラムによって制御された電気信号(信号パタ
ーン)をそれぞれ入出力して、専用LSI素子個々の電
気検査を行う。かくして前記構成のマルチチップパッケ
ージについて所要の電気検査が行われる。
(Example) The present invention will be described in detail below. First, a multi-chip package such as the one shown in FIGS. 1 to 3 is prepared, in which a plurality of IC chip components including dedicated LSI elements are mounted or mounted. Figure 1 is a top view, Figure 2 is a side view, and Figure 3 is a top view.
The figure is a bottom view, and 1 is an insulating substrate, and 2 is a cap, which serves to seal the IC chip components mounted and mounted on a predetermined surface of the insulating substrate 1. Further, 3 is a lead terminal electrically connected to the electrodes of the IC chip component, and 4 is an exposed electrode electrically connected to the electrodes of the same IC chip component. Next, the multi-chip package is inspected for electrical connections between the electrodes of the IC chip components and electrical connections between the lead leads.
A predetermined electrical test is performed on each chip component via the exposed electrode 4 and the input/output lead terminal 3. In other words, each IC chip component (dedicated LS
(excluding I elements). After that, the remaining IC
For each chip component, that is, a dedicated LSI element, each dedicated L
Electrical inspection of each dedicated LSI element is performed by inputting and outputting electrical signals (signal patterns) controlled by a test program at the time of product production or design specification of the SI element itself. In this way, the required electrical inspection is performed on the multi-chip package having the above configuration.

なお上記においては専用LSI素子を含むICチップ部
品複数個を搭載、実装して成るマルチチップパッケージ
の電気検査に当って電極相互及び入出カソードの接続系
の電気検査、専用LSI素子の電気検査の順で所要の電
気検査を行ったが検査順序は前記順序に限定されず適宜
変更してもよい。
In the above, when electrically inspecting a multi-chip package made up of multiple IC chip components including dedicated LSI elements mounted and mounted, the electrical inspection of the connection between electrodes and input and output cathodes, and the electrical inspection of the dedicated LSI element are performed in the following order: Although the necessary electrical tests were carried out in the above steps, the test order is not limited to the above order and may be changed as appropriate.

[発明の効果] 上記の如く本発明に係るマルチチップパツケジの電気検
査方法によれば、マルチチップパッケージの種別毎に、
新たにテストプログラム乃至ソフトなどの開発を要せず
に容易に所要の電気検査を行いうる。つまり専用LSI
素子を含むICチップ部品を搭載乃至実装したマルチチ
ップパッケージの電気検査乃至特性評価において、一般
ICチップ部品については開発製品化時(初期データ)
のテストプログラムを適用するため上記電気検査は低コ
ストで行いうるし、また検査時間も全体として短縮でき
る。このことは特注のマルチチップパッケージの開発、
製品化の期間短縮及び開発費なとの低減化に寄与し、実
用上多くの利点をもたらすものと言える。
[Effects of the Invention] As described above, according to the method for electrically inspecting multi-chip packages according to the present invention, for each type of multi-chip package,
Necessary electrical inspections can be easily performed without the need to develop new test programs or software. In other words, a dedicated LSI
In electrical inspection and characteristic evaluation of multi-chip packages mounted with IC chip parts including elements, general IC chip parts are tested at the time of development and commercialization (initial data).
Since the above test program is applied, the above-mentioned electrical inspection can be performed at low cost, and the inspection time can be shortened overall. This has led to the development of custom multi-chip packages,
It can be said that it contributes to shortening the period of commercialization and reducing development costs, and brings many practical advantages.

【図面の簡単な説明】[Brief explanation of the drawing]

添附図は本発明に係る電気検査方法を適用したマルチチ
ップパッケージの構成例を示したもので第1図は上面図
、第2図は側面図、第3図は下面図である。 1・・・絶縁基板 2・・・キャップ 3・・・入出カソード端子 4・・・露出電極
The accompanying drawings show an example of the structure of a multi-chip package to which the electrical inspection method according to the present invention is applied, in which FIG. 1 is a top view, FIG. 2 is a side view, and FIG. 3 is a bottom view. 1... Insulating board 2... Cap 3... Input/output cathode terminal 4... Exposed electrode

Claims (1)

【特許請求の範囲】[Claims] 絶縁基板の所定面に各電極が相互に電気的に接続される
一方、入出カソード端子に電気的に接続された専用LS
I素子を含むチップ部品が搭載封有され且つ前記チップ
部品の電極と電気的に接続された露出電極を備えて成る
マルチチップパッケージの電気検査方法であって、前記
露出電極及び入出力リードを介して前記チップ部品個々
の電気検査、電極相互の電気的接続検査及び入出力リー
ドの電気的接続検査を行うに当り、前記専用LSI素子
の電気検査にはその専用LSI素子開発時のソフトウェ
アを適用して行うことを特徴とするマルチチップパッケ
ージの電気検査方法。
The electrodes are electrically connected to each other on a predetermined surface of the insulating substrate, while the dedicated LS is electrically connected to the input and output cathode terminals.
A method for electrically inspecting a multi-chip package on which a chip component including an I element is mounted and sealed and comprising an exposed electrode electrically connected to an electrode of the chip component, the method comprising: When conducting the electrical inspection of each chip component, the electrical connection between electrodes, and the electrical connection of input/output leads, the software used when developing the dedicated LSI element is applied to the electrical inspection of the dedicated LSI element. A method for electrically inspecting a multi-chip package.
JP63203421A 1988-08-16 1988-08-16 Electric inspecting method for multi-chip package Pending JPH0252262A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63203421A JPH0252262A (en) 1988-08-16 1988-08-16 Electric inspecting method for multi-chip package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63203421A JPH0252262A (en) 1988-08-16 1988-08-16 Electric inspecting method for multi-chip package

Publications (1)

Publication Number Publication Date
JPH0252262A true JPH0252262A (en) 1990-02-21

Family

ID=16473798

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63203421A Pending JPH0252262A (en) 1988-08-16 1988-08-16 Electric inspecting method for multi-chip package

Country Status (1)

Country Link
JP (1) JPH0252262A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5754410A (en) * 1996-09-11 1998-05-19 International Business Machines Corporation Multi-chip module with accessible test pads
US6081024A (en) * 1996-07-04 2000-06-27 Nec Corporation TAB tape semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6081024A (en) * 1996-07-04 2000-06-27 Nec Corporation TAB tape semiconductor device
US5754410A (en) * 1996-09-11 1998-05-19 International Business Machines Corporation Multi-chip module with accessible test pads
US6094056A (en) * 1996-09-11 2000-07-25 International Business Machines Corporation Multi-chip module with accessible test pads and test fixture

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