JPH10104301A - Method for inspecting package substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform an efficient and reliable electrical inspection quickly. SOLUTION: The insulation inspection of the first connection state formed among a first pad 2, an inner-layer pattern 5, and a second pad 3 and the second connection state formed among the first pad 2, a net-shaped inner-layer pattern 5A, and a second pad 3 is performed while a probe is in contact with the second pad 3 and at the same time the conduction inspection of the first and second connection states is performed while the probe is in contact with the second pad 3 and a conductive rubber sheet is in contact with the entire first pad 2. Further, the conduction inspection and insulation inspection of a third connection state formed between each first pad 2 and the inner-layer pattern 5 is performed while a flying probe is in contact with the first pad 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to, for example, a first pad for a flip chip on one surface and a second pad for a ball grid array (BGA) and a land grid array (LGA) on the other surface. The first pad and the second pad are related to an inspection method for performing an electrical inspection of a package substrate made of ceramic, resin, or the like, which is connected to each other through various patterns via an inner layer pattern. The present invention relates to a method of inspecting a package substrate, which can efficiently perform an electrical inspection in a short time in consideration of various connection modes existing therebetween.

[0002]

2. Description of the Related Art Conventionally, a flip-chip pad (referred to as a first pad for convenience) is provided on one surface, and a BGA or a pad is provided on the other surface.
In a package substrate provided with an LGA pad (referred to as a second pad for convenience), it is general that the first pad and the second pad are in one-to-one correspondence via an inner layer pattern. . In such a package substrate, the inner layer pattern does not have a net structure, and therefore, the electrical inspection of each of the first pad, the second pad, and the inner layer pattern can be performed relatively easily. Here, an electrical inspection method for the first pad, the second pad, and the inner layer pattern in the conventional package substrate will be described with reference to FIGS. FIG. 5 is an explanatory view for explaining an insulation test of a connection state in which a first pad and a second pad are connected in a one-to-one correspondence via an inner layer pattern in a conventional package substrate, and FIG. FIG. 5 is an explanatory diagram for describing a conduction test of a connection state in the package substrate shown in FIG.

FIGS. 5 and 6 show a package substrate 10.
Reference numeral 0 denotes a first pad 101 for mounting a flip chip on one surface (the lower surface in FIGS. 5 and 6), and a second pad for a BGA or LGA on the other surface (the upper surface in FIGS. 5 and 6). 1
02 is formed. Further, each of the first pads 101 and the second pads 102 are in a one-to-one relationship via the inner layer pattern 103.
Connected to correspond to

In order to conduct an electrical inspection of the package substrate 100 as described above, first, a probe 104 of an inspection device is brought into contact with each of the second pads 102, and a predetermined voltage is applied to the probe 104 so that the second pads 102 and Inner layer pattern 1
03 and the first pad 101 are subjected to an insulation test. At this time, the insulation test is performed by measuring the resistance with each probe 104. Next, as described above, the probe 10
4 in contact with each second pad 102,
A conductive rubber sheet 105 is brought into contact with the entirety of the pad 101, a predetermined voltage is applied to the probe 104, and the second pad 1
02, a conduction test between the inner layer pattern 103 and the first pad 101 is performed. According to the inspection method as described above, since the structure of the package substrate 100 is simple, the first pad 10 can be quickly manufactured using an inexpensive inspection device and jig.
1. Electrical inspection between the inner layer pattern 103 and the second pad 102 can be performed.

[0005]

However, in recent years, multi-chip substrates have become the mainstream package substrates. In such a multi-chip substrate, the first pad for flip-chip mounting is provided on one surface, and the BGA or LGA is provided on the other surface.
A second pad for the GA is formed, and the first pad and the second pad are connected to each other via an inner layer pattern having a complicatedly branched and net structure. There are a plurality of types of connection states (aspects) between the pad, the second pad, and the inner layer pattern.

Therefore, the following problems exist when conducting an electrical inspection of the first pad, the second pad, and the inner layer pattern in the multi-chip substrate having the above-described configuration. That is, in the multi-chip substrate, the fineness of each of the first pad and the second pad is further promoted. In particular, the first pad, which is a flip-chip mounting pad, is formed at a narrow pitch, and the pad diameter is small. Is also small. Accordingly, the positional accuracy of the inspection jig in the inspection device is required, and therefore, the inspection jig becomes expensive.

For example, as described above, when an inspection is performed using a probe and a conductive rubber sheet,
Strict positional accuracy is required for the probe and the conductive rubber sheet, and strict accuracy is also required for the inspection jig and the inspection device. The diameter of the first pad is 10
The limit is 0 μm and the pitch is about 0.2 mm. Therefore, an inspection jig that can cope with such a limit becomes considerably expensive and has low durability.

In order to cope with the limit of the positional accuracy of the probe or the conductive rubber sheet as described above, it is conceivable to employ a so-called flying probe method. Although the inspection apparatus employing the flying probe method is expensive, it has a good position accuracy of the probe and can correspond to the first pad (pad diameter: 50 μm, pitch: 0.15 mm) having a considerably fine pitch. Also,
There is no need for expensive inspection jigs. However, in the flying probe method, since the inspection is performed using only a few flying probes, an inspection time is required. Therefore, an inspection tact for inspecting a large number of substrates becomes a problem. In addition, in the capacitor capacitance measuring method using the flying probe method, when the pattern is very short, the measured capacitance value is small even if the pattern to be connected is broken, and it is highly possible that the measured capacitance value becomes lower than the capacitance measurement limit. Therefore, an inspection jig that can cope with such a limit becomes considerably expensive.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and has a first pad for flip-chip mounting on a package substrate and a second pad for BGA or LGA.
In consideration of various connection states between the first pad and the second pad based on the inner layer pattern derived from the net structure and existing between the pads, even when using a low-cost inspection device or inspection jig, An object of the present invention is to provide a method of inspecting a package substrate, which can efficiently perform an electrical inspection in a short time.

[0010]

According to a first aspect of the present invention, there is provided an inspection method for performing an electrical inspection of a package substrate having a plurality of first pads and a plurality of second pads formed thereon. Outputting a detection signal to the probe in a state where the fixture probe is in contact with the second pad, and performing an inspection based on the detection signal detected via the probe; and applying the fixture probe to the second pad. A step of outputting a detection signal to the probe in a state where the first pads are in contact with each other and short-circuiting the first pads, and performing an inspection based on the detection signal detected via the probe; In each of the above-described steps, a capacitor capacitance generated between the pattern and the electrode plate is calculated for each pattern that is not an inspection target, and the calculated capacitor is calculated. When the calculated value of the amount is larger than the predetermined threshold value, a detection signal is output to the flying probe in a state where the flying probe is in contact with the first pad, and based on the capacitance value of the capacitor detected via the electrode plate. A capacitance test is performed. If the calculated value of the calculated capacitor capacitance is smaller than a predetermined threshold, a detection signal is output to the flying probe in a state where the flying probe is in contact with the first pad, and the signal is output via the flying probe. And a step of performing a resistance test based on the detected resistance value. In the method for inspecting a package substrate according to claim 1 having the above-described configuration, a complicated inspection of a pattern derived from a net structure can be accurately and quickly performed by sequentially performing three stages of inspection processes. .

Particularly, in the inspection method according to the first aspect, when the inspection is performed in the order of the described steps, the inspection is performed in order from the first step to a coarse inspection and then to a dense inspection. When a conduction failure or an insulation failure is detected in a test step performed earlier in the test step, a defective package substrate can be selected without performing the next test step. This maintains high efficiency in selecting non-defective / non-defective package substrates, particularly when performing an electrical inspection of the package substrate, particularly since the inspection process using a flying probe takes the most time and is the rate-determining stage. Important above. In addition, the first two inspection steps of the three inspection steps are:
Inspection can be performed by using an inspection device and an inspection jig having relatively low positional accuracy.In addition, since the inspection using a flying probe can be performed only in the final inspection process, an inspection device with a low cost can be used. Even when an inspection jig is used, an electrical inspection can be efficiently performed in a short time. Furthermore, in the final inspection, the capacitor capacitance is calculated for each pattern that is not the inspection target in the previous two inspections, and when the calculated value is larger than a predetermined threshold, the capacitance inspection is performed. When the value is smaller than the predetermined threshold value, the resistance test is performed. Therefore, even when the pattern is very short, the reliability of the test can be remarkably improved.

According to a second aspect of the present invention, in the inspection method of the first aspect, the first pad is a pad for mounting a semiconductor chip, and the second pad is a ball grid array or a land grid. It is characterized in that it is an array pad. As described above, when the second pad is a pad for a ball grid array or a land grid array, these pads have a relatively large diameter, and positional accuracy is not so required. And the first two-step inspection process can be easily performed by contacting the first pad. When the first pad is a pad for mounting a semiconductor chip, the first pad is formed more finely. The last inspection step is performed by a flying probe that can be used.

Furthermore, a third aspect of the present invention is directed to the method of inspecting a package substrate, wherein the predetermined threshold value is 1 pF. As described above, when the threshold value is 1 pF, a relatively inexpensive capacitor capacitance inspection device can perform a highly reliable and high-resolution capacitance inspection with high reproducibility of inspection results. Also,
In the future, if a more inexpensive and higher-capacitance capacitance measuring device is developed, the predetermined threshold can be changed to a value smaller than 1 pF.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method for inspecting a package substrate according to the present invention will be described in detail based on an embodiment embodying the present invention with reference to the drawings. First, a configuration of a package substrate to be subjected to an electrical inspection will be described with reference to FIG. FIG. 1 is a partial cross-sectional view schematically showing a package substrate. In FIG. 1, a package substrate 1
Is a build-up multilayer wiring board in which wiring patterns are formed by a so-called full additive method over multiple layers (in FIG. 1, 10 layers). A first pad 2 for a plurality of flip chips is formed on one surface (the upper surface in FIG. 1) of the package substrate 1, and each first pad 2 is formed by a photo via. In the present embodiment, the first pad 2 has a diameter of 100 μm, a pitch of 0.25 mm, and a diameter of 150 μm.
There are zero. For example, after the first pad 2 is supplied with solder via a solder supply device (there is also a connection method using a conductive resin) or the like, the first pad 2 is connected to the connection terminal of the flip chip by solder.

Further, the other surface of the package substrate 1 (in FIG. 1,
A plurality of second pads 3 for LGA are formed on the lower surface), and are constituted by photovias like the first pad 2. In the present embodiment, the second pad 3 has a diameter of 600
There are provided 1,000 pieces with a pitch of 1.25 mm and μm. For example, after the solder is supplied to each second pad 3 via a solder supply device (may be attached by a socket) or the like, the second pad 3 is mounted on the motherboard by soldering.

The first pad 2 and the second pad 3 are basically connected via an inner layer pattern 5 composed of a photo via formed in each interlayer insulating layer 4 of the package substrate 1. Here, a connection mode among the first pads 2, the second pads 3, and the inner layer pattern 5 will be described.
A predetermined number of the first pads 2 (800 in this embodiment)
The first pads 2 are connected to the second pads 3 via the inner layer pattern 5 so as to correspond one-to-one. This connection state is referred to as a first connection state for convenience. For example, in FIG.
Among the first pads 2, the A pad (the first pad 2 at the upper left position in FIG. 1) is connected to the F pad (the lower left position at the lower left position in FIG. 1) of the second pad 3 through the inner layer pattern 5. 2), and this connection state corresponds to a first connection state.

Of the first pads 2, a predetermined number (600 in the present embodiment) of the first pads 2 are selectively provided via the inner layer pattern 5A formed in a net shape.
It is connected to the. This connection state is referred to as a second connection state for convenience. For example, in FIG. 1, among the first pads 2, a B pad (first pad 2 from the left on the upper surface in FIG. 1) and a C pad (third first pad from the left on the upper surface in FIG. 1) 2) is connected to the G pad (the second pad 3 on the lower surface in FIG. 1 from the left) of the second pads 3 via the net-shaped inner layer pattern 5A. This corresponds to two connection states.

Further, among the first pads 2, a specific 100 first pads 2 are mutually connected via an inner layer pattern 5. This connection state is referred to as a third connection state for convenience. For example, among the first pads 2 in FIG. 1, a D pad (the fourth first pad 2 from the left on the upper surface in FIG. 1) and an E pad (the fifth first pad from the left on the upper surface in FIG. 1) 2)
They are connected to each other via the inner layer pattern 5, and this connection state corresponds to a third connection state.

Next, an electrical inspection method for the package substrate 1 configured as described above will be described with reference to FIGS. Here, FIG. 2 is a partial cross-sectional view of the package substrate schematically showing a state where an insulation test is performed in the first connection state and the second connection state, and FIG. 3 is a continuity test in the first connection state and the second connection state. And FIG. 4 is a partial cross-sectional view of the package substrate schematically showing a state in which a continuity test and an insulation test in a third connection state are being performed. Although FIGS. 2 and 3 show only the first connection state, the second connection state is the same as that in FIG. The electrical inspection of the package substrate 1 includes first an insulation inspection in a first connection state and a second connection state, and then a continuity inspection in a first connection state and a second connection state.
Then, as a final stage, a continuity test and an insulation test of the third connection state are performed.

In order to conduct an electrical inspection of the package substrate 1, first, as shown in FIG. 2, the package substrate 1 is set on an inspection device, and each probe 6 provided on an inspection jig (fixture jig) is connected to the inspection device. It comes into contact with each second pad 3. still,
FIG. 2 shows a state where the probe 6 is in contact with the inner pad F of the second pad 3. While the probe 6 is in contact with the second pad 3, a predetermined voltage is applied to each probe 6, and a resistance value is measured via each probe 6 and compared with the non-defective sampled data to determine the first connection state and Second
Conduct an insulation test on the connection. Incidentally, in this test, only the probe 6 is in contact with each second pad 3. Therefore, the first connection state to the second pad 3, the inner layer pattern 5, and the first pad 2 and the second connection state to the second pad 3, the inner layer pattern 5A, and the first pad 2 are in a good insulation state. When no short circuit occurred, it was found that the insulation matched with the conforming data of the non-defective product, and that the short circuit occurred due to insulation failure in the first connection state or the second connection state. In FIG. 5, it is found that the insulation does not match the non-defective data (the number of nets is increased) and the insulation is poor. Note that a continuity test of the pattern connected by the second pads 3 is also performed at the same time. Also, a leak test is performed simultaneously by the same method. The first inspection step is completed in about 10 seconds.

Next, as shown in FIG. 3, a conductive rubber sheet is applied to the silicon resin sheet 8 over the entire first pad 2 in a state where the probe 6 is in contact with each second pad 3 as described above. After pressing with the bonded sheets, a predetermined voltage is applied to each probe 6, the resistance value is measured, and the continuity test of the first connection state and the second connection state is performed by comparing with the non-defective data. Incidentally, in this test, each first pad 2 is short-circuited via the conductive rubber sheet 7. Therefore, the second pad 3, the inner layer pattern 5, the first connection state reaching the first pad 2, the second pad 3,
When the second connection state to the inner layer pattern 5A and the first pad 2 is in a good conduction state and no open occurs, the non-defective data and the number of nets match, indicating that the conduction is good. If an open state occurs due to a conduction failure in the first connection state or the second connection state, it does not match the non-defective data, indicating that the conduction is defective. In addition, the insulation and continuity inspection of the pattern in which the second pad 3 is not connected to the first pad 2 is also performed at the same time. The second inspection step is completed in about 10 seconds.

In the above two inspection steps, if an insulation failure or conduction failure in the first connection state or the second connection state is detected, it can be determined that the package substrate 1 is defective, so that the final It is possible to shift to the inspection of the next package substrate 1 without performing the inspection step. As described above, by selecting defective products in advance through the two inspection processes performed earlier, the number of package substrates 1 to be inspected is reduced while eliminating defective products at an early stage, and the package substrates are efficiently reduced. One test can be performed.

In the two inspection steps, the first connection state and the second connection state of the package substrate 1 may be defective in insulation.
If no continuity failure is detected, the process proceeds to the next final inspection step using a flying probe. This inspection step is a step of performing a continuity inspection / insulation inspection of a third connection state which is not an inspection target in each of the two-step inspection steps. Next, the continuity test / insulation test in the third connection state will be described in detail with reference to FIG. First, the area of each pattern in the third connection state is calculated by multiplying the length and width of the pattern from the printed circuit board design information of the first pads 2 (100 in this embodiment) and the inner layer pattern 5 in the third connection state. . Then, the electrode plate 1 is placed on the insulator 15 on the second pad 3 surface side.
0 (a copper plate or the like) is placed in contact with each other, a capacitor capacitance (CAPACITANCE) between each pattern in the third connection state and the electrode plate 10 is calculated, and the calculated capacitor capacitance data is made to correspond to each pattern. Input to the flying probe checker 14. Next, as shown in FIG. 4, in a state where the electrode plate 10 is placed in contact with the insulator 15 on the second pad 3 surface side, the package substrate 1 is set on an inspection device provided with the flying probe 9, and While the pair of flying probes 9 are selectively in contact with the first pads 2, a continuity test and an insulation test are performed for each predetermined set of the first pads 2 in the third connection state connected via the inner layer pattern 5. . In the electrical inspection, the flying probe checker 14 determines whether or not the calculated capacitor capacitance is 1 pF or more based on the calculated capacitor capacitance data corresponding to the test pattern with which the flying probe 9 is selectively contacted. A predetermined voltage is applied to the flying probe 9 by 12 and the capacitance of the capacitor detected via the electrode plate 10 connected by soldering 11 (a method using a conductive adhesive is also used) is measured. Then, the continuity test and the insulation test between the first pads 2 are performed by comparing the measured value with the capacitor value of the normal package substrate, and the electrical test of the package substrate 1 is completed. In the electrical test, when the calculated capacitor capacitance corresponding to the test pattern with which the flying probe 9 is selectively contacted is less than 1 pF, the flying probe checker 14 controls the one of the flying probes by the resistance measuring unit 13. 9, a predetermined voltage is applied to the resistance value (RE) detected through the other flying probe 9.
SISTANCE). Then, the continuity test and the insulation test between the first pads 2 are performed by comparing the measured value with the resistance value of the normal package substrate, and the electrical test of the package substrate 1 is completed. Incidentally, the final inspection step of the third stage is completed in about one minute.

The time required for the three inspection steps is about 10 seconds for the first inspection step, about 10 seconds for the second inspection step, and about 1 minute for the third inspection step. Therefore, the total inspection time is about 1.5 minutes. Therefore, compared to the inspection time required when all the inspection steps are performed through the flying probe 9 is about 3 minutes,
The electrical inspection of the package substrate 1 can be performed in about half the inspection time. Further, the first-stage inspection process, the second-stage inspection process, and the third-stage inspection process can be performed in parallel with each other, and in such a case, the inspection time is further reduced. be able to.

As described above in detail, in the inspection method for the package substrate 1 according to the present embodiment, the first connection state formed between the first pad 2, the inner layer pattern 5, and the second pad 3, and the first pad 2, net-shaped inner layer pattern 5A,
The insulation test of the second connection state formed between the second pads 3 is performed through an inexpensive inspection jig in a state where the probe 6 is in contact with the second pad 3, and the first connection state and the second connection state are checked. For the continuity test of the connection state, the probe 6 is connected to the second pad 3.
Is performed through an inexpensive inspection jig in a state in which the conductive rubber sheet 7 is in contact with the first pad 2 and formed between the first pad 2 and the inner layer pattern 5. Since the continuity inspection / insulation inspection of the third connection state is performed by the flying probe 9, the inspection by the flying probe 9 requiring an inspection time is minimized, and the inspection is performed by using a low-cost inspection apparatus and an inspection jig. The electrical inspection of the package substrate 1 can be efficiently performed in a short time.
Note that the present invention is not limited to the above embodiment,
It goes without saying that various improvements and modifications can be made without departing from the spirit of the present invention.

For example, in the above embodiment, the probe is directly contacted with the pad to perform the inspection.
After the solder bump is formed on the pad, the probe may be brought into contact with the bump to perform the inspection. This is to prevent a crack from occurring in, for example, a photo via pad when the probe comes into contact with the pad. Further, it is because the reliability can be assured by performing the inspection using the probe in the final step (a state close to the shipping state). After forming the solder bump on the pad and flattening the solder bump,
An inspection is performed with the probe abutting the flattened solder bump. In addition, fixture insulation inspection, continuity inspection with fixture and conductive rubber, capacitor capacitance measurement inspection and resistance value measurement inspection with flying probe,
This can be performed even when the pads have different shapes (for example, Au-plated pads without solder bumps, pads with solder bumps formed, pads with solder bumps formed and flattened, etc.). The inspection order can be freely determined. In addition, the capacitor capacitance measurement inspection and the resistance value measurement inspection using the flying probe were selected based on whether or not the capacitor capacitance of the pattern in the third connection state calculated in advance was 1 pF or more. If the unit can be configured, the above-described inspection method may be selected based on a capacitor capacitance smaller than 1 pF.

[0027]

As described above, the method of inspecting a package substrate according to the present invention exists between the first pad for flip chip mounting and the second pad for BGA or LGA on the package substrate, and has a net structure. In consideration of various connection states between the first pad and the second pad based on the derived inner layer pattern, an electric test is efficiently performed in a short time even when a low-cost test device or test jig is used. It is possible to provide a method of inspecting a package substrate capable of performing the above. In addition, a multichip package (MCM) substrate as well as a single chip package can be efficiently inspected.

[Brief description of the drawings]

FIG. 1 is a partial cross-sectional view schematically showing a package substrate.

FIG. 2 is a partial cross-sectional view of the package substrate schematically showing a state where an insulation test is being performed in a first connection state and a second connection state.

FIG. 3 is a partial cross-sectional view of the package substrate schematically showing a state in which a continuity test is performed in a first connection state and a second connection state.

FIG. 4 is a partial cross-sectional view of the package substrate schematically showing a state in which a continuity test and an insulation test in a third connection state are being performed;

FIG. 5 is an explanatory diagram for explaining an insulation test of a connection state in which a first pad and a second pad are connected in a one-to-one correspondence via an inner layer pattern in a conventional package substrate.

FIG. 6 is an explanatory diagram for explaining a continuity test of a connection state in the package substrate shown in FIG. 5;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Package board 2 1st pad 3 2nd pad 4 Interlayer insulating layer 5 Inner layer pattern 5A Net-like inner layer pattern 6 Probe 7 Conductive rubber sheet 9 Flying probe 10 Electrode board 11 Soldering 12 Capacitance measuring part 13 Resistance measuring part 14 Flying Probe checker 15 Insulator

Claims (3)

[Claims] 1. An inspection method for performing an electrical inspection of a package substrate on which a plurality of first pads and a plurality of second pads are formed, wherein a detection signal is sent to a probe while a fixture probe is in contact with the second pad. And outputting a detection signal to the probe in a state where the fixture probe is brought into contact with the second pad and the first pads are short-circuited. Performing an inspection based on a detection signal detected via a probe; and, in a state where an electrode plate is provided on the second pad surface side, the pattern and the electrode plate for each pattern not to be inspected in each of the steps. Is calculated between the first pad and the calculated value of the calculated capacitor capacity is larger than a predetermined threshold value. A detection signal is output to the flying probe in a state where the flying probe is in contact with the flying probe, and a capacitance test is performed based on the capacitance value detected via the electrode plate. First if small
Outputting a detection signal to the flying probe in a state where the flying probe is in contact with the pad and performing a resistance test based on a resistance value detected via the flying probe. 2. The inspection of a package substrate according to claim 1, wherein the first pad is a pad for mounting a semiconductor chip, and the second pad is a pad for a ball grid array or a land grid array. Method. 3. The method according to claim 1, wherein the predetermined threshold is 1 pF.