九、發明說明： 【發明所屬之技術領域】 本發明係有關於-種測試裝置，特別儀有關於可放置 多個測試模組之多功能測試裝置。 【先前技術】 半導體製程中對晶片的測試分兩階段，第—是在晶圓 階段，其係在晶®尚未㈣為單—晶片前，先對晶圓上個 別晶片進行測試’以在封裝前能先檢查出電性不良的晶 片’避免不良之晶片被封裝而增加封裝成本。第二是晶片 封裝後之測試。通常在晶圓測試階段之測試係採用晶圓探 針卡，晶圓探測卡是由電路板及探測㈣組成，探測頭係 電性連接電路板’再由探測頭上所設置之探針與晶片接 觸’以測試晶片的電性功能，並將測得之資料經分析盥判 斷：挑選出不良品再另外進行晶圓修補或停止投入封裝及 後段測試成本’因此晶圓探針卡之仙…乍可提高晶片之 良率’亦可降低後段封測成本。 如第1圖所示，習知晶圓探測卡1〇〇係包含有一電路 板U0及-測試模組120，該測試模組係電性連接至 該電路板U0,該測試模組12〇係具有一基板121及複數 個探針122，該些探針122係設置於該基121之_表面 以接觸欲測試之一晶圓10上之複數個銲墊11，將測 式、”。果不合格之晶片挑出並以測試合格之晶片進行後續 子裝製程，再將封裝完成之封裝體送至封裝體測試治具， 如第2圖所不’習知封裝體測試治具200係包含有-電路 1344187 板㈣及一定位裝置220,該定位裝置22〇係具有複數個 第一銲墊221 '第二銲墊222與複數個容置槽 ，該些 第一薛塾221係電性連接該些第二銲墊222，嗲 疋位裝置 220係連接該電路板21〇且該電路板之複數個探針 係電性連接該定位裝置220之該些第一銲墊221，將封 完成之複數個封裝體20放置於該定位裝置22〇之垓此二 置槽223内，利用該些封裝體2〇之複數個銲球2ι接觸= 定位裝置220之該些第二連接墊222進行該些封褒體^ 之電性測試。 然而，由上述之敘述可知，t玄晶圓探測卡及該封襄體 測試治具所使用之電路板並不相同，因此其製造成本相對 增加容易’並且容易產生誤例如：通常晶圓探測卡所 使用之電路板係適用純頻㈣，封冑冑測試治具之電路 板係適用於高頻tfl號’故晶圓探測卡僅能對晶圓上之晶片 進行基本電性測試，而封裝體 性測試，當封裝體測試結果不合格時，無法判斷封裳體是 於封裝過冑中發生誤i而使封裝體測試不纟肖，或是晶圓 探測卡與封裝體㈣治具之電&板所測得之頻率規：不 同而使得電性故障之晶片未被挑出。 【發明内容】 本發明之主要目的係在於提佴一 ^ 種多功能測試裝 置’一晶圓測試模組係設置於一雷故 哥路基板之一第一測試 區，一封裝體測試模組係設置於該電 Λ电硌基板之一第二測試 區’由於該晶圓測試模組與該封裝體 衣艰剩自式楨組係設置於同 1344187 一電路基板’可避免該晶圓測試模組與該封裝體測試模組 設置於不同規格之電路基板而對一晶片與使用該晶片所 封裝形成之封裝體產生測s式結果之誤判，並且可節省：則令戈 裝置之製造成本。 依本發明之一種多功能測試裝置主要包含—電路基 板、一晶圓測試模組以及一封裝體測試模組，該電路基板 係具有一第一測試區與一第二測試區，該晶圓測試模組係 設置於該第一測試區，該晶圓測試模組係具有一基板及複 數個第一探針且該基板係電性連接該些第一探針，該封裝 體測試模組係設置於該第二測試區，該封裝體測試模組係 具有一承载器及複數個第二探針，該承載器係電性連接該 些第二探針。 【實施方式】 請參閱第3、4A及4B圖，依據本發明之一具體實施 例係揭示一種多功能測試裝置3〇〇，其係主要包含一電路 基板3 1 0、一晶圓測試模組32〇以及—封裝體測試模組 330,其中該電路基板310係為多層電路基板且層數較厚， "玄電路基板3 1 0係適用於承裁高頻訊號，使得該電路基板 310之線路規劃係可由傳統晶圓分類測試（Wafer s〇rt testing )所需之低頻訊號工作頻率升級至全功能測試 (FUlI-function testing)所需之高頻訊號工作頻率，例如 由兆赫（Megahertz, MHz )升級至千兆赫（Gigahertz， GHz)。如第3圖所示，該電路基板3丨〇係具有一第一測試 區3 11與一第二測試區3丨2，該第一測試區3丨1係用以設 8 置該晶圓測試模組320，該第二測試區3 1 2係用以設置該 封裝體測試模組3 3 0。如第4A圖所示，該晶圓測試模組 3 20係設置於該第一測試區3 11 ’該晶圓測試模組32〇係 為插拔式晶圓測試模組，因此該晶圓測試模組3 2 〇係可輕 易地拆卸或連接於該電路基板3 1 〇，該晶圓測試模組32〇 係具有一基板3 2 1及複數個第—探針3 2 2，該些第一探針 322係設置於該基板321之一表面32u且該基板321係電 性連接該些第一探針322,以測試晶片之基本電性功能或 完整電性功能’請參閱第5 _，將該晶圓測試模組32〇設 置於該電路基板310之該第—測試區311，使該晶圓測試 模組3 2 0之該第一按朴1 。 ^铼針322接觸一晶圓10之複數個銲IX. INSTRUCTIONS: TECHNICAL FIELD OF THE INVENTION The present invention relates to a test apparatus, and a special test apparatus for placing a plurality of test modules. [Prior Art] The wafer test in the semiconductor process is divided into two stages. The first is in the wafer stage, which is before the wafer (the fourth wafer is tested before the wafer). It is possible to check the defective chip first to avoid the defective wafer being packaged and increasing the packaging cost. The second is the test after wafer packaging. Usually, in the wafer testing stage, the wafer probe card is used. The wafer probe card is composed of a circuit board and a probe (4). The probe is electrically connected to the circuit board. Then, the probe provided on the probe is in contact with the wafer. 'To test the electrical function of the chip, and the measured data is analyzed and judged: picking out the defective product and then performing the wafer repair or stopping the input package and the post-test cost. Therefore, the wafer probe card is good... Increasing the yield of the wafer can also reduce the cost of the subsequent section. As shown in FIG. 1 , the conventional wafer probe card 1 includes a circuit board U0 and a test module 120. The test module is electrically connected to the circuit board U0, and the test module 12 has a The substrate 121 and the plurality of probes 122 are disposed on the surface of the substrate 121 to contact a plurality of pads 11 on one of the wafers 10 to be tested, and the measurement method is "". The wafer is picked out and tested by a qualified wafer for subsequent sub-assembly process, and then the packaged package is sent to the package test fixture. As shown in FIG. 2, the conventional package test fixture 200 includes a circuit. 1344187 a plate (4) and a positioning device 220, the positioning device 22 has a plurality of first pads 221 ′ a second pad 222 and a plurality of accommodating grooves, and the first 塾 221 is electrically connected to the first The second pad 222, the clamping device 220 is connected to the circuit board 21, and the plurality of probes of the circuit board are electrically connected to the first pads 221 of the positioning device 220, and the plurality of packages are sealed. The body 20 is placed in the two positioning slots 223 of the positioning device 22, and the package body 2 is used. The plurality of solder balls 2 ι contact = the second connection pads 222 of the positioning device 220 perform the electrical test of the sealing bodies. However, as described above, the t-wafer wafer detecting card and the sealing body test are The boards used in the fixtures are not the same, so the manufacturing cost is relatively easy to increase and easy to produce errors. For example, the board used in the wafer probe card is usually pure frequency (4), and the circuit board of the test fixture is sealed. It is suitable for high frequency tfl number. Therefore, the wafer probe card can only perform basic electrical test on the wafer on the wafer. However, when the package test result is unqualified, it cannot be judged that the package is in the package. If the error occurs in the sputum, the package test is not sloppy, or the frequency of the wafer probe card and the package (4) fixture's electric & board is different: the chip that is electrically faulty is not picked. SUMMARY OF THE INVENTION The main object of the present invention is to provide a multi-functional test device. A wafer test module is disposed in a first test area of a mine substrate, a package test mode. The group is set to the electricity The second test area of the Λ 硌 硌 ' 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于The test module is disposed on a circuit board of different specifications to produce a erroneous judgment on a wafer and a package formed by using the wafer, and can save: the manufacturing cost of the device is reduced. The functional test device mainly comprises a circuit substrate, a wafer test module and a package test module, wherein the circuit substrate has a first test area and a second test area, and the wafer test module is disposed on the In the first test area, the wafer test module has a substrate and a plurality of first probes, and the substrate is electrically connected to the first probes, and the package test module is disposed in the second test area. The package test module has a carrier and a plurality of second probes, and the carrier is electrically connected to the second probes. [Embodiment] Please refer to Figures 3, 4A and 4B. According to an embodiment of the present invention, a multi-function test device 3 is disclosed, which mainly comprises a circuit substrate 310 and a wafer test module. 32 〇 and the package test module 330, wherein the circuit substrate 310 is a multi-layer circuit substrate and the number of layers is thick, "Xuan circuit substrate 3 1 0 is suitable for carrying high-frequency signals, so that the circuit substrate 310 The line planning can be upgraded from the low frequency signal operating frequency required by the traditional wafer classification test (Wafer s〇rt testing) to the high frequency signal operating frequency required for FUlI-function testing, for example, by Megahertz (MHz). ) Upgrade to Gigahertz (GHz). As shown in FIG. 3, the circuit board 3 has a first test area 3 11 and a second test area 3丨2, and the first test area 3丨1 is used to set the wafer test. The module 320, the second test area 3 1 2 is used to set the package test module 300. As shown in FIG. 4A, the wafer test module 32 is disposed in the first test area 3 11 'the wafer test module 32 is a plug-in wafer test module, so the wafer test The module 3 2 can be easily detached or connected to the circuit substrate 3 1 , the wafer test module 32 has a substrate 3 2 1 and a plurality of first probes 3 2 2 , the first The probe 322 is disposed on a surface 32u of the substrate 321 and the substrate 321 is electrically connected to the first probes 322 to test the basic electrical function or the complete electrical function of the wafer. [Please refer to the fifth _, The wafer test module 32 is disposed on the first test area 311 of the circuit substrate 310 to make the first test of the wafer test module 3 0 0 . ^铼 pin 322 contacts a plurality of wafers of a wafer 10
塾11，由於在本實施例中，兮· φ μ w , y L A J T e哀電路基板3 1 0係為多層電路 基板且該電路基板3 1 0传且古古此 /z_ + 你具有咼頻工作頻率之線路，因此 可測得該晶圓1 〇上所有a η +甘丄丄 叮’曰曰片之基本或完整電性功能，其 係可將未通過完整電性功能之曰 ^ , 月b之日日片挑出，避免對測試不合 格之晶片進行封裝·，而浪眚χ V a , 貢不必要之成本。 請參閱第4B圖，該私·肚μ、， 封裝體測試模組330係設置於該 第二測試區3 12，較佳地，^ 5亥第一測試區3 11與該第二測 试區3 1 2之間係具有~間距η甘/ 门距d’其係防止該第一測試區311 之該晶圓測試模組3 2 0盥呤& /、4第二測試區312之該封裝塾11, in the present embodiment, 兮·φ μ w , y LAJT e sorrow circuit substrate 3 10 is a multi-layer circuit substrate and the circuit substrate 3 1 0 transmits and Gu Gu / z_ + you have a frequency operation The frequency line, so the basic or complete electrical function of all a η + 甘丄丄叮' 曰曰 on the wafer 1 can be measured, which can pass the complete electrical function. On the day of the film, the film was picked out to avoid packaging the unqualified wafers, and the cost was not necessary. Referring to FIG. 4B, the private test module 330 is disposed in the second test area 3 12 , preferably, the first test area 3 11 and the second test area 3 1 2 has a spacing η 甘 / gate distance d ′ which prevents the wafer test module 3 2 0 盥呤 & / 4 from the first test area 311 from the package
試模組330產生電性干擾， 、J 邊封裝體測試模組330係亦 插拔式封裝體測試模組，兮壯祕 ^ @封裝體測試模組330係具有一 承載器33 1及複數個第二控 ^ 探針332 ’該承載器331係且 複數個容置槽331a以容w # “有 令夏封農完成之封裝體，該歧第_ 設置於該些容置槽331a，該承載器-係電性 点^ —^針332 °請參閱第6 ®，將複數個封裝完 之封裝體2〇故置於該承載器331之該些容置槽仙The test module 330 generates electrical interference, and the J-side package test module 330 is also a plug-in package test module. The package test module 330 has a carrier 33 1 and a plurality of The second control probe 332 'the carrier 331 is a plurality of accommodating slots 331a for accommodating w # "there is a package that is completed by the summer seal, and the _ _ is disposed in the accommodating slots 331a, the load -Electrical point ^^^ pin 332 ° Please refer to the 6th ®, and place the plurality of packaged packages 2 on the carrier 331
内’將該些封裝體20之複數個輝球21接觸該承載器331 k 一第—拎針332，並使該封裝體測試模組gw與該電 路基板3 1 0電性連接以進行最終測試（Fina丨test )，由於 =晶圓測試模組320與該封裝體測試模組330係設置於同 電路基板，可避免該晶圓測試模組32〇與該封裝體測試 模組330設置於不同規格之電路基板時，㈣—晶片與使 用該晶片所封裝形成之封裝體產生測試結果之誤判例 如，最終測试中被檢驗出不合格之封裝體内所封裝之晶片 係為通過兀整電性測试之晶片，由於測試晶片之晶圓測試 模組與測試封裝體之封裝體測試模組皆設置於同一電路 基板’因蜱無規格不同之疑慮，由此可得知於未通過最終The plurality of glow balls 21 of the packages 20 are in contact with the carrier 331 k - the first pin 332, and the package test module gw is electrically connected to the circuit substrate 310 for final testing. (Fina丨test), since the wafer test module 320 and the package test module 330 are disposed on the same circuit substrate, the wafer test module 32 is prevented from being disposed differently from the package test module 330. When the circuit board of the specification is used, (4) - the wafer and the package formed by using the wafer are misjudged, for example, the wafer packaged in the package which is inspected and found to be unacceptable in the final test is by adjusting the electrical properties. The test wafer, since the wafer test module of the test wafer and the package test module of the test package are all disposed on the same circuit substrate, because of the doubt that there is no specification, it is known that the final test fails.
測試之封裝體係在封裝過程中發生問題而導致測試結果 不合格。 【圖式簡單說明】 第 1 圖：習知晶圓探針卡壓觸一晶圓之戴面示意 圖。 第 2 圖：習知封裝體置於一測試治具之載面示意 圖。 第 3 圖：依據本發明之一具體實施例，一種多功能 測試裝置之一電路基板之上視圖。 第4A至4B圖：依據本發明之一具體實施例，該多功能測 10 1344187 斌裝置之該電路基板上設置 測試模組與一封裝體測試模 意圖。 5 圖：依據本發明之一具體實施例， 體放置於該多功能測試裝置 測試模組之截面示意圖。 ^ 6 圖：依據本發明之一具體實施例， 試裝置之該晶圓測試模組測 戴面示意圖。 【主要元件符號說明】 有該一晶圓 組之截面示 複數個封裝 之該封裝體 該多功能測 試一晶圓之 10 晶圓 11 銲墊 20 封裝體 21 銲球 100 晶圓探測卡 110 電路板 120 測試模組 121 121a 表面 122 探針 200 封裝體測試治具 210 電路板 211 探針 220 221 第一銲墊 222 第二録塾 223 300 多功能測試裝置 310 電路基板 3 11 第一測試區 3 12 320 晶圓測試模組 321 基板 321a 322 第一探針 330 封裝體測試模組 331 承載器 33 la容置槽 332 d 第一測試區與第二 測試區之間距 基板 定位裝置 容置槽 第二測試區 表面 第二探針 11The tested package system had problems during the packaging process and the test results were unqualified. [Simple diagram of the diagram] Figure 1: Schematic diagram of a conventional wafer probe card that is pressed against a wafer. Figure 2: Schematic diagram of a conventional package placed on a test fixture. Figure 3 is a top plan view of a circuit substrate of a multi-function test apparatus in accordance with an embodiment of the present invention. 4A-4B: According to an embodiment of the present invention, a test module and a package test mode are disposed on the circuit substrate of the multi-function test 10 1344187 bin device. 5 is a cross-sectional view of a test module of the multi-function test device according to an embodiment of the present invention. ^6 Figure: Schematic diagram of the wafer test module of the test apparatus according to an embodiment of the present invention. [Main component symbol description] The package of the wafer group has a plurality of packages of the package. The multi-function test of a wafer 10 wafer 11 pad 20 package 21 solder ball 100 wafer probe card 110 circuit board 120 Test Module 121 121a Surface 122 Probe 200 Package Test Fixture 210 Circuit Board 211 Probe 220 221 First Pad 222 Second Recorder 223 300 Multi-Function Test Device 310 Circuit Board 3 11 First Test Area 3 12 320 wafer test module 321 substrate 321a 322 first probe 330 package test module 331 carrier 33 la accommodating slot 332 d between the first test area and the second test area from the substrate positioning device accommodating groove second test Zone surface second probe 11