CN103077913A - Lead-out device for aging bare chips and aging method - Google Patents
Lead-out device for aging bare chips and aging method Download PDFInfo
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- CN103077913A CN103077913A CN2013100224012A CN201310022401A CN103077913A CN 103077913 A CN103077913 A CN 103077913A CN 2013100224012 A CN2013100224012 A CN 2013100224012A CN 201310022401 A CN201310022401 A CN 201310022401A CN 103077913 A CN103077913 A CN 103077913A
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- bare chip
- ageing
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- bump substrate
- location hole
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Abstract
The invention discloses a lead-out device for aging bare chips and an aging method. The lead-out device comprises a convex point base plate and a positioning base plate, wherein the convex point base plate and the positioning base plate are matched, the convex point base plate is provided with convex points and externally connected pads which are connected through conduction bands, the convex points are arranged in the convex point base plate, and the externally connected pads are arranged on the periphery of the convex point base plate which is further provided with first fixing holes and first positioning holes. According to the lead-out device, through design of the convex point base plate and the positioning base plate, bonding points of the chips come into contact with the convex points and then led out of the externally connected pads through the conduction bands, and electrodes of the chips are led out, thereby aging and screening the bare chips and guaranteeing that pressure welding can be normally performed on the bare chips after being aged and screened.
Description
Technical field
The invention belongs to chip ageing triage techniques field; Relate to a kind of bare chip ageing with ejector and ageing method.
Background technology
In circuit (the particularly space flight electronic product) assembling process of high-quality level, need to before assembling, power up the ageing screening to components and parts, the device that is implied with internal flaw is screened out, reach the purpose that guarantees the circuit product quality.The method that existing chip ageing screening is adopted is to finish the ageing screening after the encapsulation, at present without the ripe method that can carry out to bare chip the ageing screening.
On the other hand, need in the art production process of hybrid integrated circuit assembling bare chip is carried out the quality screening, there is not at present effective method that bare chip is carried out the ageing screening, can only take the to sample method of assessment, with batch chip, finish aging test after encapsulating by proportionate sampling, batch quality of chip is assessed, can't be before assembling carry out the screening of 100% ageing to chip, cause hybrid integrated circuit etc. can't ensure take the quality of bare chip as the inside circuit chip on basis.
Summary of the invention
The problem that the present invention solves is to provide a kind of bare chip ageing with ejector and ageing method, by chip electrode is drawn, realizes the screening of bare chip ageing, guarantees can carry out normal pressure welding after the screening of bare chip ageing.
The present invention is achieved through the following technical solutions:
A kind of bare chip ageing ejector, comprise the bump substrate and the positioning baseplate that are complementary, bump substrate is provided with salient point and the external pad that is connected by conduction band, salient point is arranged on the inside of bump substrate, external pad be arranged on bump substrate around, also be provided with the first fixing hole and the first location hole on the bump substrate;
Positioning baseplate is provided with the chip putting hole, and the second fixing hole and the second location hole;
Behind bump substrate and positioning baseplate fastening, salient point contacts with the phase of solder joint of the interior bare chip of placing of chip putting hole, and the first location hole and the second location hole align, and the first fixing hole and the second fixing hole align.
Described salient point leads to external pad by conduction band according to treating that the solder joint of the bare chip of ageing lays respectively with all solder joints for the treatment of the bare chip of ageing.
Described bump substrate is flexible printed circuit, and conduction band and external pad are printed on the flexible printed circuit, and salient point is electroplated on flexible printed circuit.
Described salient point contacts one to one with the solder joint of bare chip.
Described positioning baseplate is epoxy resin base plate, and the first location hole aligns afterwards with the second location hole and is connected by bolt; Align positioning convex point accurately to contact with the solder joint of bare chip by the first location hole and the second location hole.
After the solder joint of described bare chip caused external pad outward, the contact resistance between bump substrate and the positioning baseplate was controlled to be:
The resistance sum maximum of two outer leads is 190～210m Ω, and minimum value is 120～135m Ω, and mean value is 150～165m Ω; The resistance mean value of single outer lead is 80～85m Ω.
Based on the ageing method of described bare chip ageing with ejector, may further comprise the steps:
1) bare chip is placed in the chip putting hole of positioning baseplate, after will working as that bump substrate and positioning baseplate are aimed at and fastening, makes chip welding spot and one by one corresponding contact of salient point; After bump substrate and positioning baseplate is fixing, in the socket in the burn-in board of packing into, under protective atmosphere, bare chip is powered up aging;
2) bare chip after will wearing out takes out, and bump substrate and positioning baseplate is connected to the packaged chip test macro bare chip is tested, install the environment-guarantee device additional after, carry out three temperature tests.
Protective atmosphere in the described step 1) is nitrogen, and the volume content of nitrogen is lower than 0.5%.
Described step 2) the environment-guarantee device provides protective gas, chip surface high-temperature oxydation when avoiding high temperature test, chip surface frosting during low-temperature test in.
Compared with prior art, the present invention has following useful technique effect:
Bare chip ageing provided by the invention is with ejector and ageing method, design by bump substrate and positioning baseplate, chip welding spot is contacted with salient point, lead to external pad by welding again, realized that chip electrode draws, thereby can realize the screening of bare chip ageing, and guarantee to carry out normal pressure welding after the screening of bare chip ageing.
Bare chip ageing provided by the invention is with ejector and ageing method, for realizing that salient point contacts one to one with chip welding spot, aim at design, the i.e. aligning of the first location hole and the second location hole, guaranteed the relative position between bump substrate and the positioning baseplate, so that salient point accurately contacts with chip welding spot.
Bare chip ageing provided by the invention is with ejector and ageing method, the bare chip electrode is drawn the lead resistance (putting chip welding spot from outer lead) of bump substrate less than the lead resistance (from pin to chip welding spot) of chip during being encapsulated in the double straight cutting shell of 14 lines commonly used, it is enough little that the electric connection structure that the bare chip electrode is drawn bump substrate can guarantee that electrode is drawn the resistance in path, can satisfy the demand of bare chip test.
Description of drawings
Fig. 1 is the bump substrate structural representation.
Fig. 2 is the positioning baseplate structural representation.
Embodiment
The present invention is described in further detail below in conjunction with specific embodiment, and the explanation of the invention is not limited.
Referring to Fig. 1, Fig. 2, a kind of bare chip ageing ejector, comprise the bump substrate and the positioning baseplate that are complementary, bump substrate is provided with salient point 1 and the external pad 2 that is connected by conduction band 3, salient point 1 is arranged on the inside of bump substrate, external pad 2 be arranged on bump substrate around, also be provided with the first fixing hole 4 and the first location hole 5 on the bump substrate;
Positioning baseplate is provided with chip putting hole 6, and the second fixing hole 7 and the second location hole 8;
Behind bump substrate and positioning baseplate fastening, salient point 1 contacts with the phase of solder joint of the bare chip of chip putting hole 6 interior placements, and the first location hole 5 and the second location hole 8 align, and the first fixing hole 4 and the second fixing hole 7 align.
Further, for the electrode of bare chip is drawn, salient point 1 leads to external pad 2 by conduction band 3 according to treating that the solder joint of the bare chip of ageing lays respectively with all solder joints for the treatment of the bare chip of ageing.
Concrete, just need according to treating that the pad distribution of ageing bare chip carries out the layout design of the position of salient point array, conduction band line, external pad.
Described bump substrate is flexible printed circuit, and by the substrate manufacturing process manufacturing of connecting up, conduction band 3 and external pad 2 are printed on the flexible printed circuit, and salient point 1 is electroplated on flexible printed circuit.
For salient point 1 is contacted one to one with the solder joint (pad) of bare chip, carry out following aligning design:
Described positioning baseplate is epoxy resin base plate, and the first location hole 5 aligns afterwards with the second location hole 8 and is connected by bolt; Align positioning convex point 1 accurately to contact with the solder joint of bare chip by the first location hole 5 and the second location hole 8.
After the solder joint of bare chip caused external pad 2 outward, the contact resistance between bump substrate and the positioning baseplate was controlled to be:
The resistance sum maximum of two outer leads is 190～210m Ω, and minimum value is 120～135m Ω, and mean value is 150～165m Ω; The resistance mean value of single outer lead is 80～85m Ω.
Concrete, draw the performance of bump substrate for checking bare chip electrode, the bare chip electrode being drawn the contact resistance of bump substrate and chip tests, the resistance sum maximum of two outer leads is 202.668m Ω, minimum value is 131.579m Ω, mean value is 161.408m Ω, and the resistance mean value of single outer lead is 80.704m Ω.
And in standard packaging, the resistance sum maximum of two pins is 308.407m Ω, and minimum value is 160.631m Ω, and mean value is 216.889m Ω, and the resistance mean value of single outer lead is 108.444m Ω.
Contrast as can be known, the bare chip electrode is drawn the lead resistance (putting chip pad from outer lead) of bump substrate less than the lead resistance (from pin to chip pad) of chip during being encapsulated in the double straight cutting shell of 14 lines commonly used, it is enough little that the electric connection structure that the bare chip electrode is drawn bump substrate can guarantee that electrode is drawn the resistance in path, can satisfy the demand of bare chip test.
Based on the ageing method of described bare chip ageing with ejector, may further comprise the steps:
1) bare chip is placed in the chip putting hole of positioning baseplate, after will working as that bump substrate and positioning baseplate are aimed at and fastening, makes chip welding spot and one by one corresponding contact of salient point; After bump substrate and positioning baseplate is fixing, in the socket in the burn-in board of packing into, under protective atmosphere, bare chip is powered up aging;
Concrete, described protective atmosphere is nitrogen, the volume content of nitrogen is lower than 0.5%;
2) naked core after will wearing out takes out from ageing system, bump substrate and positioning baseplate are connected to the packaged chip test macro to be tested bare chip and (can test bare chip with existing general packaged chip test macro,), install the environment-guarantee device additional after, carry out three temperature tests.
Described environment-guarantee device provides necessary protective gas, chip surface high-temperature oxydation when avoiding high temperature test, chip surface frosting during low-temperature test.
Concrete, C4082 is that Representative Cultivars has been made bump substrate and positioning baseplate, has carried out practical application, the ageing screening effect is obvious.
Claims (9)
1. bare chip ageing ejector, it is characterized in that, comprise the bump substrate and the positioning baseplate that are complementary, bump substrate is provided with salient point (1) and the external pad (2) that is connected by conduction band (3), salient point (1) is arranged on the inside of bump substrate, external pad (2) be arranged on bump substrate around, also be provided with the first fixing hole (4) and the first location hole (5) on the bump substrate;
Positioning baseplate is provided with chip putting hole (6), and the second fixing hole (7) and the second location hole (8);
Behind bump substrate and positioning baseplate fastening, salient point (1) contacts with the phase of solder joint of the interior bare chip of placing of chip putting hole (6), and the first location hole (5) aligns with the second location hole (8), and the first fixing hole (4) aligns with the second fixing hole (7).
2. bare chip ageing ejector as claimed in claim 1, it is characterized in that, salient point (1) leads to external pad (2) by conduction band (3) according to treating that the solder joint of the bare chip of ageing lays respectively with all solder joints for the treatment of the bare chip of ageing.
3. bare chip ageing ejector as claimed in claim 1 is characterized in that, described bump substrate is flexible printed circuit, and conduction band (3) and external pad (2) are printed on the flexible printed circuit, and salient point (1) is electroplated on flexible printed circuit.
4. bare chip ageing ejector as claimed in claim 1 is characterized in that, described salient point (1) contacts one to one with the solder joint of bare chip.
5. bare chip ageing ejector as claimed in claim 1 is characterized in that, described positioning baseplate is epoxy resin base plate, and the first location hole (5) aligns afterwards with the second location hole (8) and is connected by bolt; Align positioning convex point (1) accurately to contact with the solder joint of bare chip by the first location hole (5) and the second location hole (8).
6. bare chip ageing ejector as claimed in claim 1 is characterized in that, after the solder joint of bare chip caused external pad (2) outward, the contact resistance between bump substrate and the positioning baseplate was controlled to be:
The resistance sum maximum of two outer leads is 190～210m Ω, and minimum value is 120～135m Ω, and mean value is 150～165m Ω; The resistance mean value of single outer lead is 80～85m Ω.
7. based on the ageing method of the described bare chip ageing of claim 1 with ejector, it is characterized in that, may further comprise the steps:
1) bare chip is placed in the chip putting hole of positioning baseplate, after will working as that bump substrate and positioning baseplate are aimed at and fastening, makes chip welding spot and one by one corresponding contact of salient point; After bump substrate and positioning baseplate is fixing, in the socket in the burn-in board of packing into, under protective atmosphere, bare chip is powered up aging;
2) bare chip after will wearing out takes out, and bump substrate and positioning baseplate is connected to the packaged chip test macro bare chip is tested, install the environment-guarantee device additional after, carry out three temperature tests.
8. ageing method as claimed in claim 7 is characterized in that, the protective atmosphere in the described step 1) is nitrogen, and the volume content of nitrogen is lower than 0.5%.
9. ageing method as claimed in claim 7 is characterized in that, described step 2) in the environment-guarantee device provide protective gas, chip surface high-temperature oxydation when avoiding high temperature test, chip surface frosting during low-temperature test.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN2013100224012A CN103077913A (en) | 2013-01-22 | 2013-01-22 | Lead-out device for aging bare chips and aging method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2013100224012A CN103077913A (en) | 2013-01-22 | 2013-01-22 | Lead-out device for aging bare chips and aging method |
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| CN103077913A true CN103077913A (en) | 2013-05-01 |
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| CN2013100224012A Pending CN103077913A (en) | 2013-01-22 | 2013-01-22 | Lead-out device for aging bare chips and aging method |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103824793A (en) * | 2014-02-28 | 2014-05-28 | 西安永电电气有限责任公司 | Electrode modification device |
| CN105206554A (en) * | 2015-10-12 | 2015-12-30 | 无锡必创传感科技有限公司 | Package device batched power-on aging device |
| CN106153986A (en) * | 2015-04-16 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | Test interface plate for bare chip and the test system for bare chip |
| CN106783843A (en) * | 2017-01-06 | 2017-05-31 | 中国科学院高能物理研究所 | Electrostatic discharge protection circuit, electrostatic protection apparatus and cDNA microarray method |
| CN108573894A (en) * | 2017-03-14 | 2018-09-25 | 欧姆龙株式会社 | Managing device and its control method, message handling program and record media |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970008544A (en) * | 1995-07-14 | 1997-02-24 | 김광호 | Leadframe for Inspection of Good Hard Dies with Separated Leads |
| CN1588636A (en) * | 2004-09-21 | 2005-03-02 | 威盛电子股份有限公司 | Detecting clamp and its top cover |
| CN201322759Y (en) * | 2008-11-24 | 2009-10-07 | 信息产业部电子第五研究所 | Bare chip testing for discrete device and aging temporary encapsulation carrier |
-
2013
- 2013-01-22 CN CN2013100224012A patent/CN103077913A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970008544A (en) * | 1995-07-14 | 1997-02-24 | 김광호 | Leadframe for Inspection of Good Hard Dies with Separated Leads |
| CN1588636A (en) * | 2004-09-21 | 2005-03-02 | 威盛电子股份有限公司 | Detecting clamp and its top cover |
| CN201322759Y (en) * | 2008-11-24 | 2009-10-07 | 信息产业部电子第五研究所 | Bare chip testing for discrete device and aging temporary encapsulation carrier |
Non-Patent Citations (1)
| Title |
|---|
| 刘林春: "《功率裸芯片的测试与老化筛选技术》", 20 May 2008, article "功率裸芯片的测试与老化筛选技术" * |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103824793A (en) * | 2014-02-28 | 2014-05-28 | 西安永电电气有限责任公司 | Electrode modification device |
| CN106153986A (en) * | 2015-04-16 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | Test interface plate for bare chip and the test system for bare chip |
| CN106153986B (en) * | 2015-04-16 | 2019-09-06 | 中芯国际集成电路制造(上海)有限公司 | For the test interface plate of bare chip and for the test macro of bare chip |
| CN105206554A (en) * | 2015-10-12 | 2015-12-30 | 无锡必创传感科技有限公司 | Package device batched power-on aging device |
| CN105206554B (en) * | 2015-10-12 | 2018-05-22 | 无锡必创传感科技有限公司 | A kind of packaging batch power-up aging equipment |
| CN106783843A (en) * | 2017-01-06 | 2017-05-31 | 中国科学院高能物理研究所 | Electrostatic discharge protection circuit, electrostatic protection apparatus and cDNA microarray method |
| CN106783843B (en) * | 2017-01-06 | 2019-03-19 | 中国科学院高能物理研究所 | Electrostatic discharge protection circuit, electrostatic protection apparatus and cDNA microarray method |
| CN108573894A (en) * | 2017-03-14 | 2018-09-25 | 欧姆龙株式会社 | Managing device and its control method, message handling program and record media |
| CN108573894B (en) * | 2017-03-14 | 2021-09-03 | 欧姆龙株式会社 | Management apparatus, control method thereof, and recording medium |
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Application publication date: 20130501 |