CN105425139B

CN105425139B - Test equipment for chip failure analysis

Info

Publication number: CN105425139B
Application number: CN201510919241.0A
Authority: CN
Inventors: 董宁; 刘攀超; 刘泽华
Original assignee: Centre Testing International Group Co ltd
Current assignee: Centre Testing International Group Co ltd
Priority date: 2015-12-10
Filing date: 2015-12-10
Publication date: 2023-05-05
Anticipated expiration: 2035-12-10
Also published as: CN105425139A

Abstract

The invention discloses test equipment for chip failure analysis, which comprises a bottom plate, a carrier plate and a clamping plate, wherein metal bulges are uniformly arranged in the center of the bottom plate, through holes which are uniformly arranged and correspond to the metal bulges are formed in the upper surface and the lower surface of the carrier plate, connecting pieces for connecting pins of a chip to be tested are arranged in the through holes, each connecting piece comprises a metal sheet arranged on the upper surface of the carrier plate and a metal probe connected under the metal sheet, the metal probes are sleeved with elastic parts, the elastic parts are fixed on the inner wall of the through holes, when the chip to be tested is arranged on the upper surface of the carrier plate, the clamping plate is lightly pressed on the chip to be tested, the pins of the chip to be tested are pressed on the metal sheet, the elastic parts are compressed together, and the metal probes are electrically connected with the metal bulges; the test machine is used for outputting test signals to the tested chip and is selectively and electrically connected with the metal bumps. The invention is a test device which can be widely applied to the failure analysis of chips with various packaging structures.

Description

Test equipment for chip failure analysis

Technical Field

The invention relates to the technical field of chip failure analysis, in particular to test equipment which can be widely applied to chip failure analysis of various packaging structures.

Background

Generally, failure of an integrated circuit is unavoidable in the processes of development, production and use, and as the requirements of people on product quality and reliability are continuously improved, failure analysis work is more and more important, and through chip failure analysis, the integrated circuit designer can be helped to find defects in design, mismatching of process parameters, mismatching in design and operation and other problems. The significance of failure analysis is mainly expressed in particular in the following aspects: failure analysis is a necessary means to determine the mechanism of chip failure. Failure analysis provides the necessary information for effective fault diagnosis. Failure analysis provides necessary feedback information for design engineers to continually improve or repair the design of the chip to make it more consistent with design specifications. Failure analysis can evaluate the effectiveness of different test vectors, provide necessary supplements for production tests, and provide necessary information basis for verification test flow optimization. The failure analysis main steps and the unsealing of the content chip: and removing the IC sealing glue, keeping the functions of the chip intact, and keeping die, bond pads, bond wire and even lead-frame free from damage, so as to prepare for the next chip failure analysis experiment. SEM scanning electron microscope/EDX composition analysis: including material structure analysis/defect observation, elemental composition conventional micro-area analysis, accurate measurement of component dimensions, and the like. Probe test: the electric signal inside the IC is obtained by the microprobe. Laser cutting: cutting off the circuit or specific area on the chip by micro laser beam.

In the process of improving the yield of the product, a product engineer needs to analyze the electrical and physical failures of the problem product, so as to diagnose the product. The position of the defect on the layout can be usually found out through electrical failure analysis, and physical failure analysis is required for defining the specific condition of the defect, and mainly comprises delamination, focused ion beam, scanning electron microscope (TEM), VC positioning technology and defect chemical composition analysis. The electrical failure analysis is a precondition of the physical failure analysis, and the physical failure analysis result is the purpose and evidence of the electrical failure analysis. In failure analysis, each step works together and is applied, which is indispensable.

In order to determine physical failure analysis and electrical failure analysis, connection test is required for each pin of a chip, and in the inspection industry, chips with various sizes and packaging types are often encountered, and each chip needs to be manufactured into a fixture before testing, which is a rather tedious work, so that it is necessary to develop a testing device capable of being widely applied to chips with various packaging structures for failure analysis.

Disclosure of Invention

The invention aims to provide test equipment which can be widely applied to chips with various packaging structures for failure analysis.

In order to achieve the above purpose, the technical scheme provided by the invention is as follows: there is provided a test apparatus for chip failure analysis, comprising:

the testing fixture comprises a bottom plate, a carrier plate and a clamping plate, wherein metal bulges which are uniformly arranged are arranged in the center of the bottom plate, through holes which are uniformly arranged and correspond to the metal bulges are formed in the upper surface and the lower surface of the carrier plate, connecting pieces which are used for being connected with pins of a chip to be tested are arranged in the through holes, the connecting pieces comprise metal sheets arranged on the upper surface of the carrier plate and metal probes connected under the metal sheets, the metal probes are sleeved with elastic parts, the elastic parts are fixed on the inner walls of the through holes, when the chip to be tested is arranged on the upper surface of the carrier plate, the clamping plate is lightly pressed on the chip to be tested, the pins of the chip to be tested are pressed on the metal sheets, the elastic parts are compressed together, and the metal probes are electrically connected with the metal bulges;

the test machine is used for outputting test signals to the tested chip and is selectively and electrically connected with the metal bumps.

The gold sheet is slightly convexly arranged on the upper surface of the carrier plate.

The bottom plate is also provided with a printed circuit and a plurality of metal columns, one end of the printed circuit is electrically connected with the metal protrusions, the other end of the printed circuit is electrically connected with the metal columns, and the test machine is selectively electrically connected with any metal column.

The metal sheet with the metal probe is integrated into a whole structure, just the elastic component is that the lower extreme has to the boss that the through-hole inner wall direction is protruding establishes, just the elastic component is the spring, just the spring upper end conflict in the lower terminal surface of metal sheet, the spring lower extreme passes through the boss block in through-hole inner wall department.

An electromagnetic shielding layer is arranged in the through hole, and a rough insulating layer structure is coated on the inner wall of the through hole.

The through hole is divided into an upper section and a lower section, the inner diameter of the upper section of the through hole is slightly larger than that of the lower section, a step structure is formed between the lower section and the upper section, the upper end of the spring is abutted against the lower end face of the metal sheet, and the lower end of the spring is clamped on the step structure.

The through hole is of a round table-shaped structure with a large upper part and a small lower part, the upper end of the spring is abutted against the lower end face of the metal sheet, and the lower end of the spring is clamped at the inner wall of the through hole.

The clamping plate comprises a clamping plate main body and a fixing plate which can be connected to the lower portion of the clamping plate main body, a fixing groove is formed in the fixing plate according to the appearance of the chip to be tested, the chip to be tested is embedded in the fixing groove, and the fixing plate is fixedly connected with the clamping plate main body through threads.

Still include high-power camera, high-power camera locates splint top, just splint main part and fixed plate are high transparent structure, when splint light press in the chip that is surveyed and will be surveyed the pin of chip press on foil, accessible high-power camera observes the pin of chip that is surveyed with foil's contact is good.

The metal sheet is brushed with a tin paste layer or a conductive silver paste layer which is used for being in good contact with the pins of the chip to be tested.

Compared with the prior art, the test equipment for chip failure analysis has the advantages that through holes which are uniformly arranged are formed in the carrier plate and penetrate through the upper surface and the lower surface of the carrier plate, so that when a chip to be tested is placed on the carrier plate, no matter which package type chip is placed on the carrier plate, pins can be placed on the metal sheet on the through holes, and the metal sheet is electrically connected with the metal probe, so that when the metal sheet is pressed, the metal probe is connected with the metal protrusion, and the test machine only needs to electrically connect the corresponding metal protrusion, and then test signals can be input to the chip to be tested. Therefore, the invention is a testing device with extremely wide application range, which can test different chips, and greatly shortens the research and development time of the testing device and reduces the development cost of the device.

The invention will become more apparent from the following description taken in conjunction with the accompanying drawings which illustrate embodiments of the invention.

Drawings

FIG. 1 is a schematic diagram of one embodiment of a test apparatus for chip failure analysis according to the present invention.

FIG. 2 is a schematic diagram of one embodiment of a backplane of the test apparatus for chip failure analysis shown in FIG. 1.

FIG. 3 is a schematic diagram of an embodiment of a carrier plate of the test apparatus for chip failure analysis shown in FIG. 1.

FIG. 4 is a schematic diagram of one embodiment of a connector of the test apparatus for chip failure analysis as shown in FIG. 1.

FIG. 5 is a schematic diagram of a cross-sectional structure of one embodiment of a through-hole of a test apparatus for chip failure analysis as shown in FIG. 1.

Fig. 6 is a schematic diagram of a cross-sectional structure of another embodiment of a through hole of the test apparatus for chip failure analysis as shown in fig. 1.

Detailed Description

Embodiments of the present invention will now be described with reference to the drawings, wherein like reference numerals represent like elements throughout. As described above, as shown in fig. 1 to 6, the test apparatus 100 for chip failure analysis according to the embodiment of the present invention includes:

the test fixture 1, the test fixture 1 comprises a bottom plate 10, a carrier plate 11 and a clamping plate 12, wherein metal protrusions 101 which are uniformly arranged are arranged in the center of the bottom plate 10, through holes 110 which are uniformly arranged and correspond to the metal protrusions 101 are formed in the upper surface and the lower surface of the carrier plate 11, connecting pieces 111 which are used for being connected with pins of a chip to be tested are arranged in the through holes 110, the connecting pieces 111 comprise metal sheets 1110 which are arranged on the upper surface of the carrier plate 11 and metal probes 1111 which are connected under the metal sheets 1110, the metal probes 1111 are sleeved with elastic components, the elastic components are fixed on the inner wall of the through holes 110, when the chip to be tested 2 is placed on the upper surface of the carrier plate 11, the clamping plate 12 is lightly pressed on the chip to be tested 2, the pins of the chip to be tested are pressed on the metal sheets 1110, the elastic components are compressed together, and the metal probes 1111 are electrically connected with the metal protrusions 101; in this embodiment, the metal bump 101 disposed in the center of the bottom plate 10 and the through hole 110 formed in the carrier 11 are all an array, and the number of bumps and through holes in the array and the size of the bumps and through holes can be preset according to the structure of the pins of the chip and the pitch between the pins. It should be noted that, since the package structure of the chip in the prior art at present is generally: the package structures, such as dual in-line package (DIP), small Outline Package (SOP), small outline package (SOJ), quad Flat Package (QFP), and Ball Grid Array (BGA), can be basically divided into a common pin shape or a ball grid array shape, and only needs to ensure that the pins are well contacted with the metal sheet 1110, and if when the chip 2 to be tested is placed on the metal sheet 1110, if the pins are too thick and the area of the metal sheet is smaller than the contact surface of the pins, one pin of the chip 2 to be tested can be simultaneously contacted with two adjacent metal sheets 1110, at this time, only one of the two adjacent metal sheets 1110 needs to be electrically connected with the test bench 3, and the test bench 3 is not prevented from outputting test signals to the chip 2 to be tested. In addition, the metal bumps 101 correspond to the through holes 110 in size, and the base plate 10 and the carrier plate 11 may be prefabricated according to test requirements.

The test machine 3 is used for outputting test signals to the tested chip 2, and is optionally electrically connected with the metal bump 101. The number of the metal bumps 101 on the bottom plate 10 may be relatively large, so that the tested chips 2 with different pin numbers can be conveniently tested, and therefore, only the metal bumps 101 contacted by the pins of the tested chips 2 need to be electrically connected in the testing process. The test board 3 outputs what kind of test signals are usually chip test stimulus developed by hardware description language verilog.

In one embodiment, the gold foil 1110 is disposed on the upper surface of the carrier plate 11 in a slightly convex manner. The purpose of the metal foil 1110 being slightly convex is to enable the pins of the chip 2 to be tested to better contact the metal foil 1110, and to better distinguish which part is in poor contact, such as whether there is a situation that one pin is not directly against the corresponding metal foil 1110.

In one embodiment, as shown in fig. 2, the base plate 10 is further provided with a printed circuit and a metal column 102, and fig. 2 shows only a part of the metal column 102, one end of the printed circuit is electrically connected to the metal bump 101, the other end is electrically connected to the metal column 102, and the test machine 3 is optionally electrically connected to any one of the metal columns 102. The metal column 102 can be connected to the bottom plate 10 through threads, the metal column 102 can be detached at ordinary times, and then is mounted when needed, so that the portable electronic device is convenient to carry and store.

In one embodiment, the metal sheet 1110 and the metal probe 1111 are integrally formed, the elastic member is a lower end having a boss 1113 protruding toward the inner wall of the through hole 110, the elastic member is a spring 1112, the upper end of the spring 1112 abuts against the lower end surface of the metal sheet 1110, and the lower end of the spring 1112 is engaged with the inner wall of the through hole 110 through the boss 1113. Since the boss 1113 is provided, it can be ensured that the connection member 111 that is not being knocked down does not come into contact with the metal boss 101.

In one embodiment, an electromagnetic shielding layer is disposed in the through hole 110, and a rough insulating layer structure is coated on the inner wall of the through hole 110. By providing the electromagnetic shielding layer, electromagnetic interference between the adjacent metal probes 1111 can be shielded from each other, the insulation layer structure can ensure insulation between the metal probes 1111 and the carrier 11, and the rough inner wall structure can ensure that the boss 1113 can be well clamped at the inner wall of the through hole 110.

In one embodiment, a schematic diagram of a cross-sectional structure of one embodiment of the via 110 is shown in FIG. 5. The through hole 110 is divided into an upper section and a lower section, the inner diameter of the upper section of the through hole 110 is slightly larger than the inner diameter of the lower section, a step structure 1101 is formed between the lower section and the upper section, the upper end of the spring 1112 is abutted against the lower end face of the metal sheet 1110, and the lower end of the spring 1112 is clamped on the step structure 1101. That is, the spring 1112 is limited to the upper section of the through hole 110, in this embodiment, the upper section and the lower section of the through hole 110 must be ensured to have a coaxial structure, and since the upper section and the lower section of the through hole 110 can be separated from each other, they are fixed by adhesion or screw connection.

In one embodiment, a schematic cross-sectional structure of another embodiment of the through hole 110 is shown in fig. 6. The through hole 110 is in a truncated cone structure with a large upper part and a small lower part, the upper end of the spring 1112 is abutted against the lower end surface of the metal sheet 1110, and the lower end of the spring 1112 is clamped at the inner wall of the through hole 110. In this embodiment, the processing and manufacturing process is simpler than that in the embodiment shown in fig. 5, but the mechanical performance requirements for the material of the carrier 11 are higher, and a stronger and durable material is required.

In one embodiment, as shown in fig. 1, the clamping plate 12 includes a clamping plate main body 121 and a fixing plate 122 that can be connected to a lower portion of the clamping plate main body 121, the fixing plate 122 is provided with a fixing groove according to an outline of the chip 2 to be tested, and the chip 2 to be tested is embedded in the fixing groove, and the fixing plate 122 is screwed and fixed with the clamping plate main body 121. Through the structure of dividing the clamping plate 12 into two parts, therefore, each time to the tested chip 2 with different models and sizes, only the fixing plate 122 needs to be modified, so that the development difficulty and the development cost of the template can be effectively reduced.

In one embodiment, as shown in fig. 1, the device further includes a high power camera 4, the high power camera 4 is disposed above the clamping plate 12, and the clamping plate main body 121 and the fixing plate 122 are both of a highly transparent structure, when the clamping plate 12 is lightly pressed against the chip 2 to be tested and presses the pins of the chip 2 to be tested against the metal sheet 1110, whether the pins of the chip 2 to be tested are in good contact with the metal sheet 1110 can be observed through the high power camera 4. In addition, in this embodiment, if the chip 2 to be tested with a small size is encountered, it may be directly fixed on the fixing plate 122 and placed on the metal sheet 1110, where the fixing plate 122 is not connected to the clamping plate main body 121, so that the effect is better by directly observing and aligning through the high power camera 4.

In one embodiment, the foil 1110 is brushed with a layer of solder paste or conductive silver paste for good contact with the pins of the chip 2 under test. The electrical contact performance between the chip 2 to be tested and the metal sheet 1110 can be greatly improved by the solder paste layer or the conductive silver paste layer. The applicant has found that the effect of brushing the solder paste layer or the conductive silver paste layer to improve the electrical contact performance is excellent during long-term operation, and is particularly suitable for small-sized chips 2 to be tested.

Referring to fig. 1-6, compared with the prior art, in the test apparatus 100 for chip failure analysis of the present invention, since the through holes 110 are uniformly arranged in the carrier 11 and penetrate through the upper surface and the lower surface of the carrier 11, when the chip 2 to be tested is placed on the carrier 11, no matter which package type chip is used, the pins can be placed on the metal sheet 1110 on the through holes 110, and the metal sheet 1110 is electrically connected with the metal probe 1111, so that when the metal sheet 1110 is pressed, the metal probe 1111 is connected with the metal bump 101, and the test machine 3 only needs to electrically connect the corresponding metal bump 101, so that a test signal can be input to the chip 2 to be tested. Therefore, the invention is a testing device with extremely wide application range, which can test different chips, and greatly shortens the research and development time of the testing device and reduces the development cost of the device.

The foregoing description of the preferred embodiments of the present invention is not intended to limit the scope of the claims, which follow, as defined in the claims.

Claims

1. A test apparatus for chip failure analysis, comprising:

the test machine is used for outputting test signals to the tested chip and is selectively and electrically connected with the metal bumps;

the metal bulge arranged in the center of the bottom plate and the through hole arranged on the carrier plate are both an array;

the bottom plate is also provided with a printed circuit and a plurality of metal columns, one end of the printed circuit is electrically connected with the metal protrusion, the other end of the printed circuit is electrically connected with the metal columns, and the test machine is selectively electrically connected with any metal column;

the clamping plate comprises a clamping plate main body and a fixing plate which can be connected to the lower part of the clamping plate main body, wherein the fixing plate is provided with a fixing groove according to the appearance of a chip to be tested, the chip to be tested is embedded in the fixing groove, and the fixing plate is fixedly connected with the clamping plate main body through threads;

the metal sheet is slightly convexly arranged on the upper surface of the carrier plate;

the metal sheet and the metal probe are of an integrated structure, the lower end of the elastic part is provided with a boss protruding towards the inner wall direction of the through hole, the elastic part is a spring, the upper end of the spring is abutted against the lower end face of the metal sheet, and the lower end of the spring is clamped at the inner wall of the through hole through the boss;

an electromagnetic shielding layer is arranged in the through hole, and a rough insulating layer structure is coated on the inner wall of the through hole;

the through hole is divided into an upper section and a lower section, the inner diameter of the upper section of the through hole is slightly larger than that of the lower section, a step structure is formed between the lower section and the upper section, the upper end of the spring is abutted against the lower end face of the metal sheet, and the lower end of the spring is clamped on the step structure;

2. The device for testing failure analysis of chips as defined in claim 1, further comprising a high power camera, wherein the high power camera is disposed above the clamping plate, and the clamping plate body and the fixing plate are both of a highly transparent structure, and when the clamping plate is lightly pressed against the chip to be tested and presses pins of the chip to be tested against the metal sheet, the high power camera can be used to observe whether the pins of the chip to be tested are in good contact with the metal sheet.

3. The test apparatus for chip failure analysis according to claim 1, wherein the metal foil is brushed with a solder paste layer or a conductive silver paste layer for good contact with the pins of the chip under test.