CN109425810B

CN109425810B - Semiconductor test apparatus, semiconductor test system, and semiconductor test method

Info

Publication number: CN109425810B
Application number: CN201710712004.6A
Authority: CN
Inventors: 陈颢; 林鸿志; 王敏哲
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2017-08-18
Filing date: 2017-08-18
Publication date: 2021-08-24
Anticipated expiration: 2037-08-18
Also published as: CN109425810A

Abstract

The present disclosure provides a semiconductor test apparatus, a semiconductor test system and a semiconductor test method, wherein the semiconductor test apparatus includes: a substrate; and the golden finger contact piece structure is placed on one side of the substrate. The semiconductor testing device provided by the disclosure can improve the efficiency of Board Level Reliability Tests (BLRT) in a development stage.

Description

Semiconductor test apparatus, semiconductor test system, and semiconductor test method

Technical Field

The present disclosure relates to the field of semiconductor, and more particularly, to a semiconductor testing apparatus, a semiconductor testing system and a semiconductor testing method.

Background

The global market currently forces manufacturers of a large number of products to offer high quality products at low prices. Therefore, it is important to improve yield and process efficiency in order to minimize production costs. This situation occurs particularly in the field of semiconductor manufacturing, since said field combines sophisticated technology (dicing edge technology) with mass production technology. Therefore, it is a goal of semiconductor manufacturers to improve the efficiency of the development phase while increasing the yield of the production phase process.

In view of the above, an object of the present invention is to provide a semiconductor testing apparatus, a related system and a related method, so as to improve the efficiency of Board Level Reliability Tests (BLRT) in the development stage.

Disclosure of Invention

Some embodiments of the present disclosure provide a semiconductor test apparatus, comprising: a substrate; and the golden finger contact piece structure is placed on one side of the substrate.

Some embodiments of the present disclosure provide a semiconductor test system, comprising: the test carrier plate is provided with a plurality of channels; the slot is placed on the test carrier plate; a plurality of wires disposed in the slots; and the semiconductor test apparatus according to claim 1 inserted into the socket; wherein the plurality of wires of the gold finger contact structure of the semiconductor test device contact the plurality of wires of the socket, respectively.

Some embodiments of the present disclosure provide a semiconductor testing method for testing board level reliability of a package component to be tested on a substrate, wherein the substrate is connected to a test carrier board by a gold finger contact structure, the method comprising: testing the gold finger contact structure using a short feedback path; welding and adhering the packaging assembly to be tested to the substrate by using a surface adhesion technology; and testing board level reliability of the package component to be tested on the substrate using long feedback path testing.

The semiconductor testing apparatus, the semiconductor testing system and the semiconductor testing method provided by the present disclosure can improve the efficiency of Board Level Reliability Tests (BLRT).

Drawings

To assist the reader in achieving the best understanding, it is suggested that, upon reading this disclosure, reference be made to the accompanying drawings and detailed description thereof. Please note that the drawings in this patent specification are not necessarily drawn to scale in order to comply with industry standards. In some drawings, the dimensions may be exaggerated or minimized intentionally to assist the reader in understanding the discussion herein.

FIG. 1 is a schematic diagram of an embodiment of a semiconductor test apparatus according to the present disclosure;

FIG. 2 is a side view of the semiconductor test apparatus of FIG. 1 according to the present disclosure;

FIG. 3 is a schematic diagram of an embodiment of a semiconductor test system in which the semiconductor test apparatus of FIG. 1 is inserted into a test carrier of a semiconductor test machine;

FIG. 4 is a side view of the semiconductor testing apparatus of FIG. 1 inserted into a test carrier of a semiconductor testing machine;

FIG. 5 is a schematic view of another embodiment of a semiconductor test system with a semiconductor test apparatus inserted in a test carrier of a semiconductor test machine according to the present disclosure;

FIGS. 6 and 7 are schematic diagrams of exemplary test circuit arrangements of the semiconductor test system of the present disclosure;

FIG. 8 is a schematic diagram of another exemplary test circuit arrangement of the semiconductor test system according to the present disclosure;

FIG. 9 is a schematic diagram of an embodiment of a test line extension of the semiconductor test system of FIGS. 6-7;

FIG. 10 is a schematic diagram of an embodiment of a test line extension of the semiconductor test system of FIG. 8;

FIG. 11 is a schematic diagram of a semiconductor test system according to an embodiment of the present disclosure during high and low temperature testing; and

FIG. 12 is a diagram illustrating an embodiment of a semiconductor testing method according to the present disclosure.

Detailed Description

The present disclosure provides many different embodiments, or examples, for implementing different features of the invention. For simplicity of illustration, examples of specific components and arrangements are also described in the present disclosure. It should be noted that these specific examples are provided for illustrative purposes only and are not intended to be limiting in any way. For example, the following description of how a first feature may be formed over or on a second feature may include certain embodiments in which the first feature is in direct contact with the second feature, and may also include other embodiments in which the second feature is intermediate to the first feature such that the first feature is not in direct contact with the second feature. Moreover, various examples in this disclosure may use repeated reference numbers and/or textual labels, which do not represent an association between different embodiments and arrangements, to make the document simpler and clearer.

Furthermore, the present disclosure uses spatially relative terms, such as "below," "lower," "above," "over," "lower," "top," "bottom," and the like, to describe one element or feature's relationship to another element(s) or feature(s) in the drawings for ease of description. These spatially relative terms are used to describe possible angles and orientations of the device in use and operation, in addition to the angular orientation shown in the drawings. The angular orientation of the device may vary (rotated 90 degrees or at other orientations) and these spatially relative descriptors used in this disclosure are to be interpreted in a similar manner.

Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the disclosure are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in their respective testing measurements. Likewise, as used herein, the term "about" generally refers to within 10%, 5%, 1%, or 0.5% of a given value or range. Alternatively, the term "about" refers to an acceptable standard deviation of the mean, as considered by one of ordinary skill in the art. Except in the operating/working examples, or where otherwise indicated, all numerical ranges, amounts, values, and percentages such as amounts of material, time periods, temperatures, operating conditions, proportions of amounts, and the like disclosed herein are to be understood as modified in all instances by the term "about". Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present disclosure and attached claims are approximations that may vary depending upon the desired properties sought to be obtained. At the very least, each numerical parameter should be interpreted based on at least the reported significances and the application of conventional carry techniques. Ranges may be expressed herein as from one end point to another end point or between two end points. Unless specifically stated otherwise, all ranges disclosed herein are inclusive of the endpoints.

In the advanced process, as the number of signal output pins of an Integrated Circuit (IC) increases, the requirement for Ball Pitch tends to be strict, and a package manner using an Integrated Fan-Out (InFO) package technology is developed in addition to the requirement for adjusting the size and the position of the signal output pins of a Printed Circuit Board (PCB) package after the IC package. The integrated fan-out Packaging technology adopts a wire-out mode, and utilizes a Wafer Level Packaging (WLP) process to embed various different bare chips, which is substantially equal to the reduction of one Packaging procedure. In other words, where more than one die is placed, the integrated fan-out package technology may save more than one layer of package structure, thereby reducing the form factor of the package, as well as the overall manufacturing cost.

The integrated fan-out package Technology may be placed on a printed circuit board in conjunction with Surface Mount Technology (SMT), which is a convenient and fast emerging Technology that allows electronic components to be quickly soldered onto a substrate and maintains the circuit between the components and the substrate unobstructed. However, the fan-out package using the surface mount technology may cause short circuit or open circuit of the package due to some reasons, such as "heat", "moisture", etc. Board Level Reliability Tests (BLRT) are procedures used to ensure that the soldering of components does not suffer from short circuits and/or open circuits during the development phase. The semiconductor testing apparatus, the semiconductor testing system and the semiconductor testing method provided in the following embodiments can improve the performance of the board level reliability test, thereby achieving the purpose of automatic testing.

FIG. 1 is a schematic diagram of a semiconductor test apparatus according to an embodiment of the present disclosure. The semiconductor test apparatus 100 includes a substrate 102 and a gold finger contact structure 106, the gold finger contact structure 106 is disposed on one side of the substrate 102, the gold finger contact structure 106 includes a plurality of conductive wires 108 made of conductive material, such as gold plating or tin plating, wherein the format of the gold finger structure 106 may be Dual in-line Memory Module (DIMM) Interface, Peripheral Component Interconnect (PCI) Interface, Peripheral Component interconnect Express (PCI-E), Universal Serial Bus (USB) Interface, or Accelerated Graphics Port (AGP) Interface, and the semiconductor test apparatus 100 may be an adapter card with various signal transmission formats. The following description will explain how the semiconductor test apparatus 100 is inserted into a socket of a test carrier of a semiconductor tester to perform an automatic test method of the semiconductor test apparatus 100 by using a semiconductor test system.

A plurality of integrated fan-out package assemblies 104_ 1-104 _4 are placed on the substrate 102 by surface mount technology. In this embodiment, the arrangement of the integrated fan-out packages 104_ 1-104 _4 is merely exemplary, and the number and arrangement of the integrated fan-out packages are not limited thereto. It should be noted that although the embodiments of the present disclosure are directed to improving the board level reliability test of integrated fan-out package technology combined with surface mount technology on a printed circuit board, the present disclosure is not limited thereto. The disclosed embodiments may also be applied to any other feasible packaging techniques and any other feasible bonding techniques.

FIG. 2 is a side view of the semiconductor test apparatus of FIG. 1 according to the present disclosure. As can be seen from fig. 2, in this embodiment, the plurality of conductive lines 108 of the gold finger contact structure 106 are further divided into a plurality of conductive lines 108_1 disposed on the front side of the gold finger contact structure 106 and a plurality of conductive lines 108_2 disposed on the back side of the gold finger contact structure 106, so as to increase the number of signals that can be tested, and finally achieve the purpose of increasing the test coverage (test coverage), but the disclosure is not limited thereto.

Fig. 3 is a schematic diagram of an embodiment of the semiconductor test system of fig. 1, in which the semiconductor test apparatus is inserted into a test carrier of a semiconductor test machine. At least one slot 112_1 is disposed on the test carrier 110, the slot 112_1 is used to accommodate the gold finger contact structure 106 of the semiconductor test apparatus 100, and a plurality of wires 114 are disposed in the slot 112_1 to correspond to the plurality of wires 108 of the gold finger contact structure 106, so that the semiconductor test apparatus 100 is electrically connected to the test carrier 110 of the semiconductor test machine. For convenience of illustration, only the slot 112_1 is shown in the front view of FIG. 3, but the embodiment may actually include a plurality of slots 112_ 1-112 _ n, where n is any integer greater than 1. FIG. 4 is a side view of the semiconductor testing device of FIG. 1 inserted into a test carrier of a semiconductor testing machine, and referring to FIG. 4, the placement of slots 112_1 to 112_ n according to the present embodiment can be understood, wherein n semiconductor testing devices 100_1 to 100_ n respectively correspond to the slots 112_1 to 112_ n. Fig. 4 also shows that the plurality of conductive lines 114 are further divided into a plurality of conductive lines 114_1 corresponding to the plurality of conductive lines 108_1 on the front side of the gold finger contact structure 106 and a plurality of conductive lines 114_2 corresponding to the plurality of conductive lines 108_2 on the back side of the gold finger contact structure 106. When the semiconductor test devices 100_ 1-100 _ n are inserted into the sockets 112_ 1-112 _ n, respectively, the gold finger contact structure 106 is embedded into the socket recess, such that the plurality of wires 108_1 on the front side of the gold finger contact structure 106 contact the plurality of wires 114_1 in the socket recess, and the plurality of wires 108_2 on the back side of the gold finger contact structure 106 contact the plurality of wires 114_2 in the socket recess.

Fig. 5 is a schematic diagram of a semiconductor test system in which the semiconductor test apparatus of the present disclosure is inserted into a test carrier of a semiconductor test machine. The semiconductor test apparatus 500 has a structure similar to the semiconductor test apparatus 100, and includes a substrate 502 and a gold finger pad structure 506, and a plurality of integrated fan-out package assemblies 504_ 1-504 _4 are disposed on the substrate 502 by surface mount technology. The test carrier 510 has a structure similar to the test carrier 110, and has at least one slot 512_1 disposed therein, the slot 512_1 is used to accommodate the gold finger contact structure 506 of the semiconductor test apparatus 500, and the slot 512_1 has a plurality of wires 514 disposed therein corresponding to the plurality of wires 508 of the gold finger contact structure 506, so that the semiconductor test apparatus 500 is electrically connected to the test carrier 510 of the semiconductor test machine.

The semiconductor test apparatus 500 is different from the semiconductor test apparatus 100 in that the gold finger pad structure 506 has a lead-in structure a, and the socket 512_1 is different from the socket 112_1 of fig. 3 in that the socket 512_1 has a lead-in structure a' whose profile characteristics correspond to the lead-in structure a and can be combined with each other. In this embodiment, the lead-in structure a is a concave structure; the lead-in structure a 'is a convex structure, and during the process of the golden finger contact structure 506 of the semiconductor test apparatus 500 entering the socket 512_1, the concave structure a of the golden finger contact structure 506 can help the golden finger contact structure 506 to be led into the correct position, and finally, the concave structure a is tightly combined with the convex structure a' of the socket 512_1, so as to ensure that the plurality of wires 508 correctly contact the corresponding plurality of wires 514. However, the disclosure is not limited thereto, the lead-in structure a of the gold finger pad structure 506 may have other appearance features, and the lead-in structure a' of the socket 512_1 may have appearance features corresponding to the lead-in structure a. For example, lead-in structure a may be a convex structure, and lead-in structure a' may be a concave structure.

Fig. 6 and 7 are schematic diagrams illustrating an embodiment of a test circuit layout of the semiconductor test system according to the present disclosure. The test wiring arrangements of fig. 6 and 7 include a plurality of short feedback (short feedback) paths and a plurality of long feedback (long feedback) paths. In fig. 6, the short feedback path is indicated by arrows and is primarily used to test whether the plurality of conductive lines 108 of the gold finger contact structure 106 are all properly in contact with the plurality of conductive lines 114 of the socket 112_ 1. In this embodiment, the plurality of wires 114 of the socket 112_1 are electrically connected to the plurality of channels (channels) of the test carrier 110, respectively, and the plurality of wires 108 of the gold finger pad structure 106 are arranged to be connected two by two after entering the substrate 102, so that when the gold finger pad structure 106 is inserted into the socket 112_1, a test signal can reach the substrate 102 from the first channel Ch1 of the test carrier 110 through the socket 112_1 and the gold finger pad structure 106, and can be directly fed back to the second channel Ch2 of the test carrier 110 through the gold finger pad structure 106 and the socket 112_1 without passing through the plurality of integrated fan-out package assemblies 104_ 1-104 _ 4. By using the short feedback paths, the leads 108 of the gold finger pad structure 106 can be electrically connected to the leads 114 of the socket 112_1 before formal testing of the substrate 102 and the integrated fan-out packages 104_ 1-104 _4 is started. For example, if the gold finger contact structure 106 has 204 leads, then 102 short feedback paths are created, requiring the use of 102 channels on the test carrier 110.

In FIG. 7, the long feedback path is indicated by arrows and is primarily used to test whether the integrated fan-out package components 104_ 1-104 _4 are electrically connected to the substrate 102 as expected. In the present embodiment, the plurality of wires 108 of the gold finger contact structure 106 are arranged in a redundant (redundancy) layout, which reduces the probability of test failure due to poor contact between the gold finger contact structure 106 and the socket 112_ 1. Specifically, more than one of the plurality of conductors 108 may be coupled to the input of each test Chain, e.g., two of the plurality of conductors 108 may be coupled to the input of the first test Chain, Chain1_ H, and more than one may be coupled to the output of each test Chain, e.g., the other two of the plurality of conductors 108 may be coupled to the output of the first test Chain, Chain1_ T. The first test chain passes through at least one of the integrated fan-out package components 104_ 1-104 _ 4. When the gold finger pad structure 106 is inserted into the socket 112_1, the test signal may pass from the first channel Ch1 and the second channel Ch2 of the test carrier 110, through the socket 112_1 and the gold finger pad structure 106 to the substrate 102, and into the input terminal Chain, Chain1_ H of the first test Chain. The first test Chain passes through at least one of the integrated fan-out packages 104_ 1-104 _4 and is fed back from the output terminal Chain1_ T to the third channel Ch3 and the fourth channel Ch4 of the test carrier 110 through the gold finger contact structure 106 and the socket 112_ 1.

Since the first Ch1 and the second Ch2 are the same signal, the third Ch3 and the fourth Ch4 are the same signal, and the same two channels are used for the next two channels during the testing of the long feedback path, the original first Ch1 and second Ch2 in fig. 7 are merged, the original third Ch3 and fourth Ch4 are merged, and the original two channels are merged in fig. 8, so the same effect can be achieved.

FIG. 9 is a schematic diagram of an embodiment of a test line extension of the semiconductor test system of FIGS. 6-7. The n semiconductor test devices 100_1 to 100_ n shown in FIG. 9 are inserted into the sockets 112_1 to 112_ n of the test carrier 110, respectively. Under the condition that each of the semiconductor test devices 100_1 to 100_ n has the same short feedback path and long feedback path arrangement, the corresponding short feedback path/long feedback path of each of the semiconductor test devices 100_1 to 100_ n can be connected in series for testing, so as to save the testing time. For example, the semiconductor test apparatuses 100_1 to 100_ n should be tested by the first test chain, i.e. the signal output terminals of the semiconductor test apparatuses 100_1 to 100_ n not connected to the first test chain should be connected to the third channel Ch3 and the fourth channel Ch4, however, in fig. 9, the signal output terminal of the first test chain of the semiconductor test apparatus 100_1 is connected in series to the signal input terminal of the first test chain of the semiconductor test apparatus 100_2, the signal output terminal of the first test chain of the semiconductor test apparatus 100_2 is connected in series to the signal input terminal of the first test chain of the semiconductor test apparatus 100_3, and connected in series all the way to the semiconductor test apparatus 100_ n in this manner, and finally the signal output terminal of the first test chain of the semiconductor test apparatus 100_ n is connected to the third channel Ch3 and the fourth channel Ch 4.

FIG. 10 is a schematic diagram of an embodiment of a test line extension of the semiconductor test system of FIG. 8. In FIG. 10, n semiconductor test devices 100_1 to 100_ n are inserted into slots 112_1 to 112_ n of a test carrier 110, respectively. Under the condition that each of the semiconductor test devices 100_1 to 100_ n has the same long feedback path arrangement, the corresponding long feedback paths of each of the semiconductor test devices 100_1 to 100_ n can be connected in series for testing, so as to save the testing time. For example, the semiconductor test apparatuses 100_1 to 100_ n are originally tested by the first test chain, that is, the signal output terminal of the first test chain of the semiconductor test apparatuses 100_1 to 100_ n should be connected to the second channel Ch2, but in fig. 10, the signal output terminal of the first test chain of the semiconductor test apparatus 100_1 is connected to the signal input terminal of the first test chain of the semiconductor test apparatus 100_2, the signal output terminal of the first test chain of the semiconductor test apparatus 100_2 is connected to the signal input terminal of the first test chain of the semiconductor test apparatus 100_3, and is connected to the semiconductor test apparatus 100_ n all the way, and finally the signal output terminal of the first test chain of the semiconductor test apparatus 100_ n is connected to the second channel Ch 2.

FIG. 11 is a schematic diagram of a semiconductor test system according to an embodiment of the present disclosure during high and low temperature testing. When performing high and low temperature tests, a thermal insulation device (not shown) may be covered on the test carrier 110 at the dotted line, so that a desired temperature is generated in the thermal insulation device for performing the tests. In this embodiment, depending on the specification of the thermal isolator, part of the semiconductor test device is removed from the socket at a position required to be subjected to a test. For example, if the thermal insulation device is to be covered on the semiconductor test device 100_2, the semiconductor test devices 100_1 and 100_3 are removed from the sockets 112_1 and 112_ 3. However, the present disclosure is not limited thereto.

FIG. 12 is a diagram illustrating an embodiment of a semiconductor testing method according to the present disclosure. The semiconductor test method 1200 includes steps 1202-1216, wherein the order of the individual steps does not imply that the steps must be performed in the order recited. Rather, the steps may be performed in any suitable order. Wherein steps 1202-1204 are accomplished with the short feedback path in the previous embodiment of the present disclosure, and steps 1208-1216 are accomplished with the long feedback path in the previous embodiment of the present disclosure. In step 1202, a continuity test (continuity test) is performed on the gold finger pad structure 106 of the embodiment of the present disclosure to verify whether the plurality of wires 108 of the gold finger pad structure 106 are all normally in contact with the plurality of wires 114 of the socket 112_ 1. In step 1204, a short circuit test is performed on the gold finger contact structure 106 of the disclosed embodiment to verify whether the plurality of wires 108 of the gold finger contact structure 106 and the plurality of wires 114 of the socket 112_1 are shorted with each other, which in this embodiment may include an N-leak test (N-leak test). In step 1206, the integrated fan-out package assemblies 104_ 1-104 _4 are bonded to the substrate 102 by surface mount technology to prepare for subsequent board level reliability tests for the integrated fan-out package assemblies 104_ 1-104 _4 and the substrate 102.

In step 1208, a test chain open test is performed, for example, in this embodiment, the test chain open test includes a test chain impedance test (chain resistance test). In step 1210, a test chain short test is performed, for example, in this embodiment, the test chain short test includes a test chain N-leak test (chain N-leak test). After the first round of testing chain open-circuit testing and testing chain short-circuit testing is completed, in step 1212, a short-circuit testing is performed on a path through which the testing chain passes under a high voltage condition by using a chain N-leakage stress (chain N-leakage stress). Finally, in steps 1214 to 1216, the tests of steps 1208 to 1210 are repeated to check whether the path traveled by the test chain is still normal after passing the high voltage.

Some embodiments of the present disclosure provide a semiconductor test apparatus for placing a package under test thereon, the semiconductor test apparatus comprising: a substrate; and the golden finger contact piece structure is arranged on one side of the substrate.

Some embodiments of the present disclosure provide a semiconductor test method for testing the board level reliability of an integrated fan-out package assembly on a substrate, wherein the substrate is connected to a test carrier board using a gold finger pad structure, the method comprising: testing the gold finger contact structure using a short feedback path; bonding the integrated fan-out packaging assembly to the substrate by using a surface adhesion technology; and testing board level reliability of the integrated fan-out package assembly on the substrate using long feedback path testing.

The foregoing outlines features of some embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Description of the symbols

100. 500 semiconductor test device

102. 502 substrate

104_ 1-104 _4 integrated fan-out packaging assembly

504_ 1-504 _4 integrated fan-out package assembly

106. 506 golden finger contact piece structure

108. 508 multiple conductors

108_1 and 108_2 multiple conductors

110. 510 test carrier plate

112_1 to 112_ n slots

512_1 slot

114. 514 plurality of conducting wires

114_1 to 114_2 multiple conductive lines

100_1 to 100_ n semiconductor test apparatus

A. A' introduction structure

Input terminal of first test Chain of Chain1_ H

Output of the first test Chain of Chain1_ T

Ch1 first channel

Ch2 second channel

Ch3 third channel

Ch4 fourth channel

1200 method

1202 to 1216

Claims

1. A semiconductor test apparatus for placing a package under test thereon, the semiconductor test apparatus comprising:

a substrate; and

a gold finger contact structure disposed on one side of the substrate, wherein the gold finger contact structure comprises a plurality of conductive lines and a lead-in structure, wherein the lead-in structure is separated from the plurality of conductive lines, wherein a first conductive line and a second conductive line of the plurality of conductive lines are electrically shorted on the substrate.

2. The device of claim 1, wherein the plurality of wires are disposed on a front side and a back side of the gold finger contact pad structure.

3. The device of claim 1, wherein the lead-in structure is a concave structure.

4. A semiconductor test system, comprising:

the test carrier plate is provided with a plurality of channels;

the slot is placed on the test carrier plate;

a plurality of wires disposed in the slots; and

the semiconductor test apparatus of claim 1, inserted into the socket;

wherein the plurality of wires of the gold finger contact structure of the semiconductor test device are respectively in contact with the plurality of wires of the socket, wherein the plurality of wires of the gold finger contact structure comprise a first wire and a second wire, wherein the first wire and the second wire are electrically shorted on the substrate.

5. The system of claim 4, wherein the semiconductor test system has at least one test chain routed from one of the plurality of channels of the test carrier, through the socket and the gold finger contact structure to the package under test placed on the semiconductor test device, and through the gold finger contact structure and the socket back to another of the plurality of channels of the test carrier.

6. The system of claim 5, wherein a path of the test chain through the socket and the gold finger contact structure to the semiconductor test device passes through a third wire and a fourth wire of the plurality of wires of the gold finger contact structure; and when the path of the test chain returns to the test carrier plate through the golden finger contact structure and the slot, the path of the test chain passes through a fifth wire and a sixth wire in the plurality of wires of the golden finger contact structure.

7. The system of claim 6, wherein a path of the test chain through the socket and the gold finger contact structure to the semiconductor test device passes through a first wire and a second wire of a plurality of wires of the socket; and when the path of the test chain returns to the test carrier plate through the golden finger contact structure and the slot, the path of the test chain passes through a third wire and a fourth wire in the plurality of wires of the slot.

8. The system of claim 4, further comprising:

another slot; and

another semiconductor test apparatus according to claim 1, inserted into the another slot.

9. A semiconductor test method for testing board level reliability of a package assembly under test on a substrate, wherein the substrate is connected to a test carrier board using a gold finger pad structure, the method comprising:

testing the connection between the golden finger contact structure and the test carrier plate by utilizing a short feedback path formed by the mutual electrical short circuit of the first lead and the second lead of the golden finger contact structure;

welding and adhering the packaging assembly to be tested to the substrate; and

testing board level reliability of the package component under test on the substrate using long feedback path testing.