JP2004138405A - Probe for measuring semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To collectively measure semiconductor devices in a state in which a plurality of the semiconductor devices are integrally formed before the formation of discrete pieces such as a wafer. <P>SOLUTION: A single contact pin or a plurality of contact pins are aligned and housed in a housing. The tip part of the single contact pin or the tip parts of the plurality of contact pins are arranged in such a way as to be protruded from one external surface of the housing. The single contact pin or the plurality of the contact pins are slidable in a vertical direction in the external surface of the housing. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a probe for measuring a semiconductor device, and more particularly to a technique which is effective when applied to collectively measure a plurality of semiconductor devices.
[0002]
[Prior art]
In the manufacture of a conventional semiconductor device, a predetermined circuit is formed by collectively forming semiconductor elements or wiring patterns in a plurality of element formation regions provided on a wafer of single crystal silicon or the like, and forming a predetermined circuit between adjacent element formation regions. The wafer is cut in the scribing area, and dicing is performed to separate each element formation area as individual semiconductor chips. The individual semiconductor chips thus singulated are fixed to a base substrate or a lead frame, for example. The semiconductor device is completed through a mounting process such as bonding and wire bonding and a sealing process such as resin sealing.
[0003]
However, in electronic devices on which semiconductor devices are mounted, miniaturization and thinning, and high-speed and high-frequency operations are being promoted, and mounting forms in which semiconductor devices are mounted on electronic device mounting boards are also reduced in size and thickness. And higher density are required. For this reason, there is an increasing need for bare chip mounting in which a semiconductor chip is directly mounted on a mounting substrate and MCM (Multi Chip Module) in which a plurality of semiconductor devices are sealed in a single sealing body.
[0004]
In such a case, before the mounting in the bare chip mounting, and before the sealing in the MCM, each semiconductor chip is preliminarily separated from a good product (KGD (Known Good Die)) which has been confirmed to operate normally and a defective product. Need to be kept.
[0005]
In addition, an electrical characteristic test for measuring an electrical characteristic of a manufactured semiconductor device is performed on a semiconductor device for the purpose of finding a defective product, making the characteristics uniform, or finding a defect that occurs over time. In burn-in for the purpose of detecting defects over time, etc., the circuit operation of the semiconductor device is performed for a certain period of time under a load such as a use condition such as a high temperature which is severer than the use condition of the customer, and the customer performs Defects that occur over time, which are problematic during use, are generated at an accelerated rate, and the cause of the temporal failure is found before shipment, and the initial failure of the product is eliminated.
[0006]
When performing a characteristic test or the like of such a semiconductor device, it is necessary to remove the semiconductor device after the test. Therefore, the semiconductor device is not fixedly mounted on a test board, but is housed in an easily attachable / detachable semiconductor device socket. Then, the semiconductor device is connected to a test board via a socket to perform the measurement.
[0007]
[Patent Document 1]
JP 2001-217054 A [Patent Document 2]
JP-A-7-32168
[Problems to be solved by the invention]
Patent Document 1 discloses an electrical component socket for detachably housing an individualized electrical component such as a semiconductor device, which is provided at an intermediate portion of a contact pin that contacts a terminal of the electrical component. A technique for urging a contact portion of a contact pin by a deformed portion and an auxiliary elastic member is described.
[0009]
In recent years, in a method of manufacturing a semiconductor device using a wiring board, in order to improve productivity, a plurality of manufacturing steps are collectively performed using a wiring board in which a plurality of device regions are connected as a member. Is used. In particular, by using a series of manufacturing methods of performing block molding using a sealing mold having a large cavity covering a plurality of device regions, and then cutting the wiring substrate and the sealing body with a dicing blade. In addition to improving the productivity in the encapsulation process, there are also advantages such as the ability to use the encapsulation mold for a plurality of types of products having different outer shapes, and to reduce the discarded area of the wiring board. . A method for manufacturing a semiconductor device with improved productivity by using the batch sealing step is called MAP (Multi Arrayed Packaging). However, in the case of using the socket described in Document 1, since the semiconductor device is tested in an individualized state, there is a problem that a decrease in productivity in a test process is inevitable.
[0010]
In addition to the miniaturization of the semiconductor chip, the miniaturization of the product outer shape is also being promoted. In a CSP (Chip Size Package) type, the size of the product outer shape is substantially the same as the semiconductor chip to be mounted. In order to reduce the size of the semiconductor device, the thickness of the semiconductor chip is reduced by polishing the back surface and the like, and the sealing body covering the semiconductor chip is also reduced, so that the strength of the semiconductor device is reduced. In addition, the area that can be used for fixing a semiconductor device is reduced due to miniaturization.
[0011]
For these reasons, a socket for accommodating a miniaturized semiconductor device requires a delicate mechanism for fixing the semiconductor device of the socket, and as the semiconductor device becomes smaller, the socket relative to the semiconductor device becomes smaller. Size will be larger on the contrary.
[0012]
For this reason, especially in a measurement involving heating such as a burn-in test, the number of test substrates that can be accommodated in the processing space is limited, and the number of processes increases due to an increase in the number of semiconductor devices to be measured. Since heating must be performed each time, the time required for measurement is greatly increased.
[0013]
Patent Document 2 describes a probe card used for electrical inspection of a semiconductor wafer, and in particular, to suppress thermal deformation of a printed circuit board due to a temperature change and maintain initial flatness of a needle tip of a needle. It discloses a technique that can be used.
[0014]
In electrical inspection of a semiconductor wafer, terminals such as probe needles that press against the electrodes of the semiconductor wafer are required to electrically connect the semiconductor wafer and the test head. Since the reliability of the contact with the electrode of the semiconductor wafer is ensured by the deformation, there is a problem that the portion is easily damaged during repeated use.
[0015]
Patent Literature 1 discloses a technique for improving the connection reliability of each probe needle by devising the shape of a probe card or the like. However, as the number of probe needles is increased, damage to a partial probe needle may be reduced. Since the possibility is high and it is difficult to repair only the probe needle damaged at this time, there is a problem that the entire probe card must be replaced.
[0016]
In addition, the scale or type of circuits to be mounted on a semiconductor chip has been expanded due to the higher integration of semiconductor elements, and more circuits or more multifunctional circuits are mounted by such high integration. Therefore, more pads are required for semiconductor devices. Due to such a reduction in the size of the semiconductor chip and an increase in the number of pads, the pads of the semiconductor device have been made finer and narrower.
[0017]
With the advance of miniaturization of pads, miniaturization of probes and increase in the number of pins are required.However, in the conventional probe card, a large number of individual probe pins made of tungsten, beryllium copper, etc. Due to the mechanical manufacturing method of electrically connecting the material fixed with resin etc. to the printed circuit board, it is difficult to miniaturize the probe card and increase the number of pins, and it is difficult to respond to the miniaturization of semiconductor devices Has become.
[0018]
In addition, since the area of the probe card required for the size of the semiconductor chip to be measured is large, it is difficult to realize a probe card having a sufficient number of pins for measuring the entire area of the wafer, and the cost of the probe card is high. When used for measurement in a mass production process, the cost required for measurement increases the product price.
[0019]
Further, in the conventional probe, since the amount of displacement in the Z direction perpendicular to the wafer is small because the elastic deformation of the needle-like metal is used, when the wafer is deformed such as warpage, the displacement of the probe causes Since the deformation cannot be absorbed and it is difficult to maintain the contact of the probe over the entire wafer, it is difficult to collectively test the entire semiconductor device formed on the large-diameter wafer.
[0020]
The object of the present invention is to solve these problems and form various semiconductor devices such as a semiconductor chip state or a sealed state in a state in which a plurality of wafers or the like before singulation are integrated. It is an object of the present invention to provide a technology that can collectively measure semiconductor devices.
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0021]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
A single or a plurality of contact pins are arranged and accommodated in a housing, and a tip of the single or a plurality of contact pins is disposed so as to protrude from an outer surface of the housing. A tip is slidable in a direction perpendicular to the outer surface of the housing.
Hereinafter, embodiments of the present invention will be described.
In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and repeated description thereof will be omitted.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
(Embodiment 1)
1A and 1B show a semiconductor device measuring probe according to an embodiment of the present invention, in which FIG. 1A is a partially longitudinal front view, FIG. 1B is a plan view, and FIG. 1C is a cross section along the line aa. It is a figure and (d) is mentioned later. In this probe 1 (test connection terminal), 20 contact pins 2 are fixed to a housing 3 made of a resin or the like and integrated, and this probe 1 is connected to a 20-pin semiconductor device in measurement of a semiconductor device. Corresponding to one-to-one correspondence, the respective contact pins 2 are arranged in accordance with the arrangement of the external terminals of the semiconductor device to be measured.
[0023]
The contact pin 2 is connected to the external terminal of the semiconductor device by a contact portion 4, an elastic portion 5 continuous with the contact portion 4, and connected to the elastic portion 5 and fixed to the substrate via the substrate wiring via the substrate wiring. The elastic portion 5 is elastically deformed when loaded in the Z direction as shown in FIG. 2, and urges the contact portion 4 by the repulsive force.
[0024]
The contact portion 4 has a rounded tip with an R. For example, in a measurement that involves a temperature change during heating or the like in a burn-in test, the tip of the contact portion 4 moves when the object to be measured is deformed due to thermal expansion. To prevent excessive stress from being generated in the contact portion 4. In addition, since the tip of the contact portion 4 moves smoothly, the natural oxide film formed on the surface of the external terminal to be measured can be removed by wiping, which makes a minute movement in the horizontal direction after the contact. Contact resistance between the terminal and the external terminal can be reduced.
[0025]
In addition, a locking portion 4a projects right and left at the end of the contact portion 4, and the locking portion 4a is locked to the housing 3 to make the amount of protrusion of the contact portion 4 uniform, and due to a processing error of the elastic portion 5 and the like. The protrusions of the contact portions 4 are prevented from being mismatched. The movement of the contact portion 4 in the X direction and the Y direction is restricted by the distal end portion 3 a of the housing 3. Further, the elastic portion 5 is configured such that the movement in the X direction and the Y direction is restricted by the side wall 3b of the housing 3 and an internal partition wall (not shown), thereby preventing contact with each other.
[0026]
In addition, when there is a convex portion or the like in the vicinity of the measurement target, the distal end portion 3a is desirably narrower than the side wall 3b in order to avoid the convex portion or the like. For this reason, in the examples shown in FIGS. 1 and 2, the side surface of the contact portion 4 of the contact pin 2 is partially exposed from the side surface of the contact portion 3 a of the housing 3. For example, as shown in FIG. A configuration may be adopted in which all side surfaces are covered with the distal end portion 3a of the housing 3 to protect the contact portion 4 and prevent accidental contact conduction of the contact portion 4.
[0027]
The elastic portion 5 is composed of arcuate deformed portions 5a alternately arranged at different positions in the X direction orthogonal to the load direction and a connecting portion 5b connecting the deformed portions 5a, and the elastic deformed portion 5a serving as a spring is formed. The contact portion 4 is displaced in the Z direction due to the elastic deformation of the contact pin 2, the contact portion 4 is urged by the repulsive force of the elastic deformation, and the contact portion 4 is pressed against the object to be measured, whereby the contact between the contact pin 2 and the object to be measured is brought into contact. To maintain.
[0028]
To increase the amount of displacement of the elastic portion 5 in the Z direction, it is conceivable to increase the diameter of the arc of the deformed portion 5a. However, this would increase the size of the contact pin 2 in the X direction. In the contact pin 2 of the embodiment, the size in the X direction is reduced by laminating the deformed portions 5a having elasticity in the load direction.
[0029]
The contact pins 2 are obtained by applying a gold plating to a metal sheet such as titanium copper or the like and pressing the metal sheet. As shown in FIG. It is cut along the outer shape of the region 60 and separated into contact pins 2. When the elastic portion 5 is formed by this processing, first, a portion corresponding to the inner periphery of the deformed portion 5a is punched out in a circular shape as shown in FIG. 4A, and then a connecting portion as shown in FIG. By punching the side edge of 5b into a rectangular shape having a width smaller than the circular diameter, the connecting portion 5b is wider than the deformed portion 5a, so that the strength of the connecting portion 5b is improved and Later deformation can be prevented.
[0030]
Further, since the connecting portion 5b has a thickness in the inward direction of the deformed portions 5a located at both ends thereof, the deformed portions 5a located at both ends are shifted inside the arc, respectively, and the deformed portion 5a is shifted in the Z direction. Therefore, the size of the elastic portion 5 in the Z direction can be reduced. In the present embodiment, the deformed portions 5a are stacked in nine stages, but if a larger displacement is required, it can be dealt with by stacking the deformed portions 5a in more stages.
[0031]
In the connecting portion 6, one end thereof is continuous with the elastic portion 5, and a groove corresponding to the side wall 3b of the housing 3 is formed in the middle, and the end of the side wall 3b of the housing 3 is fitted into this groove to connect the contact pin 2 to the groove. It is fixed to the housing 3. At the other end of the connection portion 6, a connection terminal 6a is provided offset from the side wall 3b of the housing 3.
[0032]
As shown in FIG. 1C, the connection terminal 6a has a press-fit structure in which a hole is provided at the center and the peripheral edge of the hole is slightly extended to facilitate elastic deformation. As the press-fit structure, as shown in FIG. 1 (d), other configurations such as deforming the cross section of the connection terminal 6a into an N-shape and elastically deforming the end can be adopted. .
[0033]
FIG. 5 is a plan view showing a probe substrate (mother board for electrical characteristic test) on which a plurality of probes 1 are mounted, and FIG. 6 is a longitudinal sectional view taken along line aa in FIG. The probe board 7 is a multilayer wiring board having five layers in the example shown in the figure. When the probe 1 is mounted on the probe board 7, the press-fit structure of the connection terminal 6 a is fitted into the through hole 7 a of the probe board 7. The contact pin 2 can be fixed to the probe board 7 by the elastic force.
[0034]
The through-hole 7a into which the connection terminal 6a is inserted is connected to the wiring 7b of each layer. In this example, the connection terminal 6aa is routed by the wiring 7b of the third layer from the bottom to conduct to the signal pad 8a. The terminal 6ab is routed by the second-layer wiring 7b from the bottom to conduct to the signal pad 8b, and the connection terminal 6ac is routed by the first-layer wiring 7b from the bottom to conduct to the signal pad 8c, and the connection terminal 6ad Are routed by the fourth-layer wiring 7b from the bottom to conduct to the signal pad 8d, and each wiring 7b is connected to the signal pad 8a, 8b, 8c, 8c formed at the end of the uppermost wiring 7b by the through hole 7a. The signal pads 8a, 8b, 8c and 8d are connected to a measuring device to measure a semiconductor chip or the like.
[0035]
As for the wiring of the wiring 7b, each wiring 7b can be independently drawn out, but if necessary, wirings that can be shared such as ground wiring, power supply wiring, address wiring, data lines, etc. are connected within the board. , Wiring 7b and signal pads 8a, 8b, 8c, 8d can be simplified.
[0036]
When attaching the probe 1 to the probe substrate 7, the press-in jig 9 shown in FIG. 7 is used, and the probe 1 is held by the elastic force of the press-in jig 9 as shown in FIG. However, since the connection terminal 6a is offset from the side wall 3b of the housing 3, the end of the press-fitting jig 9 directly contacts the connection terminal 6a. For this reason, it is possible to prevent a large force from being applied to the housing 3 when the probe 1 is attached. Therefore, even if the thickness of the housing 3 is reduced to make it compact, the elastic portion 5 or the contact portion 4 Can be prevented from being deformed.
[0037]
The connection terminal 6a penetrates the probe board 7, and the end of the connection terminal 6a protrudes to the opposite side. For this reason, when exchanging the probe 1 due to, for example, an operation failure due to breakage of the contact pin 2 or a decrease in connection reliability due to metal fatigue, the protruding portion is pushed as shown in FIG. 8B. As a result, the press-fit structure of the connection terminal 6a is pushed out from the through-hole 7a of the probe substrate 7, and the probe 1 is released, so that the probe 1 can be easily removed.
[0038]
In the case of simultaneously measuring a measurement object having a large area, a large number of probes 1 are attached to the probe substrate 7. For this reason, according to the connection terminal 6a of the present embodiment, when a malfunction occurs in some of the probes 1 and it becomes impossible to measure the whole at the same time, the defective probe 1 can be easily and quickly replaced. Therefore, it is possible to reduce the delay of the process.
[0039]
The contact pins 2 of the present embodiment are formed by processing a sheet material. When considering the planar arrangement of the contact pins 2, the width in the X direction is larger than the thickness of the sheet material, and the planar arrangement is the direction in the X direction. Depends on That is, by directing the wide portion of one contact pin 2 ′ in a direction shifted from the closest contact pin 2, the contact pins 2 can be arranged at a higher density.
[0040]
Specifically, as shown in (a) of FIG. 9, in the case of a so-called staggered arrangement in which the contact pins 2 are alternately shifted, the closest to one contact pin 2 '. Since the other contact pins 2 are positioned diagonally up and down, the contact pins 2 and 2 'are arranged in a horizontal direction, and as shown in FIG. 2B, the contact pins 2 are arranged along vertical and horizontal lines. In the case of a so-called lattice arrangement, the other contact pins 2 closest to one contact pin 2 ′ are located on the left, right, up and down, so that the contact pins 2 and 2 ′ are arranged obliquely. The contact pins 2 can be arranged with high density.
[0041]
FIG. 10 shows a modified example of the contact pin 2 used in the probe 1 of the present embodiment, and shows a front part and a side part of a main part by enlarging a part in the figure. In the above-described contact pin 2, the current flowing at the time of measurement flows in a meandering manner through all the deformed portions 5a and the connection portions 5b. For this reason, it is conceivable that the current flow path (wiring length) becomes longer and the inductance of the contact pin 2 increases.
[0042]
In order to reduce inductance, the contact pin 2 is provided with a projection 5c that becomes a short-circuit portion so as to face a part of the connecting portion 5b. As shown in FIG. Since the current flowing through the connecting portion 5b and the deformed portion 5a between the protrusions 5c flows between the protrusions 5c as a bypass, the current flow path can be shortened and the inductance can be reduced.
[0043]
As the short-circuit portion, as shown in FIG. 12, similarly to the other modified example, the protrusion 5c is replaced by a sloped surface 5d shown in FIG. 12B, and the elastic portion 5 shown in FIG. The height, which is the size in the Z direction, of the elastic portion 5 can be reduced by the configuration in which the opposing inclined surfaces 5d sometimes come into contact with each other and a current flows between the inclined surfaces 5d as a bypass.
[0044]
The above-described contact pin 2 has a configuration in which a press-fit structure is adopted for the connection terminal 6a and the contact pin 2 is fixed to the through hole 7a of the probe board 7 in order to facilitate attachment / detachment of the probe 1. As shown in FIG. 13, by connecting the connection terminals 6a of the contact pins 2 to the wiring 7a of the probe board 7 with solder 10 or the like, it is necessary to offset the connection terminals 6a from the side walls 3b of the housing 3. Since it is no longer necessary, the mounting area of the probe 1 can be reduced, so that the probe 1 can be more highly integrated. In addition, elimination of the through hole 7a for the contact pin 2 facilitates routing of the wiring 7b inside the probe substrate 7.
[0045]
In the above-described embodiment, the contact pins 2 are formed by pressing. However, when the contact pins 2 are processed by etching, more precise processing can be performed. Thus, the density of the probe 1 can be increased.
[0046]
In the probe board 7, the signal pads 8a, 8b, 8c, and 8d are formed at the ends of the wiring 7b. It is possible to adopt an appropriate form such as connection to a connector between boats. In addition, the probe board 7 includes a decoupling capacitor, a noise filter, a choke coil, a stabilized power supply, or the like for suppressing power supply spike noise caused by measurement of a large number of chips and power supply drop caused by simultaneous signal switching. It is also possible to adopt a configuration in which a component or circuit such as an attached power bus bar is mounted.
[0047]
In addition, the number of semiconductor chips formed on the wafer is increasing due to the increase in the diameter of the wafer and the miniaturization of the semiconductor chip. For this reason, when the number of semiconductor chips to be contacted simultaneously is large, the total contact pressure applied to the substrate at the time of contact may increase and the probe substrate 7 may be bent. For example, in a probe board 7 on which 300 20-pin probes 1 are mounted, if a load of 30 g is applied to each contact pin 2, a large load of 600 g per probe and a total weight of 180 kg is applied to the entire probe board 7.
[0048]
For this reason, it is conceivable that such a load cannot be tolerated only by the rigidity of the probe substrate 7, and in such a case, as shown in FIG. It is effective to attach a reinforcing structure 11 made of fiber reinforced plastic or aluminum, duralumin, magnesium alloy, iron, stainless steel, titanium, or the like having excellent heat resistance and creep resistance to the probe substrate 7.
[0049]
The reinforcing structure 11 is directly contacted with the connection terminals 6a protruding from the probe board 7 to prevent contact with components mounted on the probe board 7 or to ensure insulation of the wiring 7b and the like. May be formed. In addition, a through hole may be formed in the reinforcing structure 11 so as to match with a signal extraction terminal, a connector, a cable, and the like. When the reinforcing structure 11 is formed by a method such as aluminum die casting or magnesium alloy injection molding, such irregularities or through holes can be easily formed.
[0050]
(Embodiment 2)
Next, with respect to the semiconductor device manufactured by the MAP method shown in FIG. 15, a method of manufacturing the semiconductor device in which the probe 1 described above is used to perform collective measurement of the semiconductor device before singulation will be described.
[0051]
In this semiconductor device, the semiconductor chip 22 is mounted on each of a plurality of device regions 60 indicated by broken lines on the base substrate 21, and the bonding pads 23 of the semiconductor chip 22 and the bonding leads 24 formed on the base substrate 21 are bonded with bonding wires. The device mounting surface of the base substrate 21 is covered with a sealing body 26. The bonding lead 24 is connected to a through hole 28 penetrating the base substrate 21 by a wiring 27 formed in the base substrate. The through hole 28 is connected to one end of a wiring 29 on the back surface of the base substrate 21. The end is connected to the probe terminal 30.
[0052]
In the manufacture of the MAP type semiconductor device, a base substrate 21 and a semiconductor chip 22 whose element mounting surface (front surface) is shown in FIG. 17 and whose back surface is shown in FIG. 18 are prepared as shown in FIG. The base substrate 21 is formed by forming copper foil wirings 27 and 29 on a plate-like insulator such as a glass epoxy resin, and it is particularly preferable to cover the portions 24 and 30 to be electrodes by Ni-Au plating or the like. In this example, six semiconductor devices indicated by broken lines are simultaneously formed.
[0053]
First, as shown in FIG. 19, die bonding is performed in which the semiconductor chips 22 are mounted on the device regions 60 indicated by broken lines on the surface of the base substrate 21 (only two semiconductor chips 22 are bonded in the figure). ). Subsequently, as shown in FIG. 20, wire bonding is performed to electrically connect the bonding pads 23 of the mounted semiconductor chip 22 and the bonding leads 24 of the base substrate 21 with bonding wires 25 such as gold wires. (Only two semiconductor chips 22 are bonded in the figure)
[0054]
Subsequently, as shown in FIG. 21, the sealing bodies 26 of the respective semiconductor devices are integrally sealed by transfer molding using an epoxy resin or the like. The sealant of the runner and the gate portion, which are resin paths in transfer molding, are omitted in the drawings. As shown in the figure, a probe terminal 30 connected to a through hole 28 and a wiring 29 is formed on the back surface of the base substrate 21. As shown in FIG. 4 is brought into contact conduction, and collective measurement is performed on all the semiconductor devices before singulation.
[0055]
The probe terminal 30 can be used as an LGA (Land Grid Array) terminal of a semiconductor device, or a BGA (Ball Grid Array) terminal after a solder ball is mounted on the probe terminal 30 and subjected to solder reflow and flux cleaning. In particular, an LGA type semiconductor device used as a terminal in a state where a plating film or the like is formed on an electrode of a wiring board does not have a protruding electrode such as a solder ball on an electrode of the wiring board as compared with a BGA type semiconductor device or the like. Therefore, the necessity of applying a probe disclosed in the present invention as a probe for an electrical characteristic test is increased. This is because, in the LGA type semiconductor device, the electrode surface is almost flat because the electrode has a land shape, and a sufficient elastic deformation stroke of the contact pin is required to ensure the connection reliability between the probe and the electrode. Need to be secured. Therefore, by using the contact pin 2 to which the shape of the elastic portion 5 described in the above embodiment is applied, it is possible to sufficiently secure the connection reliability between the probe and the electrode even in the electrical characteristic test of the LGA type semiconductor device. Becomes possible.
[0056]
Thereafter, the semiconductor device shown in FIG. 15 is divided into individual pieces by dicing for cutting the base substrate 21 and the sealing body 26 at a time along the outer shape of the device region 60 shown by a broken line in FIG. Complete.
[0057]
In addition, since the wirings 27 and 29 are formed on the base substrate 21 by electroless plating, the wirings 27 and 29 are formed independently of each other. However, in the case of a base substrate formed by electrolytic plating, As shown in FIGS. 24 and 25, each wiring is electrically connected by a lead wire 29a to supply a potential to each electrode at the time of a plating process, and each wiring 29 And the lead wiring 29a are separated.
[0058]
For this reason, in order to perform the measurement before singulation, it is necessary to separate the lead wiring 29a and the respective wirings 29 prior to the measurement. As shown in FIG. 26, the back surface of the base substrate 21 is half-cut. The lead wiring 29a and each wiring 29 are separated and insulated. This back half cut is performed at a depth that can cut the wirings 29 and 29a formed by plating at a minimum, and the position of the half cut is set in accordance with the dicing line for singulation. FIG. 27 is a bottom view showing the semiconductor device after singulation. Lead wires 29a for adjacent semiconductor chips remain in a separated state, but no problem arises in use. The half-cut position does not necessarily need to be aligned with the dicing line as long as it does not affect actual use.
[0059]
(Embodiment 3)
Next, a description will be given of a method of manufacturing a semiconductor device in which a semiconductor chip formed on a wafer 31 shown in FIG. In particular, at this time, it is preferable to complete the test in a shorter time by applying an accelerated load to each semiconductor chip more than the load in actual use in order to reduce the time and cost required for the test. These tests are called aging tests. A plurality of semiconductor chips 32 having bonding pads 33 arranged along one side are arranged vertically and horizontally on the wafer 31 to be integrated.
[0060]
The bonding pads 33 formed on the semiconductor chip 32 are smaller in size than the contact portions 4 of the contact pins 2 described above, and the arrangement intervals thereof are also finer. For this reason, it is difficult to bring the contact pins 2 into direct contact with the bonding pads 33.
[0061]
Therefore, in the present embodiment, a conversion board (interposer) 34 which is a wiring board having terminals arranged at a larger pitch than the bonding pads 33 so as to be connected to the bonding pads 33 and conform to the arrangement of the contact pins. As shown in FIG. 29, the measurement is performed with the wafer 31 superimposed on the conversion substrate 34. Here, the part a in FIG. 29 is enlarged and shown in FIG. 30, and a longitudinal sectional view along the line aa ′ in FIG. 30 is shown in FIG.
[0062]
The conversion substrate 34 is a wiring substrate using glass epoxy or polyimide, and has slits 34a formed at intervals corresponding to the arrangement intervals of the semiconductor chips 32, and the bonding pads 33 of the semiconductor chip 32 are exposed to the slits 34a. . A measurement pad 35 corresponding to an external terminal of the semiconductor device is formed on the conversion board 34. One end of a wiring 36 formed on the conversion board is connected to the measurement pad 35, and the other end of the wiring 36 is connected to a bonding lead 37. It has become.
[0063]
First, the bonding leads 37 and the bonding pads 33 of the semiconductor chip 32 are connected by bonding wires 38. In this wire bonding, if a defective semiconductor chip such as a power supply short-circuit, a current consumption defect, an input / output characteristic defect, a function defect, or the like has been identified in advance by another inspection or the like, the corresponding semiconductor chip is not connected to a wire. Without bonding, the defective semiconductor chip 32 and the conversion board 34 are not connected, and are kept in a non-conductive state, so that only 100% of non-defective products can be measured. As a result, wasteful measurement can be reduced and the measurement can be made more efficient. In particular, it is effective to prevent the measurement terminal or the measurement circuit from being abnormally damaged due to an overcurrent or the like due to the defective semiconductor chip 32. is there.
[0064]
Subsequently, as shown in FIG. 31, the contact portion 4 of the contact pin 2 is brought into contact with the measurement pad 35 so as to make contact. The probes 1 are arranged on the probe substrate used for this measurement so as to correspond to the semiconductor chips 32, and the contact pins are arranged so as to correspond to the measurement pads 35 in each probe 1, so that the probe 1 is formed on the wafer 31. The semiconductor chips 32 can be measured simultaneously and collectively. When the measurement is completed, the bonding wire 38 is removed, the wafer 31 is removed from the conversion substrate 34, the wafer 31 is diced to separate the semiconductor chips 32, and the KGD determined to be good from the measurement result is selected.
[0065]
FIG. 32 is a longitudinal sectional view showing an example of an MCM type semiconductor device using the KGD thus selected. In this semiconductor device, a flash memory chip 42 is stacked and mounted on a base substrate 41 in two stages and a storage capacity is determined. Has been doubled. A bonding pad 43 for wire bonding is formed on one side of the flash memory chip 42. The bonding pad 43 and the bonding lead 44 of the base substrate 41 are connected by a bonding wire 45, and the bonding wire 45 and the base substrate 41 are connected. The semiconductor chip 42 and the external terminal 47 are electrically connected through the wiring 46 of FIG.
[0066]
The semiconductor chip to be measured includes, in addition to the test target circuit incorporated for the purpose of use of the semiconductor chip, a test pattern generator to be applied to the test target circuit, and an output pattern from the test target circuit. A test circuit such as a compressor for compression and a comparator for comparing a compressed output pattern with an expected output pattern is incorporated in the same semiconductor chip, and a BIST (Build In) for measuring a test target circuit using these test circuits. There is a semiconductor chip adopting a Self Test (Self Test) method.
[0067]
The JTAG (Joint Test Action Boundary Scan Architecture) test, which is an example of the BIST, is a boundary scan test method (IEEE Standard Test Access Guide) that was standardized in 1990 as IEEE1149.1. In this test method, Vcc and Vss as a power supply, TCK of a clock signal, TDI for sampling at the rising edge of the clock signal and serially inputting an instruction or data to a test target circuit, and determining the output value at the falling edge of the clock signal and testing. A TDO that serially outputs data from a target circuit, a TMS (Test Mode Select) that samples at rising edges of a clock signal and controls a test operation, and a sequential circuit (state machine) that controls a boundary scan register using the TMS signal and the clock signal. Signal terminals of TAP (Test Access Port) for decoding the TMS signal and / TRST, which is a negative logic option signal for asynchronously initializing the TAP controller, are required.
[0068]
As described above, according to the BIST, measurement can be performed by connecting a small number of terminals required for measurement to the measurement device, and it is not necessary to connect all terminals. Therefore, unlike the above-described semiconductor chip 32, as shown in FIG. 33, the semiconductor substrate 32 having a large number of bonding pads 33 formed on four sides is also used to convert the conversion substrate 34 to the state of the wafer 31 in the same manner as described above. The measurement can be carried out.
[0069]
When measuring the wafer 31 on which the semiconductor chip incorporating the BIST is formed, as shown in FIG. 34, the bonding pads 33 of the necessary signal terminals required for the above-described measurement are attached to one side of the semiconductor chip 32. By arranging, by exposing this one side from the slit 34a of the conversion board 34, all signal terminals required for measurement can be connected by the slit.
[0070]
A 12-pin measuring pad 35 and a wiring 36 having one end connected to the measuring pad 35 and the other end connected to the bonding lead 37 are formed on the conversion board 34 in correspondence with the semiconductor chip 32. The bonding leads 37 of the wiring 36 required for internal measurement and the bonding pads 33 of the semiconductor chip 32 required for measurement exposed on the slit 34a are connected by bonding wires 38, and the other measurement pads 35 may be set as NC.
[0071]
If a defective semiconductor chip such as a power supply short-circuit, a current consumption defect, an input / output characteristic defect, a function defect, or the like has been identified in advance by another inspection or the like, the connection between the defective semiconductor chip and the conversion board 34 is made. Without conducting, it is possible to measure the total number of non-defective products only. As a result, unnecessary measurement can be reduced and the measurement can be made more efficient. In particular, it is effective to prevent a measurement terminal or a measurement circuit from being abnormally damaged due to an overcurrent or the like due to a defective semiconductor chip. .
[0072]
In the measurement, the contact portions 4 of the contact pins 2 are brought into contact with the measurement pads 35 of the conversion substrate 34 so that all the semiconductor chips 32 formed on the wafer 31 can be measured simultaneously and collectively. As described above, even when many bonding pads 33 are arranged on the four sides of the semiconductor chip 32 shown in FIG. 33, the measurement of the semiconductor chip 32 can be performed in the same manner as described above.
[0073]
Here, the BIST has been described using JTAG as an example. However, the present embodiment is not limited to this method, and the present embodiment can be generally applied to a case where measurement is performed using only a specific bonding pad. If a signal necessary for measurement cannot be secured only by the bonding pads 33 arranged on one side of the semiconductor chip 32, the bonding pads 33 are formed on the other side which is opposed to the one side and similarly exposed from the slit 34a. The bonding pad obtained may be used for the measurement.
[0074]
(Embodiment 4)
Next, a description will be given of a method of manufacturing a semiconductor device in which a semiconductor device formed by WLP on the wafer 31 shown in FIG. A plurality of semiconductor chips 32 having bonding pads 33 shown in FIG. 35 arranged along one side are arranged vertically and horizontally on the wafer 31 to be integrated.
[0075]
FIG. 36 is a plan view and a bottom view showing a base substrate 51 used in this semiconductor device. In the base substrate 51, a copper foil wiring 52 is formed on a plate-shaped insulator such as a glass epoxy resin by plating or the like, and the semiconductor chip connection surface of the base substrate 51 corresponds to the bonding pad 33 of the semiconductor chip 32. And a wiring 52 having one end connected to the bonding lead 53 and the other end connected to a through hole 54, the through hole 54 penetrates the substrate 51, and the through hole 54 A wiring 52 is formed, one end of which is connected to the other end and the other end of which is connected to a 12-pin external pad 55. The base substrate 51 has the same shape as the semiconductor chip 32, and the same number of the semiconductor chips 32 in the wafer 31 state And correspondingly.
[0076]
As shown in a longitudinal sectional view in FIG. 37, the semiconductor chip 32 in the wafer state and the base substrate 51 are adhered by an underfill adhesive 56, and the bonding pads 33 of the semiconductor chip 32 and the bonding leads 53 of the base substrate 51 are Are connected by bumps 57 made of gold or the like. In this state, in order to measure the semiconductor chips 32 on the whole wafer before singulation, the probe 1 having the contact pins 32 corresponding to the arrangement of the external pads 55 on the base substrate 51 is used in the same manner as the arrangement of the semiconductor chips 32. All the semiconductor chips 32 formed on the wafer 31 are simultaneously measured simultaneously by arranging them on the probe substrate and bringing the contact portions 4 of the contact pins 2 of the probe 1 into contact with the external pads 55 on the bottom surface of the base substrate 51.
[0077]
If a defective semiconductor chip 32 such as a power supply short-circuit, a current consumption defect, an input / output characteristic defect, a function defect, or the like is specified in advance by another inspection or the like, the bump 57 is formed on the corresponding semiconductor chip 32. Instead, the defective semiconductor chip 32 and the base substrate 51 are not connected to each other and are in a non-conductive state, and the total number of non-defective products can be measured. As a result, wasteful measurement can be reduced and the measurement can be made more efficient. In particular, it is effective to prevent the measurement terminal or the measurement circuit from being abnormally damaged due to an overcurrent or the like due to the defective semiconductor chip 32. is there.
[0078]
The connection between the bonding pad 33 of the semiconductor chip 32 and the bonding lead 53 of the base substrate 51 is performed by using another flip chip connection such as a silver paste, an anisotropic conductive paste, or an anisotropic conductive film in addition to the bump 57. It is also possible to adopt a technique, in which the formation of the through-hole 54, the external pad 55, and the wiring 52 is performed by using an LSI wiring forming process of forming a copper wiring covered with a barrier metal on an insulating film such as polyimide. It is also possible.
[0079]
As described above, the present invention has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and it is needless to say that various modifications can be made without departing from the scope of the invention. It is.
[0080]
For example, in the electric characteristic test in each of the above embodiments, the example in which the electric characteristic test is performed at a stage before the singulation process has been described. Since the test process can be simplified, an electrical characteristic test may be performed after division for individualization, for example, after a dicing process, and even in such a case, the electrical characteristics test may be performed on the probe substrate (motherboard). It is preferable to arrange semiconductor devices or semiconductor chips singulated so that they can be connected collectively to a plurality of probes.
[0081]
Specifically, although not shown, in the second embodiment, after a dicing process for singulating the semiconductor devices, the plurality of singulated semiconductor devices are arranged in a tray, A characteristic test can be performed.
Although not shown, in the third embodiment, after the dicing step for singulating the semiconductor chips, an electrical characteristic test is performed in a state where the singulated semiconductor chips are arranged on a tray. You can do it.
[0082]
【The invention's effect】
The effects obtained by the typical inventions among the inventions disclosed in the present application will be briefly described as follows.
(1) According to the present invention, there is an effect that a probe can be constituted by a contact pin and a housing which are integrally processed.
(2) According to the present invention, the effect (1) has an effect that the cost of the probe can be reduced.
(3) According to the present invention, there is an effect that a sufficient amount of displacement can be obtained by stacking the deformed portions by the effect (1).
(4) According to the present invention, the effect (1) has an effect that the contact pin can be downsized and the density of the probe can be increased.
(5) According to the present invention, there is an effect that measurement can be performed collectively in a wafer state or a state in which a plurality of semiconductor devices are integrated, such as a MAP semiconductor device before singulation.
(6) According to the present invention, due to the effect (5), the time required for measurement can be reduced, and the cost required for measurement can be reduced.
[Brief description of the drawings]
1A and 1B show a semiconductor device measuring probe according to an embodiment of the present invention, in which FIG. 1A is a partially longitudinal front view, FIG. 1B is a plan view, and FIGS. FIG.
FIG. 2 is a longitudinal sectional view showing a probe in a weighted state.
FIG. 3 is a front view showing a contact pin in a manufacturing process.
FIG. 4 is a partially enlarged view illustrating processing of a contact pin.
FIG. 5 is a plan view showing a probe board on which a plurality of probes are mounted.
FIG. 6 is a longitudinal sectional view taken along line aa in FIG.
FIG. 7 is a front view showing the press-fitting jig.
FIG. 8 is a longitudinal sectional view for explaining attachment and detachment of a probe.
FIG. 9 is a partial plan view showing the arrangement of contact pins.
FIG. 10 is a front view and a partially enlarged view showing a modified example of a contact pin.
FIG. 11 is a front view and a partially enlarged view showing a modified example of a contact pin.
FIG. 12 is a partially enlarged view showing another modification of the contact pin.
FIG. 13 is a longitudinal sectional view showing a modified example of probe attachment.
FIG. 14 is a longitudinal sectional view showing a probe board to which a reinforcing structure is attached.
15A and 15B are a plan view and a bottom view showing a semiconductor device manufactured by a MAP method.
FIG. 16 is a diagram showing a flow of manufacturing a MAP type semiconductor device.
FIG. 17 is a plan view showing a base substrate used for manufacturing a MAP type semiconductor device.
FIG. 18 is a bottom view showing a base substrate used for manufacturing a MAP type semiconductor device.
FIG. 19 is a plan view showing a MAP-type semiconductor device manufacturing for each process.
FIG. 20 is a plan view showing a step of manufacturing a MAP-type semiconductor device;
FIG. 21 is a plan view showing a MAP type semiconductor device manufacturing process for each process.
FIG. 22 is a longitudinal sectional view showing collective measurement of a MAP type semiconductor device.
FIG. 23 is a plan view showing a step of manufacturing a MAP type semiconductor device;
FIG. 24 is a plan view showing another base substrate used for manufacturing a MAP type semiconductor device.
FIG. 25 is a longitudinal sectional view of another base substrate shown in FIG. 24;
FIG. 26 is a vertical cross-sectional view showing the manufacture of a semiconductor device using the another base substrate.
FIG. 27 is a bottom view showing a semiconductor device using the other base substrate.
FIG. 28 is a plan view showing a wafer and semiconductor chips.
FIG. 29 is a plan view showing a conversion substrate.
FIG. 30 is a partially enlarged view showing a part a in FIG. 29;
FIG. 31 is a partial vertical sectional view showing batch measurement of a semiconductor device in a wafer state.
FIG. 32 is a longitudinal sectional view showing an MCM type semiconductor device.
FIG. 33 is a plan view showing a wafer and semiconductor chips.
FIG. 34 is a partially enlarged view showing a wafer and a conversion substrate.
FIG. 35 is a plan view showing a semiconductor chip used for manufacturing a semiconductor device of the WLP method.
36A and 36B are a plan view and a bottom view showing a base substrate used for manufacturing a semiconductor device of a WLP method.
FIG. 37 is a partial vertical cross-sectional view showing batch measurement of a WLP-type semiconductor device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Probe, 2 ... Contact pin, 3 ... Housing, 3a ... Tip part, 3b ... Side wall, 4 ... Contact part, 4a ... Locking part, 5 ... Elastic part, 5a ... Deformed part, 5b ... Connection part, 5c ... Projecting portion, 6 connecting portion, 6a connecting terminal, 7 probe board, 7a through hole, 7b wiring, 8a, 8b, 8c, 8d signal pad, 9 press fitting jig, 10 solder, 11 ... Reinforcement structure 21, 41, 51 base board, 22, 32, 42 semiconductor chip, 23, 33, 43 bonding pad, 24, 37, 44, 53 bonding lead, 25, 38, 45 bonding wire , 26 ... sealing body, 27, 29, 36, 46, 52 ... wiring, 29a ... lead-out wiring, 28, 54 ... through hole, 30 ... probe terminal, 31 ... wafer, 32 ... semiconductor chip, 33 ... Bonn Ingupaddo, 34 ... conversion substrate, 34a ... slit, 35 ... measurement pad, 47 ... external terminal, 55 ... external pad, 56 ... underfill adhesive 57 ... bumps 60 ... device region.

Claims (6)

A single or a plurality of contact pins are arranged and accommodated in a housing, and a tip of the single or a plurality of contact pins is disposed so as to protrude from an outer surface of the housing. A probe for measuring a semiconductor device, wherein a tip portion is slidable in a direction perpendicular to the outer surface of the housing. The contact pin includes a contact portion that comes into contact with the object to be measured, an elastic portion that is continuous with the contact portion, and a connection portion that is connected to the substrate and is continuous with the elastic portion.
The elastic portion includes an arc-shaped deformed portion alternately arranged in the load direction and a connecting portion connecting the deformed portions, and the contact portion is measured by the elastic deformation of the deformed portion serving as a spring. The probe for measuring a semiconductor device according to claim 1, wherein the probe is pressed. The probe for measuring a semiconductor device according to claim 2, wherein a width of the connecting portion is wider than that of the deformed portion. In the connecting portion, the width is increased by increasing the thickness in the inward direction of the arc of the deformed portion located at both ends thereof, and the deformed portions located at both ends are shifted inside the arc, respectively. The probe for measuring a semiconductor device according to claim 3. 2. The probe for measuring a semiconductor device according to claim 1, wherein the connection portion is provided with a connection terminal having a press-fit structure. 6. The probe according to claim 5, wherein the connection terminal having the press-fit structure is provided offset from a side wall of the housing.

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