KR0125970B1 - Test socket for known-good die - Google Patents

Abstract

a rectangular bottom socket where several built-in pads and contact pads are formed; semiconductor chips installed on the built-in pads; wires connecting contact pads to the bonding pads of the semiconductor chip; an upper socket fixed with a fixing means on top of the bottom socket; contact terminals installed through the upper socket in order to be contacted with contact pads; a penetration hole forming a space which the semiconductor chip can occupy, being formed on the center of the upper socket; a through hole formed adjacent to the penetration hole; and input/output pads connected to contact terminals by a metal line and formed on one side of the upper socket.

Description

Test Sockets for Known Good Die Arrays

1 is a cross-sectional view of one embodiment of a test socket for a known good die array according to the present invention.

The present invention relates to a test socket for a Known Good Die (KGD) array, which is an unbonded bare chip that has been fully tested, and more specifically, a wafer using a conventional semiconductor manufacturing process. The present invention relates to a test socket for a KGD array capable of mass-producing KGD by carrying out electrical and burn-in tests of a plurality of semiconductor chips separated from the circuit.

In general, after the semiconductor chip is manufactured, various tests are performed to confirm the reliability of the product. The test is an electrical test that connects all the input and output terminals of the semiconductor chip with the test signal generation circuit and tests the normal operation, and connects several input and output terminals such as the power input terminal of the semiconductor chip with the test signal generation circuit to generate a higher temperature than the normal operating condition. In addition, there is a burn-in test that checks a semiconductor chip for life and defects by applying stress at high voltage. For example, in the case of DRAM, defective memory circuits, memory cells and wirings are usually checked.

As a result, a semiconductor chip that is likely to cause a certain disturbance when used in a steady state will necessarily cause such a defect in burn-in test, for example, breakdown of the insulating film of the gate oxide film. Therefore, during the burn-in test, defective chips are detected and removed before shipment to ensure product reliability.

However, in the state of the normal semiconductor chip separated from the wafer, the electrical connection with the test signal generating circuit is difficult, so that electrical and burn-in tests are almost impossible. Therefore, electrical and burn-in tests are usually performed in a state where the semiconductor chip is packaged in a molding compound. Here, an outer lead connected to the chip pad protrudes from the sidewall of the package. After inserting the external leads of the semiconductor package into a test socket having a socket hole into which the external leads can be inserted, the test socket is mounted on the burn-in board again to perform burn-in test.

However, the semiconductor package as described above has a limitation in high-density mounting, so in recent years, a multi-chip using a flip chip that directly mounts a plurality of bare chips on a ceramic board without using a single chip package is used. chip) technology has been developed, a number of integration methods have been proposed that can achieve high speed, high capacity, small size and large-scale integration. One representative method of these is a multi chip module (hereinafter referred to as MCM). The MCM can obtain ultra-high density by embedding a plurality of semiconductor chips interconnected on a multi-ceramic board having high-density wiring therein. Currently, the MCM has been successfully applied to a super computer by IBM, NEC, Hitachi, etc. Is being applied. However, the MCM is technically and economically restricted for the following reasons. That is, MCM in which a plurality of semiconductor chips are embedded compared to the conventional single-chip package technology has a large integration scale, but the production yield is significantly reduced and the production cost is greatly increased, making it difficult to secure a sufficient market for MCM. In particular, the most difficult problem of the MCM is the sufficient security of KGD, which is directly related to production yield, the test is completed and the same degree of reliability as in the conventional packaging technology is recognized.

Despite the growing awareness of the importance of KGD applied to MCM, there is a significant disadvantage in mass production of low-cost KGD. That is, since a single bare chip separated from a wafer has no external lead, a test socket applied to the semiconductor package test cannot be used, and electrical and burn-in tests cannot be performed before being installed on a printed circuit board in a bare chip state. There is this.

As a technology to solve this problem, a flip chip test socket adapter for enabling electrical and burn-in tests in a bare chip state in which solder bumps are formed on each bonding pad of the chip is provided in the United States of America. Patent No. 5,006,792. The flip chip test socket adapter forms solder bumps on a bonding pad of a semiconductor chip, and then inserts the solder bumps into a dedicated adapter for testing. The test socket adapter includes a substrate on which cantilever beams are formed to correspond to solder bumps of a semiconductor chip to be inserted. The substrate is housed in a case, and input / output terminals protruding out of the case are inserted on a burn-in board to perform a burn-in test. The semiconductor chip using the test socket adapter of the above configuration enables the test in the bare chip state before the package.

However, the prior art has to perform electrical and burn-in tests in a bare chip state in which bumps, which are metal protrusions, are formed on each bonding pad of a single semiconductor chip separated from a wafer. The process of forming bumps on the bonding pads of a single semiconductor chip requires expensive equipment requiring high precision due to the fine pitch between the bonding pads due to high integration. In addition, there is a problem in that chip handling becomes difficult because the individual semiconductor chips must be dealt with during the test.

Therefore, the KGD manufacturing method according to the prior art forms a solder bump on a bonding pad of a semiconductor chip, mounts each semiconductor chip in a dedicated test socket, and then performs a small amount of electrical and burn-in tests. Compared with the packaged semiconductor package, there is a problem that the unit price is very high. In addition, a single semiconductor chip is very difficult to handle, and a conventional test socket has a problem in that a complex structure is very difficult to manufacture.

In order to solve the above problems, according to the KGD array and the manufacturing method disclosed in the patent application No. 93-5769 filed by the applicant of the Korean Patent Office, it is possible to easily obtain a large amount of KGD.

In addition, a test socket capable of producing a large amount of KGD using the above-described lead frame and array manufacturing method is disclosed in Korean Patent Application No. 93-11670 filed with the Korean Intellectual Property Office.

The conventional test socket for the KGD array includes a plurality of die pads which are supported by tie bars and arranged regularly, and an insulating tape which is formed at regular intervals around each of the die pads and attached to an upper side of the die pads. A lead frame for a KGD array having leads supported by and shorted to the outside; Semiconductor chips mounted on the die pad; Wires connecting one side of the leads to bonding pads of the semiconductor chip; A rectangular lower socket on which the lead frame of the structure is mounted; An upper socket fixed by fixing means on an upper side of the lower socket; Contact terminals provided at regular intervals on the lower surface of the upper socket so as to be in contact with the other sides of the leads of the lead frame mounted on the lower socket; It is formed on one side of the upper socket, and consists of input and output pads connected by the contact terminals and the metal wiring. Therefore, since the tie bar can be cut after being supplied to the buyer, handling of the chip unit is very easy, and KGD can be easily classified into wire bonding, flip chip, etc. according to the buyer's request. In particular, it is possible to mass-produce defect-free KGDs by conducting electrical and burn-in tests with ordinary semiconductor chips, thereby reducing the cost of KGDs. On the other hand, after fabricating a printed circuit engine, there is a problem in that contact terminals are mounted on the printed circuit board, and wires connected between chips and leads are easily damaged.

Accordingly, an object of the present invention is to provide a test socket capable of mass testing of the entire KGD array, in which a plurality of semiconductor chips are mounted on the KGD lead frame, for mass removal of KGD, which is easily removable and guarantees reliability of semiconductor devices. In providing.

Features of the test socket for KGD array according to the present invention for achieving the above object is a rectangular lower socket formed with a plurality of mounting pads and contact pads; Semiconductor chips mounted on the mounting pads; Wires connecting the contact pads to the bonding pads of the semiconductor chip; An upper socket fixed by fixing means on an upper side of the lower socket; Contact terminals provided at regular intervals through the upper socket so as to contact pads formed in the lower socket; A through hole formed in a center of the upper socket to form a space occupied by the semiconductor chip; A through hole formed to be bent adjacent to the through hole; It is formed on one side of the upper socket, and is composed of input and output pads connected by the contact terminals and the metal wiring.

Hereinafter, a preferred embodiment of a test socket for a KGD array according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view showing one embodiment of a test socket for a KGD array according to the present invention.

Referring to FIG. 1, the upper and lower sockets 11 and 12 having a rectangular shape are formed of an insulating material, for example, ceramic or plastic, and the upper and lower sockets are formed on both sides of the upper socket 11. A plurality of pads 14 to be electrically and burn-in tested on the lower socket 12 are fixed by fixing means 15 such as a plurality of screws or insertion pins so that the sockets 11 and 12 can be attached and detached. The pads 14 are formed of a mounting pad 14a for mounting the semiconductor chip 13 and contact pads 14b for wire bonding and testing the semiconductor chip 13. have.

The upper socket 11 is provided with contact terminals 16 at positions corresponding to the contact pads 14b through upper and lower portions, and the contact terminals 16 are connected to the contact pads 14b. This allows you to free up space for installation. In addition, the contact terminal 16 is connected to a conductive material such as copper, aluminum, or silver that penetrates up and down the substrate, and a bump 16a protrudes, thereby being connected to the contact pad 14b. Isocon (isocon) terminal suitable for the, the bump (16a) can be formed in a diameter of about 0.6 ~ 1.0mm and a height of about 0.5mm. A nickel (Ni) plated film having a thickness of about 1.0 to 2.0 μm is formed on a surface of the bump 16a, and a gold plated film having a thickness of about 0.3 μm to 0.5 μm is formed on a surface of the nickel plated film. Plating uses electroplating or electroless plating. In addition, a rectangular through hole 17 is formed at the center of the upper socket 11 and has a space that can be sufficiently occupied by the semiconductor chip 13 and the wire 22 to be tested. The lower portion of the semiconductor chip 13 and the wire 22 is wider so that the upper socket 11 is not in contact with the semiconductor chip 13 and the wire 22. As semiconductor chips become more integrated, the width of the lower portion needs to be wide enough to accommodate all the semiconductor chips, and the width may be limited to improve the test efficiency. In addition, a plurality of through holes 17a are bent along the bends of the through holes 17 in the periphery of the through holes 17 formed in the upper socket 11, so that the through holes 17 are formed. It is intended to meet the shape of. In addition, inside the through hole 17a, a metal having excellent conductivity such as gold, copper, silver, aluminum, or the like is plated in a cylindrical or cylindrical shape by an electroless plating method or an electroplating method, and thus formed on upper and lower portions of the upper socket 11. Connect them electrically. In addition, the upper socket 11 has a tab terminal 18 for electrical connection with an external burn-in board or an electrical test board on one side, and input / output pads 19 are formed on the surface of the tab terminal 18. The input / output pads 16 are made of metal wires, such as aluminum, copper, silver, and gold, which are formed in one or multiple layers. The semiconductor chip 13 is bonded by an adhesive 24 on the mounting pad 14a on the lower socket 12, and the balls 21 are formed on the semiconductor chip 13 by the wire 22. It is electrically connected with the contact pad 14b.

Hereinafter, the burn-in process by a test socket is demonstrated.

First, the semiconductor chip 13 is adhered with an adhesive 24 on the mounting pad 14a formed on the lower socket 11, and the wire 22 is formed on the semiconductor chip 13. It is electrically connected to the pad 14b for contacting and fixed on the lower socket 12. Next, the bump 16a of the contact terminal 16 during the burn-in process by fixing the lower socket 12 by a fixing means 15 made of an insertion pin or a screw formed on one side of the upper socket 11. The contact failure between the contact pads 14b is prevented and the flow of the lower socket 12 is prevented. At this time, the semiconductor chip 13 and the wire 22 are accommodated in the through hole 17 formed in the upper socket 11. After setting as above, electrical test or burn-in test is performed collectively. After identifying the KGD and the defective chip on the burned-in test semiconductor chip 13, the wire 22 is cut off only the balls 21 of the defective chip, the adhesive 24 is removed, and the lower socket 12 is removed. ) Is used again, or the KGD mounted on the mounting pads 14a of the lower socket 12 is shipped in an array state.

As described above, in the test socket for the nodule die array, which is composed of the upper and lower sockets, there is no need for a separate socket support, so that the structure is simplified, and damage to the wire is prevented by a through hole formed in the upper socket. The bump is plated with a material having excellent conductivity, corrosion resistance, and abrasion resistance, so that the life of the socket can be extended. In addition, since multiple semiconductor chips are simultaneously mounted and burned-in tests are carried out in batches, it is possible to produce a large number of known good dies, thereby reducing the test cost, which accounts for a large part of the known good die production cost, to reduce the production cost of the known good dies. There is a significant savings effect. In addition, multi-chip modules with high mounting density can be easily manufactured at low cost, which can be applied to general personal computers as well as supercomputers.

Claims (4)

A test socket for a known good die array, comprising: a rectangular lower socket having a plurality of mounting pads and contact pads; Semiconductor chips mounted on the mounting pads; Wires connecting the contact pads to the bonding pads of the semiconductor chip; An upper socket fixed by fixing means on an upper side of the lower socket; Contact terminals installed at regular intervals through the upper socket to contact the pads for contact formed on the lower socket; A through hole formed in a center of the upper socket to form a space occupied by the semiconductor chip; A through hole formed to be bent adjacent to the through hole; A test socket for a known good die array formed on one side of the upper socket and configured as input / output pads connected to the contact terminals by metal wiring. The test socket according to claim 1, wherein the through hole has a cross-sectional area of a lower portion greater than that of an upper portion. The test socket for hard die array according to claim 1, wherein the fixing means comprises a screw or an insertion pin. The test socket according to claim 1, wherein the contact terminal has bumps plated with nickel and gold at the bottom thereof.