KR950012291B1 - Test socket and known good die - Google Patents

Abstract

The test socket has multiple external connection terminals(22) on one side end of a substrate(21). The external connection terminals(22) are connected to an external burn-in test substrate. A land pattern (23) is formed in the center which is connected to the external connection terminals(22) through individual metal wiring with a fixed space between them. A semiconductor chip (25) having an equal number of bump eletrodes (26) in the bottom surface is mounted in the upper part of the land pattern(23) formed in the center of the substrate(221). The test socket is used for long period, reliability of semiconductor chip is maintained, and damage to bonding pad is prevented.

Description

Test socket and manufacturing method of know good die using the same

1 is a main part micrograph of a known good die array using a conventional tap method.

2 is a micrograph of a test socket for a known good die used in a conventional tap method.

3 is a micrograph of a main portion of a known good die array using a conventional thin film contact probe method.

4 is a known good die array manufacturing method using a conventional temporary packaging method,

4A is a cross-sectional view of a known good die array provided by a test housing.

FIG. 4B is a micrograph of the bonding pad of the known good die array of FIG. 4A.

5 is an exploded perspective view of a test socket for a know good die array according to the present invention.

6 is a cross-sectional view taken along line VV ′ of FIG. 5.

7 is a cross-sectional view showing a known good die manufacturing process according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a known good die manufacturing method using a test socket, and more particularly, to a plurality of semiconductor chips separated from a wafer and formed with bumps using a conventional semiconductor manufacturing process. The present invention relates to a test socket capable of producing a large quantity of a good good die, a bare bare chip, in which bumps remain after a test is completed, and a method for manufacturing a known good die using the same. .

In general, after the semiconductor chip is manufactured, various tests are performed to confirm the reliability of the product. The test is an electrical test for normal operation and disconnection by connecting all input / output terminals of the semiconductor chip with a test signal generation circuit, and normal operation by connecting some input / output terminals such as a power input terminal of the semiconductor chip with a test signal generation circuit. There is a burn-in test that checks the lifetime and defects of semiconductor chips by applying stress at temperatures, voltages, and currents higher than the conditions. For example, in the case of DRAM, there is a burn-in test method for checking defective memory circuits, memory cells, wirings, and the like.

As a result, such defects that are likely to cause some obstacle when the semiconductor chip is used in the normal state during burn-in test, for example, breakdown of the insulating film of the gate oxide film, etc. necessarily occur. The burn-in test therefore ensures the reliability of the product by detecting defective chips during testing and removing them before shipment.

However, in the normal bare chip state separated from the wafer, the electrical connection with the test signal generating circuit is difficult, so that electrical and burn-in tests are almost impossible. Therefore, electrical and burn-in tests are generally performed in a state of being packaged with a semiconductor chip molding molding member, for example, an epoxy molding compound (hereinafter, referred to as EMC).

Here, the basic type of the semiconductor package is a semiconductor chip that has not been tested on the die pad, the bonding pads of the chip and one side of the leads are connected by a wire, the semiconductor surrounding the chip and the wire to protect The body of the package is formed. The outer leads protruding from the outside of the semiconductor package body, the outer leads protruding from the leads, and inserting the outer leads of the semiconductor package into a test socket having a socket hole into which the outer leads can be inserted, then reinsert the test socket. Burn-in test is performed by mounting on the burn-in test board.

However, the semiconductor package as described above has a limitation in high-density mounting, and thus, in recent years, a multi-chip using a flip chip that directly mounts a plurality of bare chips on an insulated ceramic substrate without using a semiconductor package directly. Multi chip manufacturing technology has been developed, and many semiconductor chip integration methods have been proposed that can achieve high-speed, high-capacity, small-scale, and large-scale integration. One representative method of these is a multi chip module (hereinafter abbreviated as MCM).

The MCM is capable of obtaining very large scale intergration by embedding a plurality of connected semiconductor chips, and has been successfully applied to supercomputers by IBM, DEC, Hitachi, and the like.

However, the MCM is limited technically and economically for the following reasons, i.e., compared to the conventional single semiconductor chip packaging technology, an MCM in which a plurality of semiconductor chips are embedded has a large integrated scale, but has a significantly lower production yield. There is a problem that the cost is very high, it is difficult to secure sufficient market of MCM.

In particular, the most difficult problem of the MCM is that it is difficult to sufficiently secure the known good die, which is directly related to the production yield, the test is completed and the high accuracy reliability is recognized as in the conventional packaging technology.

Despite the growing awareness of the importance of known good dies applied to MCMs, there are significant difficulties in mass production of low cost good dies. Because the single bare chip separated from the wafer does not have external leads, it is impossible to use the test socket applied to the semiconductor package test, and before the bare chip is installed on the printed circuit board (abbreviated as PCB) in the bare chip state. There is a problem in that electrical and burn-in tests are not possible.

Techniques to solve this problem include hot chuck probe method, tape automated bonding (TAB) method, thin film contact probinf method, and flip chip test socket adapter. Various methods have been developed, such as using an adapter, a wafer level test method, and a known good die manufacturing method provided by a test housing.

Although these methods have their advantages, they all have disadvantages in terms of reduction in manufacturing cost for mass production of known good dies.

These methods are outlined as follows.

First, the hot chuck probe method is a method of performing a test after contacting a hot chuck probe having terminals capable of contact with bonding pads of a bare chip in a wafer state to a bonding pad of a chip. There is an additional process is unnecessary, there is an advantage that can be supplied to the consumer in the state of the wafer, but it takes a lot of time for the test, there is a problem that the manufacturing cost is increased because a separate hot chuck probe to be manufactured for other types of semiconductor chips.

FIG. 1 is a photomicrograph of a main part of a known good die array using a conventional tap method, and FIG. 2 is a photomicrograph of a test socket for a known good die used in a conventional tap method.

In the tap method, as shown in FIG. 1, a semiconductor chip cut from a wafer is mounted on one side of leads of a tape carrier having metal thin film leads formed on an insulating film through bumps. Thereafter, the tape automated bonded semiconductor chip is mounted on the test socket shown in FIG. 2 to connect the other side of the leads with the test terminals to perform burn-in test, and the semiconductor chip is separated to external lead bonding. Implement on MCM.

However, this tap method has no technical problem when applied to a known good die manufacturing process by a general technique, but the manufacturing cost increases due to special tooling, and an additional process required for bump formation is required, and the MCM assembly The disadvantage is that it is only applicable to in-process tap method or flip chip test socket adapters.

3 is a micrograph of a main part of a known good die array using a conventional thin film contact probe method. This method involves the formation of a metal trace on a thin film of imide, followed by a membrane-shaped contact terminal on one side of the metal trace to align with the bonding pad and a membrane to attach to the glass support frame on the other side. The glass support frame is burned in by fanning out to the (membrane) end. This method can test a large-capacity semiconductor chip, but there is a disadvantage in that a membrane and a supporting frame for each device are required and an expensive tooling process is required.

The following method of using a flip chip test socket adapter is disclosed in US Pat. No. 5,006,792. In the case of a bare chip in which solder bumps are formed on each bonding pad of the chip, the test is performed by inserting the same into a dedicated adapter. Conduct. The test socket adapter has a substrate on which cantilever beams are correspondingly connected with the solder bumps of the semiconductor chip to be inserted. Thereafter, the inter-substrate is housed in the case, and the input / output terminals protruding out of the case are inserted onto the burn-in test substrate to perform burn-in test.

The tap method and the method using the test socket adapter can use tap technology that is already popular and have the advantage of enabling testing in a bare chip state before packaging.

However, the process of forming bumps on the bonding pads of a single semiconductor chip requires expensive equipment requiring high precision due to the fine pitch between the bonding pads due to high integration, and chip handling is required because the individual semiconductor chips must be dealt with during the test. Difficult, since a small amount of chips are tested, there is a problem that the unit cost is very high compared to the conventional semiconductor package. In addition, the tape carrier according to the tap method is not reusable after being used once, and the method of using the tester socket adapter has a problem in that the manufacturing of the test socket is complicated and complicated.

In addition, the wafer level test is an ideal method of performing a batch test after connecting the contact terminals to all the chips on the wafer, but it is practically impossible to manufacture the contact terminals corresponding to the bonding pads of all the chips. There is a problem such as noise generation.

In order to solve these problems, a method of manufacturing a good good die provided by a test housing disclosed in US Pat. No. 5,173,451 is as follows.

4 shows a known good die array manufacturing method using a conventional temporary packaging method, in which a is a cross-sectional view of a known good die array provided by a test housing, and b is a micrograph of a bonding pad of a known good die array of FIG.

Referring to FIG. 4A, external contact leads 12 are disposed outside the rectangular ceramic substrate 13 having the die accommodation space 11 formed at the center thereof, and the inside of the die accommodation space 11 is formed. The semiconductor chip 15 is mounted on the adhesive tape 14. Contact pads 18 corresponding to the bonding pads 17 of the semiconductor semiconductor chip 15 are formed at ends of the ceramic substrate 13, and the contact pads 18 are the external contact leads 12. ) And internal wiring (not shown). The bonding pads 17 and the contact pads 18 are connected by wires 19, which perform a soft bond that does not form a wire ball on the contact pads 18 to facilitate removal. do.

Next, a rectangular cover is mounted on the ceramic substrate 13 to close and seal the inside by the elastic rubber member 16, and then insert the external contact leads 12 into a test substrate (not shown). To carry out a burn-in test.

The known good die 10 provided in such a test housing has a single semiconductor chip 15 attached to the die receiving space 11 of the ceramic substrate 13 having external contact leads 12 such as a conventional semiconductor package. 14, the bonding pads 17 of the chip 15 and the contact pads 18 inside the substrate 13 are connected to each other by a wire 19. Then, a plurality of known good dies 10 are mounted on the test substrate to perform a burn-in test at once. Then, the known good die 10 provided in the tested test housing was detached from the test board, the cover was removed, the wire 19 was removed, and the semiconductor chip 15 was removed to test the defect-free, known good defects. You can get a die.

Meanwhile, referring to FIG. 4B, after removing the wire from the bonding pad after the burn-in test as described above, the surface of the bonding pad is closely observed, and the marks remain in the center part.

Therefore, the known good die manufacturing method provided in the test housing has the advantage of improving the yield since a relatively many known good dies can be obtained in a single test process using a conventional wire bonding process. The complexity and limited use of only one type increases the cost of manufacturing a ceramic substrate, and damages the reliability of the semiconductor chip due to damage of the wire-bonded bonding pad.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to mount a plurality of semiconductor chips having a bonding pad with bumps formed on a test socket that is easy to manufacture, and then, by reflow soldering, a PCB substrate. The present invention provides a test socket for attaching bumps to a land pattern of and attaching the bumps onto a burn-in test substrate of a plurality of test sockets.

Another object of the present invention is to provide a test socket that can be obtained inexpensively a large amount of defect known good die after performing a burn-in test.

Still another object of the present invention is to provide a method of manufacturing a known good die, which can easily obtain a large amount of known good die formed with bumps, as well as preventing damage to a semiconductor chip during a burn-in test.

A characteristic of the test socket according to the present invention for achieving the above object is that the external contact terminals are connected to the external burn-in test substrate at one end of the test socket, and a plurality of the external contact terminals at regular intervals. A substrate on which metal wiring is formed and at least one land pattern connected to the external contact terminals by the metal wiring is formed; The burn-in test is performed by having a plurality of semiconductor chips mounted on the land pattern formed at the center of the substrate and having at least one bump formed thereon.

A feature of a known good die manufacturing method using a test socket according to the present invention is a substrate having land patterns formed at regular intervals in a central portion of the substrate and contact terminals formed to be connected to external terminals at one side of the substrate. Mounting semiconductor chips having a plurality of bumps formed thereon; Bonding the bumps of the semiconductor chip to the land patterns of the substrate after the process; A process of performing burn-in test by mounting the substrate on the test substrate after the process; and heating and isolating the semiconductor chips having the bumps formed thereon after the process to isolate the substrate from the burn-in test. It is a point which has a process of conveying to a chip carrier sequentially by a conveying means.

Hereinafter, with reference to the accompanying drawings an embodiment of a test socket and a known good die manufacturing method using the same according to the present invention will be described in detail.

FIG. 5 is an exploded perspective view of a test socket for a known good die array according to the present invention, and FIG. 6 is a cross-sectional view taken along line V-V 'of FIG.

First, referring to FIG. 5, contact readers, for example insertion terminals 22, are formed on one side of a rectangular substrate 21 made of a predetermined material, for example, ceramic or plastic, for connection with the outside. Metal patterns 24 are formed on the substrate 21 at predetermined intervals, and land patterns 23 connecting the insertion terminals 22 and the metal patterns 24 to each other are formed at the center of the substrate 21. Formed.

Next, referring to FIG. 6, the semiconductor chip 25 to be mounted on the land pattern 23 formed at the center of the substrate 22 has a plurality of bump electrodes 26 formed on the bottom thereof. The bump electrodes 26 may be formed by, for example, a bump electrode formation method using a metal mask, or may be formed by dropping solder balls directly onto an electrode pad in a bare chip state. In this case, the land patterns 23 should be formed to correspond to the bump electrodes 26 of the semiconductor chip 25. In addition, as shown in FIG. 5, the land patterns 23 are connected to the external insertion terminals 22 by at least one metal wire 24 formed in the substrate 21. The substrate 22 may protect the semiconductor chips 25 mounted on the upper portion of the substrate 21 by a protective case (not shown) formed by screws (not shown) in the corners and coupled by a coupling means. have. In addition, the case may be selected and used in any group among a metal having low resistance to prevent static electricity, an antistatic plastic, or a plastic coated with an antistatic material.

After the plurality of test sockets 20 are inserted into and installed on a burn-in test substrate (not shown), the burn-in is applied by applying stress to a temperature, voltage, and current higher than the operating conditions of the conventional semiconductor chip 25. Perform the test. After the burn-in test as described above, the semiconductor chip 25 mounted on the land pattern 23 is separated. Therefore, a good hard die is obtained by separating the defective semiconductor chips 25 which have been subjected to the burn-in test. In the test socket 20, a plurality of test chips 20, for example, 8 to 10 semiconductor chips 25 are mounted on the test socket 20, and a plurality of test sockets 20, for example, about 20 tests. Since the socket 20 is mounted, a large number of semiconductor chips 25 can be tested in one burn-in test at a time, about 160 to 200 at a time, so that a large number of known hard dies can be obtained. In addition, the substrate 21 may be used almost semi-permanently as long as no abnormality occurs in the land patterns 23, which are contact pads in which the bump electrodes 26 are repeatedly attached or detached. The substrate 21 may be formed of a plastic PCB. In this case, the manufacturing cost of the substrate 21 is very low.

A method for manufacturing a known good die using the test socket as described above will be described below.

7 shows a cross-sectional view of the furnace hard die manufacturing process according to the present invention. Reference numerals by the same means are used the same as those disclosed in the preceding figures.

Referring to the cross-sectional view of the test socket 20 of FIG. 6 described above, a test socket 20 for manufacturing a known good die may be formed of a rectangular PCB board 21 made of plastic or ceramic material, and the PCB board 21. The land pattern 23 is formed at the center of the upper surface of the c), and is formed at one end of the PCB substrate 21 and has external insertion terminals (not shown) for electrical connection with the outside.

Referring to the manufacturing process of the known good die 30 with reference to the test socket 20 provided as described above, first, an electrical connection between the substrate and each chip bonding pad is performed in the wafer state in which the integrated circuit design is completed through the manufacturing process of the semiconductor device. To facilitate this, solder bumps or gold bumps are formed to align. Such a technique is referred to as a controlled collapsing chip connection technique. Thereafter, the wafer is sawed so as to be separated into individual semiconductor chips, and then the semiconductor chip 25 is mounted and attached to the substrate 21 for electrical connection with the substrate 21. At this time, the solder pattern on the land pattern 23 of the substrate 21 and the bump 26 formed on the chip bonding pad are attached to each other through a reflow soldering process. That is, during the reflow soldering, the semiconductor chip 25 is heated at a specific temperature for 3 to 8 seconds in a surface mounting furnace so that the solder pattern on the land pattern 23 of the substrate 21 is soldered to the bumps 26. ) And complete electrical connection with the external connection terminal 24 at the same time. The bumped semiconductor chip 21 may be mounted on the substrate 21 in the same manner as the flip chip mounting method.

The external insertion terminals of the test socket 20 prepared as described above are mounted on a burn-in test substrate (not shown) to perform burn-in test. Then, after removing the test socket 20 from the burn-in test substrate, heating the substrate 21 under the same temperature condition as in the reflow soldering process described above, the solder pattern on the land pattern 24 is remelted. The upper surface of the semiconductor chip 25 is then sucked with a vacuum pick-up tool 40 to obtain a flawless knocked good die 30 which has been burned in. At this time, the vacuum pick-up tool 40 sucks the known good die 30 and transfers it to the chapter carrier (not shown). The known good dies 30 are left with bumps 26 on the bonding pads, and are directly used as flip chip bumps during the semiconductor chip mounting process of the bumps 26 and directly in the multichip module assembly process. Wire bonding or bump electrodes may be formed again.

Therefore, it is possible to manufacture a large quantity of good good die by compensating or solving the disadvantages caused by the method of using a conventional task socket adapter, a hot chuck probe method, a tap method, and a known good die provided by a test housing. .

As described above, the test socket according to the present invention has external contact terminals connected to an external burn-in test board at one end thereof, and a plurality of metal wires are formed at a predetermined interval from the external contact terminal. And a plurality of semiconductor chips which are mounted on a substrate on which at least one land pattern connected by contact terminals and a metal wiring are formed and a land pattern formed at the center of the substrate, and at least one bump is formed. .

A semiconductor chip having a plurality of bumps formed on a substrate having land patterns formed at a predetermined interval in a central portion of the substrate and contact terminals formed at one side of the substrate so as to be connected to external terminals using the test socket. After mounting the semiconductor chips and bonding the bumps of the semiconductor chip and the land patterns of the substrate, and mounting the substrate on the test substrate for burn-in test, the semiconductor chips having the bumps formed thereon are heated and separated from the substrate. Known good die can be manufactured by sequentially transferring a burnt-tested good-no-good die to a chip carrier by a transfer means.

Therefore, as described above, the substrate for manufacturing the known good die can be used almost semi-permanently because it is made of a plastic material, and using a conventional PCB substrate has an advantage in that the manufacturing cost of the substrate is very low. In addition, a plurality of semiconductor chips having bump electrodes formed on one substrate are mounted, the substrates are mounted on a plurality of burn-in test substrates, burn-in tests are performed, and the semiconductor chips are separated from the substrates. It is possible to supply a plurality of known good dies in which the formed bump electrodes remain inexpensively. In addition, the bump electrode formed on the bonding pad of the semiconductor chip can be used as a bump during the bonding process, thereby satisfying the MCM buyer, and the MCM can be extended to an expensive supercomputer or a personal computer.

As described above, the test socket and the known good die manufacturing method using the same according to the present invention may be manufactured by mounting at least one semiconductor chip having a bump electrode formed on the test socket and performing a burn-in test, thereby manufacturing a large number of known good dies. It is obvious that various modulation changes are possible without being limited to the present embodiment without departing from the spirit of the invention.

Claims (10)

External contact terminals connected to an external burn-in test board are formed at one end of the test socket, and a plurality of metal wires are formed at regular intervals from the external contact terminals, and the external contact terminals are connected by metal wires. A substrate on which at least one land pattern is formed; And a test socket including a plurality of semiconductor chips mounted on an upper portion of the land pattern formed at the center of the substrate and having at least one bump formed therein. The test socket of claim 1 wherein the substrate is made of either plastic or ceramic. The test socket of claim 1, wherein portions of the substrate other than the external contact terminals may be protected by an antistatic protective case. The test socket according to claim 3, wherein the case is selected from any of a group of low resistance metals capable of preventing static electricity, antistatic plastics, or plastics coated with an antistatic material. Mounting semiconductor chips having a plurality of bumps formed on the substrate having land patterns formed at regular intervals in a central portion of the substrate and contact terminals formed on one side of the substrate so as to be connected to external terminals; Bonding the bumps of the semiconductor chip to the land patterns of the substrate after the process; Mounting a substrate on a test substrate after the step and performing burn-in test; After the process, the semiconductor chip having the bumps formed is separated from the substrate by heating to be isolated, and then the burned-down test of the defective good good die is carried out by the transfer means to the chip carrier. Way. The method of claim 5, wherein the semiconductor chips are mounted by reflow soldering on land patterns. The method of claim 6, wherein the reflow soldering is performed by attaching the semiconductor chip by heating to a specific temperature in a surface mount path so that the solder pattern on the land pattern is soldered to the bumps. The method of claim 5, wherein bumps formed on the semiconductor chip remain intact after being separated from the substrate. The method of claim 8, wherein the bumps are used as bump electrodes in a multichip module manufacturing process. The method of claim 5, wherein the transfer means uses a vacuum pickup tool having a suction force.