KR0141453B1 - Manufacturing method of known-good die - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a manufacturing apparatus and a manufacturing method of a known good die capable of mass producing a known good die by collectively AC and burn-in testing a plurality of integrated circuit chips separated from a wafer. Technology to form a bump on the printed circuit board and a tab (TAB) terminal for electrical testing and electrically connecting the bare chip electrode pad, and to provide a pressing means for contacting the bump and the electrode pad. The present invention provides a manufacturing apparatus and a manufacturing method of a known good die which can automatically test a plurality of bare chips before bonding or molding. Therefore, the present invention can mass-produce inexpensive known good dies using an integrated circuit chip, and can be extended to not only a multi-chip module (MCM) currently used in a super computer but also a personal computer.

Description

Manufacturing apparatus and manufacturing method of know good die

1 is a schematic diagram of a test socket for executing a conventional burn-in test,

2 (a) and (b) are cross-sectional views of a test socket adapter used to conduct a burn-in test of a conventional flip chip and flip chip,

3 is a front view of a printed circuit board used in the manufacture of a known good die according to the present invention;

4 is a front view of a matching means used in the manufacture of a known good die according to the present invention,

Figure 5 is a front view of the pressing means used in the manufacture of the furnace good die according to the present invention,

6 is a state diagram of a combination of a printed circuit board, a matching means and a pressing means used in the manufacture of a known good die according to the present invention.

* Explanation of symbols for the main parts of the drawings

30; A printed circuit board 31; Matching means mounting area

32; Bare chip 33; TAB terminal

35; Diepad area 40; Matching means

50, 60; Pressing means 51; Feed Contact

52, 62; Tool assembly 53; Load transfer means

The present invention relates to a manufacturing apparatus and a manufacturing method of a known good die (hereinafter referred to as KGD), and more particularly, to a plurality of integrated circuit chips separated from a wafer using a conventional semiconductor assembly process. The present invention relates to a KGD manufacturing apparatus and a manufacturing method capable of mass-producing KGD by AC and Burn in testing.

KGD technology can be largely divided into production technology and test technology of boards for burn-in and testing. In the manufacture of boards, burn-in and test progress are divided according to chip and wafer level, and wafer-level technology is used to manufacture probing cards, processing thousands of input / output terminals, and burn-in. Since there are problems to be solved, such as the method, attention is being paid to the manufacturing technology of the board for the integrated circuit chip.

In the manufacture of semiconductor devices, integrated circuit chips (hereinafter referred to as IC chips) are generally required to perform AC and burn-in tests. It is to find a defective IC chip in advance. However, since the IC chip is not normally connected to the test pattern generation circuit in the state of the IC chip, the AC chip and the burn-in test are packaged with a molding compound, as shown in FIG. It will be done at.

Referring to FIG. 1, the outer lead 12 connected to the electrode pad protrudes from the sidewall of the package 10. The package 10 from which the outer lead 12 protrudes is mounted to a test socket 15 having a socket hole 14 into which the outer lead 12 can be inserted. The test socket 15 in which the package 10 is mounted is again mounted on a burn-in board, not shown. In this state, AC and burn-in tests are performed. Reference numeral 16 denotes a lead of the test socket 15 that is electrically connected to the external lead 12 of the package 10.

In the AC and burn-in tests, a test signal is input to the IC chip under a high temperature and a high voltage rather than a normal state. Then, it is checked whether or not a defect occurs in the IC chip. For example, in the case of DRAM, a defective memory circuit, a defective memory cell, a defective wiring, and the like are usually checked.

As a result, an IC chip that is likely to cause any disturbance when used in a steady state will necessarily cause such defects (such as breakdown of the insulating film of the gate oxide film) during the burn-in test. Therefore, an IC chip in which a defect is generated during the burn-in test is detected, and this IC chip is treated as defective. In this way, the defective IC chip is removed before shipment to ensure the reliability of the product.

Recently, a multi-chip technology using flip chips, in which a plurality of IC chips are mounted on a ceramic board without using a single chip package, has been developed to achieve high speed, high capacity, small size, and large scale integration. Many integration methods have been proposed. One representative method of these is a multi chip module (hereinafter referred to as MCM).

MCM achieves ultra-high density, in which a large number of IC chips are interconnected on a lower-density wired multilayer ceramic board, and has been successfully applied to supercomputers by IBM, DEC, Hitachi, and others.

However, MCMs are subject to many technical and economic limitations for the following reasons. In other words, MCM in which a large number of IC chips are embedded, compared to the conventional single chip package technology, has a large integrated scale, but the production yield is significantly reduced, resulting in a very high production cost.

In particular, the most difficult problem of MCM is that it is difficult to secure enough KGD, which is directly related to production yield, to which the test is completed and the same degree of reliability as in the conventional package technology is recognized.

This invention relates to sufficient securing of KGD. Hereinafter, the defective IC chip which has completed all the tests is defined as KGD. In addition, an IC chip that is separated from a wafer into a single IC chip and has not been tested without being packaged is called a bare chip. A more detailed overview of KGD is presented in the Potential Project Report 1992 of Microeletronic and Computer Technology Corpration.

Despite the growing awareness of the importance of KGD applied to MCM, there are significant difficulties in mass production of low-cost KGD. That is, a single bare chip separated from the wafer does not have external leads and therefore cannot use test sockets that can be applied to chip testing, so the AC and burn-in before being installed on the printed circuit board (hereinafter referred to as PCB) in the bare chip state. There is a problem that cannot be tested.

As a technique for solving this problem, a hot chuck probe method, a tape automated bonding (TAB) method, a flip chip test socket adapter method, a wafer level burn-in test Various methods have been developed such as a wafer level burn-in test method, a temporary packaging method, and a KGD manufacturing method provided by a test housing.

These methods have their advantages, but they all have their disadvantages in terms of cost savings for mass production of KGD.

These methods are outlined as follows.

First, the hot chuck probe method is a method of performing a test after contacting a hot chuck probe having terminals that can contact the electrode pads of an IC chip in a wafer state with the electrode pad of the IC chip. The condition can be maintained and no additional process is required in the wafer state, so it can be supplied to the consumer in the wafer state, but it takes a lot of time to test, and a separate hot chuck probe must be manufactured according to different IC chips. Therefore, there is a problem that the manufacturing terminal rises.

In the tap method, an IC chip saved in a wafer is mounted on one side of leads of a tape carrier having metal thin leads formed on an insulating film through bumps, and the other side of the leads is connected to test terminals, sockets, and the like. It is possible to use the current package technology as a method of connection and test by using it, but it is required to secure the technology and process for bump shape, it is expensive, and there is limited flexibility in the assembly of MCM, so only the tab or flip tab is used. The disadvantage is that it is applicable and not reusable.

The method of using a flip chip test socket adapter is to perform AC and burn-in tests using a dedicated adapter in a bare chip state in which solder bumps are formed on each electrode pad, and the adapters used in the US Pat. 006, 792. This is shown in FIG.

2A and 2B are cross-sectional views of test socket adapters for performing burn-in tests of conventional flip chip and flip chip.

Referring to FIG. 2A, the solder bumps 24 are formed on the electrode pads of the bare chip 22 because the AC and burn-in tests are not possible by mounting them in the test sockets without wires connected to the electrode pads with wires. The test is then performed by inserting it into a dedicated test socket adapter.

Referring to FIG. 2 (b), the test socket adapter has a substrate 28 having cantilever beams 26 correspondingly connected to the solder bumps 24 of the bare chip 22 to be inserted. The substrate 28 is housed in the case 20. Here, reference numeral 23 denotes a lead connected to the cantilever beam 26, reference numeral 27 denotes a lead protruding out of the case, and reference numeral 25 denotes a guide vigo which stably supports the bare chip 22 when it is inserted. Reference numeral 29 denotes a cover for protecting the bare chip 22.

The test method of the IC chip using the test socket adapter of the configuration as described above enables the test in the bare chip state before packaging. However, this technique requires chip testing and burn-in with a solder bump, which is a metal projection, formed on each electrode pad of the IC chip.

In the process of forming solder bumps on an electrode pad of an IC chip, expensive equipment requiring high precision is required due to fine pitch between electrode pads due to high integration. In addition, since the structure of the test socket is very difficult to manufacture, the chip handling is difficult because the individual IC chip must be handled during the test, and a small amount of the IC chip is tested, so that the unit cost is much higher than that of a conventional semiconductor package.

Wafer-level burn-in test is an ideal method of conducting a batch test after connecting contact terminals to all IC chips on the wafer, but it is impossible to manufacture contact terminals corresponding to electrode pads of all IC chips. There is a problem such as noise generation.

The temporary packaging method is to fix an IC chip with a thermoplastic adhesive in a conventional ceramic package, wire bond, and separate the waa from the electrode pad after the burn-in and testing are completed. While there is no limitation in the test, there is a problem in that productivity is reduced due to the wire removing process and bonding marks remain on the electrode pads.

Problems in the manufacture of KGD according to the prior art can be summarized as follows. ① Since IC chips are impossible to test AC and burn-in, they are produced in small quantities using bumps and dedicated test sockets. (2) Handling at the chip level is very difficult because it must deal with a single IC chip. 3. The cost is considerably more expensive than a packaged IC chip. ④ Difficulties in creating a test zig. ⑤ There is no standardization.

An object of the present invention is to solve the above problems, by applying a physical force on the back of the bare chip to temporarily connect the bump on the printed circuit board and the electrode pad on the bare chip to perform a temporary AC test and burn-in test It is to provide a manufacturing apparatus of KGD that makes it possible.

Another object of the present invention is to provide a method for manufacturing a KGD which can obtain a KGD by collectively performing AC and burn-in tests on one or a plurality of bare chips separated from a wafer by forming bumps on a printed circuit board. To provide.

A feature of the KGD manufacturing apparatus according to the present invention for achieving the above object includes: matching means for preventing the shaking of a plurality of bare chips to be tested;

A signal wiring line formed of at least one or more layers, a die pad region for mounting bare chips, a plurality of bumps arranged for electrical connection with electrode pads of a bare chip in a die pad region, a mounting region in which matching means are mounted, and a bare chip A printed circuit board having a tab (TAB) terminal in which an electrical circuit is implanted so as to conduct electrical burn-in tests at a plurality of times;

And pressing means for pressing the bare chips to a predetermined pressure by fastening the printed circuit board to a side thereof.

It will include.

Here, the pressurizing means includes a feed part contact part which is in contact with the automatic equipment feed part, a tool assembly arranged in line with the upper end of the feed part contact part, and formed at an end of the tool assembly, and a bare chip is formed on the contact part. It may be used to have at least one impact buffer means attached to reduce the load to prevent damage to the bare chip.

An elastic spring may be used as the shock absorbing means. In addition, the pressing means is composed of a tool assembly arranged in a line on the upper end, a load transmission means formed at the end of the tool assembly to transfer a vertical load to the bare chip, and a secondary pad for applying a physical load to the bare chip May be used.

The secondary pad is preferably a heat resistant material that does not undergo thermal deformation so as not to affect the bare chip during the burn-in test. As the heat resistant material, artificial rubber, synthetic rubber, and teflon may be used.

As the matching means, matching holes are arranged as many as the number of bare chips, and an edge portion is formed on the outer side surface of the matching holes.

On the other hand, the KGD manufacturing method according to the present invention comprises the steps of preparing a tool assembly for forming a plurality of bump groups on the surface of the printed circuit board tab tab is formed, and applies a physical force to the printed circuit board and the bare chip;

Fixing a bare chip to a plurality of bumps in a bump group of the printed circuit board and pressing the bare chip and the printed circuit board with a tool assembly;

Inserting a tab terminal formed on one side of the printed circuit board into a test multilayer printed circuit board separately to perform AC and burn-in tests;

Checking for defective chips and chips that are not defective after the steps of performing the AC and burn-in tests are completed;

And selectively removing the tool assembly pressurizing the bare chip for subsequent processing to selectively remove the defective / defective bare chip;

Characterized in that it comprises a.

Hereinafter, with reference to the accompanying drawings, a preferred embodiment of the KGD and its manufacturing method according to the present invention will be described in detail.

3 is a front view of a printed circuit board used in the manufacture of the KGD according to the invention.

Referring to FIG. 3, the printed circuit board 30 has a die pad region 35 for mounting a plurality of bare chips 32 to be tested and having at least one signal wiring line formed thereon, and a bare chip 32. The mating means mounting area 31 for preventing the fluctuation of these parts, and the tab terminal 33 implanted with an electrical circuit so as to perform electrical burn-in test on the individual or multiple bare chips 32.

4 is a front view of the mating means used in the manufacture of the KGD according to the invention.

Referring to FIG. 4, in the matching means 40, after the bare chip 32 is mounted on the die pad region 35 of the printed circuit board 30, the bare chip 32 swings even if any external force is applied. In order to prevent this, the matching holes 41 are formed on the board of the same material as the printed circuit board by the number of bare chips, and the edge portion 42 is provided on the outer side of the matching holes 41.

5 and 6 are front views of the pressing means used in the manufacture of the KGD according to the invention.

Referring to FIG. 5, the pressurizing means 50 includes a feed part contact part 51 engaged with an automatic facility feed part, a body 54 to which a printed circuit board is coupled, a feed part contact part 51 and a body 54. The tool assembly 52 arranged in a row at the upper end of the upper and lower ends of the tool assembly 52 and the end of the tool assembly 52 are distributed evenly to the contact portion of the bare chip, and the bare chip is not damaged by the transmitted load. It has at least one load transfer means 53 having an impact buffer effect.

As this load transmitting means, an elastic spring which is generally used can be used.

Referring to FIG. 6, the pressing means 60 is a tool assembly 62 arranged in a line at an upper end thereof, and a load transmitting means 63 formed at an end of the tool assembly 62 to transmit a vertical load to the bare chip. ) And a secondary pad 64 for applying a physical load to the bare chip.

7 is a state diagram of the combination of a printed circuit board, a matching means and a pressing means used in the manufacture of the KGD according to the present invention.

Referring to FIG. 7, the KGD manufacturing apparatus combines one of the pressing means 50 and 60 of FIG. 5 or 6 with the printed circuit board 30 of FIG. 3, and the matching means 40. The bare chip is configured to combine the printed circuit board 30 with the printed circuit board 30 at a mating position where the electrode pads and the bumps 34 on the printed circuit board 30 are electrically connected.

In FIG. 7, the pressurizing means of FIG. 6 and the matching means of FIG. 4 are used, and are mainly used for test of IC chip burn-in of small size, and only burn-in test of IC chip of large size is performed. Pressing means are used.

The manufacturing method of the KGD having the above configurations will be outlined as follows.

Referring to FIG. 7, first, a plurality of groups of bumps 34 are formed on the surface of the printed circuit board 30 on which the tab terminals 33 are formed, and physical forces are applied to the printed circuit board 30 and the bare chip 32. The tool assembly 62 and the bare chip 32, which apply the pressure, are prepared so that the matching means 40 is not rocked.

Next, the bare chip 32 and the printed circuit board 30 are pressed by the tool assembly 62 while the electrode pads of the bare chip 32 are electrically connected to the bump 34 group on the printed circuit board 30. do. Then, the tab terminal 33 formed on one side of the printed circuit board 30 is inserted into a separate test volume printed circuit board to perform AC and burn-in tests. After the AC and burn-in tests are completed, the defective IC chip and the defective IC chip are checked. The tool assembly pressing the bare chip can be selectively removed for subsequent processing to obtain KGD, which is a bare chip of defect / defective bare chip.

The effects of the KGD manufacturing apparatus and the manufacturing method according to the present invention described above are as follows.

① It is possible to mass-produce defect-free KGD which is usually AC and burn-in test by IC chip. ② It is very easy to handle at the chip level because there is no need to cut the tie or cut the wire. ③ The equipment used for the existing IC chip assembly is used as it is in this invention, so no additional facility is required. ④ It is easy to make a test jig.

⑤ Standardization is possible. ⑥ No thermal or chemical change on bare chip pads. ⑦ The KGD's cost can be lowered dramatically, so the scope of application can be extended to personal computers as well as MCM and ASIC modules currently used in supercomputers.

Claims (9)

Matching means for preventing rocking of the plurality of bare chips to be tested; A signal wiring line formed of at least one or more layers, a die pad region for mounting bare chips, a plurality of bumps arranged in the die pad region for electrical connection with an electrode pad of a bare chip, a mounting region in which the matching means is mounted, and A printed circuit board having a tab terminal implanted with an electrical circuit for conducting electrical burn-in tests of a plurality of bare chips simultaneously; And pressing means detachably fastened to a side of the printed circuit board to press the bare chips at a constant pressure. The apparatus of claim 1, wherein the matching means is provided with matching holes arranged as many as the number of bare chips, and an edge portion is formed at an outer side surface of the matching hole. According to claim 1, wherein the pressing means is a feed part contact portion in contact with the automatic equipment feed portion, the tool assembly formed in line with the upper end of the feed portion contact portion, and the contact portion of the bare chip formed at the end of the tool assembly Apparatus for producing a furnace good die, characterized in that it has at least one load transfer means for transmitting a load to the. The tool assembly of claim 1, wherein the pressing means comprises: a tool assembly arranged in a line at an upper end thereof, a load transmitting means formed at an end of the tool assembly to transfer a vertical load to the bare chip, and two to apply a physical load to the bare chip. A manufacturing apparatus of a known good die, characterized by consisting of a tea pad. 3. The apparatus of claim 2, wherein the matching means is formed of the same material as the printed circuit board. The apparatus of claim 3, wherein the load transfer means is made of an elastic spring. The apparatus for manufacturing a known good die according to claim 4, wherein the secondary pad is made of a heat resistant material. The apparatus of claim 4, wherein the secondary pad is any one of artificial rubber, synthetic rubber, and teflon. Preparing a tool assembly for forming a plurality of bump groups on a surface of a printed circuit board on which tab terminals are formed, and applying physical force to the printed circuit board and the bare chip; Fixing a bare chip to a plurality of bumps in the bump group of the printed circuit board and pressing the bare chip and the printed circuit board with the tool assembly; Inserting a tab terminal formed on one side of the printed circuit board into a separate test printed circuit board to perform AC and burn-in tests; Checking for defective chips and chips without defects after the steps of performing the AC and burn-in tests are completed; And selectively removing the tool assembly pressurizing the bare chip for subsequent processing to selectively remove the defective / defective bare chip.