JP2006005163A - Semiconductor device, and mounting inspecting method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a mounting inspecting method thereof whereby a connective state present between its semiconductor package and its mother board can be inspected more properly than a conventional method. <P>SOLUTION: A semiconductor device 300 comprises a semiconductor package 100 and a mother board 200. The semiconductor package 100 has in its mounting surface 21 adjacently to its solder balls 122 a plurality of dummy terminals 124 which are fused in heating values different from ones of its solder balls 122 and are connected electrically in series with each other. The mother board 200 has on its mounting surface 201 a plurality of dummy pads 203 corresponding to the dummy terminals 124, and has outside its mounting region 204 for the semiconductor package 100 two testing pads 205 which are connected in a conductive way with its two dummy pads 203 corresponding to both ends of the dummy terminals 124 connected in series with each other. By using the semiconductor device 300, a resistance value generated between the testing pads 205 is so measured and is so compared with a predetermined reference value as to inspect the connective state present between the semiconductor package 100 and the mother board 200. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having a semiconductor element mounted thereon and having a connection terminal mounted on a substrate having a pad corresponding to the connection terminal under predetermined reflow conditions, and a mounting inspection method thereof. .

  Conventionally, as disclosed in, for example, Patent Document 1, a semiconductor device in which a semiconductor package is mounted and a semiconductor package having a connection terminal is mounted on a substrate having a pad corresponding to the connection terminal under predetermined reflow conditions. There is known a mounting inspection method for inspecting a connection state between a semiconductor package and a mother board.

  In this mounting inspection method (mounting inspection system), a wiring pattern (pattern wiring) is extended from at least two pads (connection pads) to which connection terminals (solder pads) are connected, and a semiconductor package (electronic component) after mounting. A test pad (test land) is formed at a position on the substrate that is not covered by the substrate. Then, using the wiring pattern of the semiconductor package (internal pattern wiring) and the wiring pattern of the substrate, an electrical path from one test pad to the other testing pad through the wiring pattern of the semiconductor package and the wiring pattern of the substrate Form.

Therefore, after mounting under predetermined reflow conditions, the connection state between the semiconductor package and the substrate can be inspected by inspecting the electrical connection state between the test pads.
Japanese Patent Laid-Open No. 11-87003

  By the way, at the time of mounting, reflow conditions (for example, temperature) vary somewhat. However, in the above configuration, a terminal having the same configuration as the connection terminal that electrically connects the semiconductor package and the substrate is used as a connection terminal that configures an electrical path between the test pads, that is, a test terminal. Therefore, for example, the inspection result may not accurately reflect the connection state between the connection terminal of the semiconductor package and the pad of the substrate due to variations (for example, ball diameter (ie, volume)) of the connection terminal and / or the test terminal.

  In view of the above problems, an object of the present invention is to provide a semiconductor device and a mounting inspection method thereof that can more accurately inspect the connection state between a semiconductor package and a substrate.

  The invention according to any one of claims 1 to 15, which achieves the above object, mounts a semiconductor package having a semiconductor element and a connection terminal on a substrate having a pad corresponding to the connection terminal under predetermined reflow conditions. The present invention relates to a semiconductor device.

  The semiconductor package has a plurality of dummy terminals formed adjacent to the connection terminals on the connection terminal formation surface, and the substrate has a plurality of dummy pads corresponding to the dummy terminals. And a plurality of test pads in a region where the semiconductor package is not mounted, and the dummy terminals are melted with a heat amount different from that of the connection terminals, and / or the dummy pads are melted with a heat amount different from that of the pads. And at least one of the plurality of dummy terminals and between the plurality of dummy pads are electrically connected, and dummy pads corresponding to both ends of the connected dummy terminals or both ends of the connected dummy pads are tested. The pads are electrically connected to each other.

  Thus, according to the present invention, at least one of the dummy terminal and the dummy pad is configured such that the dummy terminal melts with a different amount of heat than the connection terminal, and the dummy pad melts with a different amount of heat than the pad. That is, in a state where there is no variation in reflow conditions (the connection terminal and the pad are ideally connected), the connection state of the dummy terminal and the dummy pad is good, although inferior to the connection state of the connection terminal and the pad, If the reflow conditions vary, the connection state between the dummy terminal and the dummy pad is configured to be defective before the connection state between the connection terminal and the pad. Therefore, according to the configuration of this semiconductor device, since the connection terminal and the dummy terminal and / or the pad and the dummy pad have a difference in advance, the resistance value between the test pads is measured, and a predetermined reference value is obtained. As a result, the connection state between the semiconductor package and the substrate can be inspected more accurately than in the past.

  In addition, since there is a difference between the connection terminal and the dummy terminal and / or the pad and the dummy pad, the number of dummy terminals is larger than when a terminal having the same configuration as the connection terminal is used as a dummy terminal as in the prior art. Can be reduced. Therefore, the inspection time can be shortened. In addition, the wiring length of the wiring pattern that electrically connects the dummy terminals can be shortened. Therefore, the manufacturing cost can be reduced. In addition, since the number of dummy terminals can be reduced, the mounting area of the semiconductor package on the substrate can be reduced.

  Next, a specific example of a configuration in which the dummy terminal melts with a different amount of heat from the connection terminal and / or the dummy pad melts with a different amount of heat than the pad will be described below.

  For example, as described in claim 2, at least one of the dummy terminal and the dummy pad requires a larger amount of heat than the connection terminal to melt the dummy terminal, and a larger amount of heat than the pad to melt the dummy pad. You may comprise as needed.

  In this case, since at least one of the dummy terminal and the dummy pad is harder to melt than the connection terminal and the dummy pad is harder to melt than the pad, the bonding state of the dummy terminal and the dummy pad is the connection terminal. And inferior to the bonding state between the pad and the pad. Therefore, if the bonding state between the dummy terminal and the dummy pad is good, it can be determined that the bonding state between the connection terminal and the pad is also good.

  More specifically, as described in claim 3, at least one of the dummy terminal and the dummy pad is such that the volume of the dummy terminal is larger than the volume of the connection terminal, and the volume of the dummy pad is larger than the volume of the pad. You may comprise so that it may be large. According to a fourth aspect of the present invention, at least one of the dummy terminal and the dummy pad has a melting point of the material constituting the dummy terminal higher than the melting point of the material constituting the connection terminal, and the material constituting the dummy pad. The melting point may be higher than the melting point of the material constituting the pad.

  In addition, as described in claim 5, at least one of the dummy terminal and the dummy pad requires a smaller amount of heat than the connection terminal for melting the dummy terminal, and less than the pad for melting the dummy pad. You may comprise so that it may require.

  In this case, at least one of the dummy terminal and the dummy pad is more easily melted than the connection terminal, and the dummy pad is more easily melted than the pad. It is easy to short-circuit between terminals (between dummy terminals and connection terminals) and / or between adjacent pads (between dummy pads or between dummy pads and pads). Therefore, if the connection state between the dummy terminal and the dummy pad is good (not short-circuited), it can be determined that the connection state between the connection terminal and the pad is also good.

  More specifically, as described in claim 6, at least one of the dummy terminal and the dummy pad is such that the volume of the dummy terminal is smaller than the volume of the connection terminal, and the volume of the dummy pad is larger than the volume of the pad. You may comprise so that it may be small. Further, according to claim 7, at least one of the dummy terminal and the dummy pad has a melting point of the material constituting the dummy terminal lower than the melting point of the material constituting the connection terminal, and the material constituting the dummy pad The melting point of the material may be low so that the material constituting the pad has a low melting point.

  Furthermore, as described in claim 8, at least one of the dummy terminal and the dummy pad, the dummy terminal is melted with a larger amount of heat than the connection terminal is melted, and the connection terminal is melted A second dummy terminal that melts with a smaller amount of heat than the first dummy terminal, and the dummy pad includes a first dummy pad that melts with a larger amount of heat than the pad melts, and a smaller amount of heat than the pad melts. It may be configured to have a second dummy pad that melts in step (b).

  In this case, since the operational effect of the invention of claim 2 and the operational effect of the invention of claim 5 can be realized simultaneously, the connection state of the dummy terminal and the dummy pad is not short-circuited. If the bonding state is good, it can be determined that the connection state between the connection terminal and the pad, that is, the semiconductor package and the substrate is not short-circuited, and the bonding state is also good.

  More specifically, as described in claim 9, at least one of the dummy terminal and the dummy pad is such that the volume of the first dummy terminal is larger than the volume of the connection terminal, and the volume of the second dummy terminal is The volume of the second dummy pad may be smaller than the volume of the connection terminal, the volume of the second dummy pad may be larger than the volume of the pad, and the volume of the second dummy pad may be smaller than the pad. In addition, as described in claim 10, at least one of the dummy terminal and the dummy pad has a melting point of the material constituting the first dummy terminal higher than the melting point of the material constituting the connection terminal, and the second dummy The melting point of the material constituting the terminal is lower than the melting point of the material constituting the connection terminal, the melting point of the material constituting the first dummy pad is higher than the melting point of the material constituting the pad, and the second dummy pad is formed. You may comprise so that melting | fusing point of the material to comprise may have low melting | fusing point of the material which comprises a pad.

  In addition, as described in claim 11, the height from the connection terminal formation surface of the dummy terminal semiconductor package to the terminal vertex is substantially the same as the connection terminal, and from the pad formation surface of the dummy pad substrate to the pad vertex. It is preferable that the height is substantially the same as that of the pad because the influence of the height on the connection state can be excluded during reflow mounting.

  The plurality of dummy terminals may not be adjacent to each other. However, as described in claim 12, it is preferable that the terminals are adjacent to each other and the terminal pitch thereof is substantially the same as that of the connection terminal. In this case, the wiring length of the wiring pattern connecting the dummy terminals and / or the wiring length of the wiring pattern connecting the dummy pads can be shortened. Further, the influence of the terminal pitch on the connection state can be excluded.

  The formation position of the dummy terminal is not particularly limited. However, as described in claim 13, it is formed at the outermost peripheral position of the connection terminal formation region in the semiconductor package, or as formed in four corners of the connection terminal formation region in the semiconductor package. Preferably it is. In these places, connection failure is likely to occur due to a semiconductor package and / or a substrate warp generated during reflow mounting. Therefore, if a dummy terminal (and a dummy pad) is provided at the location, the connection state between the semiconductor package and the substrate can be accurately inspected.

  Further, depending on the arrangement of the connection terminals, there may be a connection terminal non-arrangement region in the central region of the connection terminal formation surface of the semiconductor package. In such a case, if a dummy terminal is formed in the central region, which is a non-arrangement region of the connection terminal, as described in claim 15, a separate space for forming the dummy terminal is not required. The mounting area can be reduced.

  In the semiconductor device according to any one of claims 1 to 15, as described in claim 16, a resistance value between electrically connected test pads is measured, and a predetermined reference value is obtained. By comparing, the connection state between the dummy terminal and the dummy pad can be inspected. Based on the connection state between the dummy terminal and the dummy pad, the connection state between the connection terminal and the pad, that is, the semiconductor package and the substrate can be inspected (determined) more accurately than in the past.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, an example is shown in which the dummy terminals are configured to melt with different amounts of heat with respect to the connection terminals.
(First embodiment)
1A and 1B are diagrams showing a schematic configuration of a semiconductor package portion of the semiconductor device according to the present embodiment, where FIG. 1A is a plan view viewed from the mounting surface side, and FIG. FIG. 2A and 2B are diagrams showing a schematic configuration of the mother board portion of the semiconductor device according to the present embodiment, where FIG. 2A is a plan view viewed from the mounting surface side of the semiconductor package 100, and FIG. It is a schematic sectional drawing in a BB cross section. In FIGS. 1 and 2, for convenience, the semiconductor package and the mother board are shown separately.

  As shown in FIG. 1, a semiconductor package 100 is obtained by mounting a semiconductor chip 110 on a circuit board 120. The semiconductor package 100 in this embodiment is a BGA (Ball Grid Array) type.

  The circuit board 120 is formed, for example, by forming a wiring portion in resin, and has a plurality of solder balls 122 as connection terminals on the back surface (mounting surface 121 with the mother board) of the semiconductor chip 110 mounting surface. Yes. The solder ball 122 is electrically connected to the semiconductor chip 110 by a wiring portion (not shown) formed on the circuit board 120, and the solder ball 122 is melted at the time of reflow and joined to the pad on the mother board. The semiconductor package 100 (semiconductor chip 110) and the mother board are electrically connected.

  In the present embodiment, the solder balls 122 are not formed in the central region of the mounting surface 121 (the region surrounded by the alternate long and short dash line in FIG. 1A), and are arranged in a grid pattern surrounding the non-formed region 123. Has been. The ball diameter and terminal pitch of the solder balls 122 are not particularly limited. For example, the solder balls 122 are formed with a ball diameter of 0.5 mm and a terminal pitch of 1 mm.

  In addition, the circuit board 120 has a ball-like dummy terminal 124 that melts in a heat amount different from that of the solder ball 122 in the non-formation region 123 described above. A plurality of dummy terminals 124 are formed adjacent to the solder balls 122.

  In this embodiment, the dummy terminal 124 has two first dummy terminals 124 a having a ball diameter (volume) larger than the solder ball 122 (for example, 0.7 mm) and a ball diameter (volume) larger than the solder ball 122. The small (for example, 0.3 mm) second dummy terminal 124b is composed of two, a total of four. The first dummy terminal 124a and the second dummy terminal 124b are both formed using the same material as the solder ball 122, and the terminal pitch and the height from the mounting surface 121 to the terminal apex are determined by the solder ball. It is set to be substantially the same as 122. At that time, the height is a predetermined height between an electrode (not shown) formed on the mounting surface 121 of the circuit board 120, the solder ball 122 formed on the electrode, and the dummy terminal 124. It is adjusted by providing a conductive base (not shown) having

  Further, the dummy terminals 124a and 124b are not electrically connected to the semiconductor chip 110, and each dummy terminal 124a and 124b is formed by a wiring pattern 125 formed on the semiconductor package 100 (the circuit board 120 or the circuit board 120 and the semiconductor chip 110). Are electrically connected. In the present embodiment, the dummy terminals 124a and 124b are electrically connected by the wiring pattern 125 (broken line in FIG. 1A) formed on the circuit board 120.

  Next, as shown in FIG. 2, the mother board 200 is formed by, for example, forming a wiring portion on resin, and is formed on the mounting surface 201 of the semiconductor package 100 so as to correspond to the solder balls 122 of the semiconductor package 100. And a plurality of dummy pads 203 formed corresponding to the dummy terminals 124 of the semiconductor package 100. The mother board 200 corresponds to the board shown in the claims.

  In addition to the pad 202 and the dummy pad 203, an area (non-mounting area) outside the mounting area 204 (area surrounded by a two-dot chain line in FIG. 2A) where the semiconductor package 100 is mounted at the time of mounting. In addition, two test pads 205 are provided. The test pad 205 includes a dummy pad 203 corresponding to each of the dummy terminals 24 at the both ends (one each of 124a and 124b in this embodiment) among the plurality of electrically connected dummy terminals 24, and wiring. The patterns 206 (broken lines in FIG. 2A) are electrically connected to each other. In the present embodiment, the dummy pad 203 is formed in a central region 207 surrounded by the pad 202 (region surrounded by an alternate long and short dash line in FIG. 2A). Therefore, the wiring pattern 206 is formed in the resin constituting the mother board 200 as shown in FIG. 2B, and the test pad 206 and the dummy pad 203 are connected via the via hole 208 filled with the interlayer connection material. And are electrically connected.

  In the present embodiment, the shape, volume, height, and constituent material of each pad 202, 203, 204 are the same. However, each may have a different configuration.

  Then, the semiconductor package 100 is positioned and mounted on the mother board 200, and in this positioning state, a mounting process is performed under predetermined reflow conditions (the solder balls 122 are ideally melted and connected to the pads 202). The ball 122 is melted and joined to the pad 202. As a result, as shown in FIG. 3, a semiconductor device 300 in which the semiconductor package 100 is mounted on the mother board 200 is formed. FIG. 3 is a cross-sectional view showing a schematic configuration of the semiconductor device 300 and corresponds to FIG.

  Here, if there is no variation in the above-described reflow conditions, the solder ball 122 is ideally melted and forms a good connection state with the pad 202. However, since the reflow conditions vary somewhat, the amount of heat received by the solder balls 122 (and the dummy terminals 124) also varies. That is, since the solder ball 122 may not be able to form a good connection state with the pad 202, it is necessary to inspect the connection state between the semiconductor package 100 and the mother board 200.

  On the other hand, as described above, the semiconductor device 300 according to the present embodiment is a dummy that is adjacent to the mounting surface 121 of the semiconductor package 100 and adjacent to the solder ball 122 and has a connection state worse than that of the solder ball 122 when the heat quantity is the same. A terminal 124 is provided. The dummy terminals 124 are electrically connected by the wiring pattern 125. Further, the mounting surface 201 of the mother board 200 has pads 202 formed corresponding to the solder balls 122 and dummy pads 203 formed corresponding to the dummy terminals 124. Further, the test pads 205 are electrically connected to the dummy pads 203 corresponding to both ends of the electrically connected dummy terminals 124 through the wiring patterns 206. Accordingly, the connection state between the dummy terminal 124 and the dummy pad 203 can be inspected by measuring the resistance value between the two test pads 205.

  Here, a mounting inspection method in the semiconductor device 300 will be described.

  First, for example, a tester is brought into contact with the two test pads 205 to measure the resistance value of the semiconductor device 300. Then, the measured value is compared with a predetermined reference value. The reference value is a resistance value (including tolerance) when the connection state between the dummy terminal 124 and the dummy pad 203 is good.

  When the resistance value between the test pads 205 is higher than the reference value, it indicates that the bonding state between the first dummy terminal 124 a having a ball diameter larger than at least the solder ball 122 and the corresponding dummy pad 203 is poor. Yes. That is, it is shown that the amount of heat sufficient to completely melt the first dummy terminal 124a was not given by reflow. In this case, the solder balls 122 may not be melted due to variations in reflow conditions.

  Further, when the resistance value between the test pads 205 is lower than the reference value, the connection state between the second dummy terminal 124b having a ball diameter smaller than that of the solder ball 122 and the corresponding dummy pad 203 is poor. Show. That is, the second dummy terminal 124b is excessively melted, and a bridge is formed (short-circuited) between the second dummy terminal 124b and the adjacent terminal (dummy terminal 124 or solder ball 122). In this case, the solder balls 122 may be excessively melted due to variations in reflow conditions.

  That is, as a result of measuring the resistance between the test pads 205, only when the measured value is within a reference value having a predetermined width, the solder ball 122 does not short-circuit between the adjacent solder balls 122 and It can be determined that a good bonding state is formed therebetween, that is, a good connection state.

  As described above, according to the semiconductor device 300 and the mounting inspection method thereof according to the present embodiment, the solder ball 122 is secured to the pad 202 without being short-circuited between the adjacent solder balls 122. It is possible to accurately check whether or not

  Moreover, in this embodiment, since it can test | inspect with simple apparatuses, such as a tester, manufacturing cost can be reduced compared with the case where it test | inspects using expensive apparatuses, such as an X-ray transmissive apparatus. .

  In this embodiment, the solder ball 122 is not disposed in the central region (non-mounting region 123) of the mounting surface 121, and the dummy terminal 124 is formed in the non-mounting region 123. As described above, since the dummy terminal 124 is formed in the empty area where the solder ball 122 is not formed, a space for forming the dummy terminal 124 is not required, and the mounting area of the semiconductor package 100 on the mother board 200 is reduced. Can do.

  Further, in the present embodiment, an example in which the height of the dummy terminal 124 from the mounting surface 121 to the terminal vertex is set to be substantially the same as that of the solder ball 122 is shown. Such a configuration is preferable because the influence of the height on the connection state can be excluded and only variations in reflow conditions can be considered. However, the heights may be different as long as the dummy terminals 124 and the solder balls 122 can be connected to the corresponding pads 202 and 203 in a state where there is no variation in the reflow conditions.

  In the present embodiment, an example in which a plurality of dummy terminals 124 are formed so as to be adjacent to each other and have a terminal pitch substantially the same as that of the solder balls 122 is shown. With this configuration, the wiring length of the wiring pattern 125 that electrically connects the dummy terminals 124 can be shortened. Further, the influence of the terminal pitch on the connection state can be excluded. However, the plurality of dummy terminals 124 may be formed so as not to be adjacent to each other.

  Further, in the present embodiment, the example in which the dummy terminal 124 includes the two first dummy terminals 124a and the two second dummy terminals 124b is shown. However, the number is not limited to this example. At least one piece may be formed.

  The ball diameter (volume) of the dummy terminal 124 is not limited to the above example. Any ball diameter may be used as long as the dummy terminal 124 is melted and a good connection state with the dummy pad 203 can be formed in a state where there is no variation in reflow conditions.

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIG. 4A and 4B are diagrams showing a schematic configuration of the semiconductor package 100 portion of the semiconductor device 300 according to the present embodiment. FIG. 4A is a plan view viewed from the mounting surface side, and FIG. It is sectional drawing in a C cross section.

  Since the semiconductor device 300 and its mounting inspection method in the second embodiment are often in common with those in the first embodiment, the detailed description of the common parts will be omitted below, and different parts will be mainly described. .

  The second embodiment is different from the first embodiment in that the dummy terminals 124 are formed using a material that melts with a different amount of heat from the solder balls 122.

  As shown in FIG. 4, in this embodiment, the dummy terminals 124 formed on the mounting surface 121 of the semiconductor package 100 have a ball diameter (volume), a terminal pitch, and a mounting surface 121 that are substantially the same as the solder balls 122. It has a height to the top of the terminal. A plurality of dummy terminals 124 are formed and arranged adjacent to each other.

  However, the dummy terminal 124 is formed using a material that melts with a different amount of heat from the solder ball 122. Specifically, two first dummy terminals 124 c formed using a material having a melting point higher than that of the solder ball 122 and a second dummy formed using a material having a melting point lower than that of the solder ball 122. The terminal 124d is composed of a total of four terminals.

  Accordingly, when the resistance value between the test pads 205 is measured and the measurement result is higher than the reference value, the first dummy terminal 124c made of a material having a melting point higher than that of the solder ball 122 and the dummy pad corresponding thereto. It shows that the bonding state with 203 is bad. That is, it is indicated that the amount of heat sufficient to completely melt the first dummy terminal 124c was not given by reflow. In this case, the solder balls 122 may not be melted due to variations in reflow conditions.

  Further, when the resistance value between the test pads 205 is measured and the measurement result is lower than the reference value, at least the second dummy terminal 124d made of a material having a melting point lower than that of the solder ball 122 and the corresponding dummy pad. This indicates that the connection state with the terminal 203 is poor. That is, the second dummy terminal 124d is excessively melted, and a bridge is formed (short-circuited) between the second dummy terminal 124d and the adjacent terminal (dummy terminal 124 or solder ball 122). In this case, the solder balls 122 may be excessively melted due to variations in reflow conditions.

  That is, as a result of measuring the resistance between the test pads 205, only when the measured value is within a reference value having a predetermined width, the solder ball 122 does not short-circuit between the adjacent solder balls 122 and It can be determined that a good bonding state is formed between them.

  As described above, even in the configuration of the semiconductor device 300 and the mounting inspection method shown in the present embodiment, the solder ball 122 is not short-circuited between the adjacent solder balls 122 and is in a good bonding state with the pad 202. It is possible to accurately inspect whether or not

  The ball diameter (volume) of the dummy terminal 124 is not limited to the above example. For example, by changing the ball diameter with respect to the solder ball 122, the superiority difference (safety factor) for determining the connection state between the solder ball 122 and the pad 202 can be adjusted more finely.

(Third embodiment)
Next, a third embodiment of the present invention will be described with reference to FIG. 5A and 5B are diagrams for explaining the semiconductor device 300 according to the present embodiment, in which FIG. 5A is a plan view seen from the mounting surface side of the semiconductor package 100, and FIG. FIG. 5A and 5B, the semiconductor package 100 and the mother board 200 are illustrated separately for convenience.

  Since the semiconductor device 300 and its mounting inspection method according to the third embodiment are in common with those according to the first embodiment, the detailed description of the common parts will be omitted below, and different parts will be mainly described. .

  The third embodiment is different from the first embodiment in that a dummy terminal 124 is formed at the outermost peripheral position of the solder ball 122 formation region in the semiconductor package 100.

  Here, the circuit board 120 and / or the mother board 200 constituting the semiconductor package 100 warp due to heat or the like during reflow. This warpage is greater on the side surface side of the board (board edge side), and poor connection between the solder ball 122 and the pad 202 tends to occur at that location.

  Therefore, in the present embodiment, as shown in FIG. 5A, dummy terminals 124 are formed at the outermost peripheral position of the solder ball 122 formation region on the mounting surface 121 of the semiconductor package 100 where connection failure is likely to occur. Yes. The dummy pad 203 is also formed at the outermost peripheral position of the pad 202 corresponding to the dummy terminal 124 as shown in FIG.

  Therefore, if the semiconductor device 300 having the dummy terminals 124 shown in the present embodiment is configured and the mounting inspection is performed, the connection state between the solder ball 122 and the pad 202 can be more accurately inspected.

  In the present embodiment, as an example, the dummy terminal 124 includes two first dummy terminals 124 a having a ball diameter (volume) larger than that of the solder ball 122 and the solder ball, as in the first embodiment. It is composed of two second dummy terminals 124 b having a ball diameter (volume) smaller than 122. In addition, the first dummy terminal 124 a and the second dummy terminal 124 b are formed using the same material as the solder ball 122, and the terminal pitch and the height from the mounting surface 121 to the terminal vertex are substantially the same as the solder ball 122. Is set.

  However, the configuration of the dummy terminal 124 is not limited to the above example. A configuration may be adopted in which a plurality of dummy terminals 124 that melt with a heat quantity different from that of the solder balls 122 are formed at the outermost peripheral position of the formation region of the solder balls 122 in which poor connection is likely to occur. Therefore, it is good also as a structure similar to 2nd Embodiment.

  In this embodiment, the dummy pad 203 is formed at the outermost peripheral position of the pad 202 corresponding to the dummy terminal 124. Therefore, since the solder balls 122 do not exist in the outer peripheral direction, the wiring pattern 206 is formed on the mounting surface 201 as shown in FIG. In this case, the via hole 208 can be eliminated. However, as in the first embodiment, the wiring pattern 206 may be formed in the mother board 200.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described with reference to FIG. 6A and 6B are diagrams for explaining the semiconductor device 300 according to this embodiment. FIG. 6A is a plan view seen from the mounting surface side of the semiconductor package 100, and FIG. 6B is a view seen from the mounting surface side of the mother board 200. FIG. In FIGS. 6A and 6B, the semiconductor package 100 and the mother board 200 are illustrated separately for convenience.

  Since the semiconductor device 300 and its mounting inspection method in the fourth embodiment are often in common with those in the first embodiment, the detailed description of the common parts will be omitted below, and the different parts will be described mainly. .

  The fourth embodiment is different from the first embodiment in that dummy terminals 124 are formed at the four corners of the solder ball 122 formation region.

  As shown in the third embodiment, the circuit board 120 and / or the mother board 200 constituting the semiconductor package 100 warp due to heat or the like during reflow. This warpage is greater on the side surface side of the board (board edge side), and poor connection between the solder ball 122 and the pad 202 tends to occur at that location.

  Therefore, in the present embodiment, as shown in FIG. 6A, dummy terminals 124 are formed at the four corners of the solder ball 122 formation region on the mounting surface 121 of the semiconductor package 100 where connection failure is likely to occur. As shown in FIG. 6B, dummy pads 203 are also formed at the four corners of the pad 202 formation region corresponding to the dummy terminals 124.

  Therefore, if the semiconductor device 300 having the dummy terminals 124 shown in the present embodiment is configured and the mounting inspection is performed, the connection state between the solder ball 122 and the pad 202 can be more accurately inspected.

  In this embodiment, a plurality of dummy terminals 124 electrically connected by the wiring pattern 125 are formed at each corner, and a test pad 205 is formed in each of the dummy terminals 124. Therefore, the wiring length of the wiring pattern 125 can be shortened. Further, it is possible to easily identify at which part of the four corners the connection failure has occurred.

  In this embodiment as well, as an example, the dummy terminal 124 includes two first dummy terminals 124 a having a ball diameter (volume) larger than that of the solder ball 122 and the solder ball, as in the first embodiment. It is composed of two second dummy terminals 124 b having a ball diameter (volume) smaller than 122. In addition, the first dummy terminal 124 a and the second dummy terminal 124 b are formed using the same material as the solder ball 122, and the terminal pitch and the height from the mounting surface 121 to the terminal vertex are substantially the same as the solder ball 122. Is set.

  However, the configuration of the dummy terminal 124 is not limited to the above example. A configuration may be adopted in which a plurality of dummy terminals 124 that melt with a heat quantity different from that of the solder balls 122 are formed at the four corners of the solder ball 122 formation region in which poor connection is likely to occur. At this time, a plurality of dummy terminals 124 formed at the four corners may be connected by the wiring pattern 125 and the resistance value may be measured by the test pad 205.

  The dummy pads 203 are formed at the four corners of the pad 202 formation region corresponding to the dummy terminals 124. Therefore, since the solder ball 122 does not exist in the outer peripheral direction, the wiring pattern 206 is formed on the mounting surface 201 as shown in FIG. In this case, the via hole 208 can be eliminated. However, like the first embodiment, the wiring pattern 206 may be formed in the mother board 200.

  Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and can be implemented with various modifications.

  In this embodiment, the dummy terminal 124 is melted with a larger amount of heat than the solder ball 122 is melted, and the second dummy terminal is melted with a smaller amount of heat than the solder ball 122 is melted. The example comprised by 124b was shown. However, the dummy terminal 124 may be configured by either the first dummy terminal 124a or the second dummy terminal 124b.

  Further, in the present embodiment, an example in which the dummy terminal 124 is configured to melt with a heat amount different from that of the solder ball 122 is shown. However, in the semiconductor device 300, at least one of the dummy terminal 124 and the dummy pad 203 is melted with a heat amount different from that of the solder ball 122, and the dummy pad 203 is melted with a heat amount different from that of the pad 202. It only has to be configured. Therefore, the dummy pad 203 may be configured to melt with a different amount of heat from the pad 202, the dummy terminal 124 may be melted with a different amount of heat from the solder ball 122, and the dummy pad 203 may be configured to be different from the pad 202. It may be configured to melt with different amounts of heat.

  When the dummy pad 203 is configured to melt with a different amount of heat from the pad 202, the dummy pad 203 may be configured to require a larger amount of heat than the pad 202 melts. It may be configured to require a smaller amount of heat than the pad 202 melts. Alternatively, the first dummy pad that requires a larger amount of heat than the pad 202 melts and the second dummy pad that requires a smaller amount of heat than the pad 202 melts may be used. For example, the relationship between the dummy terminal 124 and the solder ball 122 shown in the first to fourth embodiments can be replaced with a dummy pad 203 and a pad 202.

  In the present embodiment, an example in which the plurality of dummy terminals 124 are electrically connected by the wiring pattern 125 is shown. However, at least one of the plurality of dummy terminals 124 and the plurality of dummy pads 203 is electrically connected, and the dummy pads 203 corresponding to both ends of the connected dummy terminals 124 or both ends of the connected dummy pads 203 The test pad 205 may be electrically connected. Therefore, the plurality of dummy terminals 124 may not be electrically connected by the wiring pattern 125, and the plurality of dummy pads 203 may be electrically connected. Further, together with the plurality of dummy terminals 124, the plurality of dummy pads 203 corresponding to the dummy terminals 124 may be electrically connected.

It is a figure which shows schematic structure of a semiconductor package among the semiconductor devices in 1st Embodiment, (a) is the top view seen from the mounting surface side, (b) is sectional drawing in the AA cross section of (a). It is. It is a figure which shows the structure of a mother board among semiconductor devices, (a) is the top view seen from the mounting surface side of a semiconductor package, (b) is a schematic sectional drawing in the BB cross section of (a). It is sectional drawing which shows schematic structure of a semiconductor device. It is a figure which shows schematic structure of a semiconductor package among the semiconductor devices in 2nd Embodiment, (a) is the top view seen from the mounting surface side, (b) is sectional drawing in the AA cross section of (a). It is. 4A and 4B are views for explaining a configuration of a semiconductor device according to a third embodiment, where FIG. 5A is a plan view of the semiconductor package viewed from the mounting surface side, and FIG. 5B is a plan view of the mother substrate viewed from the mounting surface side. It is. It is a figure for demonstrating the structure of the semiconductor device in 4th Embodiment, (a) is the top view which looked at the semiconductor package from the mounting surface side, (b) is the top view which looked at the motherboard from the mounting surface side It is.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Semiconductor package 121 ... Mounting surface 122 ... Solder ball (connection terminal)
124 ... dummy terminals 124a, 124c ... first dummy terminals 124b, 124d ... second dummy terminals 125 ... wiring pattern 200 ... mother board 201 ... mounting surface 202 ... Pad 203 ... Dummy pad 205 ... Test pad 206 ... Wiring pattern 300 ... Semiconductor device

Claims (16)

In a semiconductor device in which a semiconductor element is mounted and a semiconductor package having a connection terminal is mounted on a substrate having a pad corresponding to the connection terminal under predetermined reflow conditions.
The semiconductor package has a plurality of dummy terminals formed adjacent to the connection terminals on the connection terminal formation surface,
The substrate has a plurality of dummy pads corresponding to the dummy terminals, and a plurality of test pads in a region where the semiconductor package is not mounted,
The dummy terminal is configured to melt with a heat amount different from that of the connection terminal, and / or the dummy pad is configured to melt with a heat amount different from that of the pad,
At least one of the plurality of dummy terminals and between the plurality of dummy pads are electrically connected, and the dummy pads corresponding to both ends of the connected dummy terminals or both ends of the connected dummy pads, The semiconductor device is electrically connected to the test pads. When the dummy terminal is configured to melt with a different amount of heat than the connection terminal, the melting of the dummy terminal requires a larger amount of heat than the connection terminal,
2. The method according to claim 1, wherein when the dummy pad is configured to melt with a different amount of heat than the pad, the dummy pad requires a larger amount of heat than the pad to melt. Semiconductor device. When the melting of the dummy terminal requires a larger amount of heat than the connection terminal, the volume of the dummy terminal is larger than the volume of the connection terminal,
3. The semiconductor device according to claim 2, wherein when the dummy pad requires a larger amount of heat than the pad to melt, the volume of the dummy pad is larger than the volume of the pad. When the melting of the dummy terminal requires a larger amount of heat than the connection terminal, the melting point of the material constituting the dummy terminal is higher than the melting point of the material constituting the connection terminal,
The melting point of the material constituting the dummy pad is higher than the melting point of the material constituting the pad when the dummy pad requires a larger amount of heat than the pad. The semiconductor device according to claim 3. When the dummy terminal is configured to melt with a different amount of heat than the connection terminal, the melting of the dummy terminal requires a smaller amount of heat than the connection terminal,
2. The method according to claim 1, wherein when the dummy pad is configured to melt with a different amount of heat than the pad, melting of the dummy pad requires a smaller amount of heat than the pad. Semiconductor device. When the melting of the dummy terminal requires a smaller amount of heat than the connection terminal, the volume of the dummy terminal is smaller than the volume of the connection terminal,
6. The semiconductor device according to claim 5, wherein when the dummy pad requires a smaller amount of heat than the pad, the volume of the dummy pad is smaller than the volume of the pad. When the melting of the dummy terminal requires a smaller amount of heat than the connection terminal, the melting point of the material constituting the dummy terminal is lower than the melting point of the material constituting the connection terminal,
The melting point of the material constituting the dummy pad is lower than the melting point of the material constituting the pad when melting of the dummy pad requires a smaller amount of heat than the pad. The semiconductor device according to claim 6. When the dummy terminal is configured to melt with a different amount of heat than the connection terminal, the dummy terminal includes a first dummy terminal that requires a larger amount of heat than the connection terminal melts, and the connection terminal. Having a second dummy terminal that requires a smaller amount of heat than is melted,
When the dummy pad is configured to melt with a different amount of heat from the pad, the dummy pad includes a first dummy pad that requires a larger amount of heat than the pad melts, and the pad The semiconductor device according to claim 1, further comprising: a second dummy pad that requires a smaller amount of heat than that of melting. When the dummy terminal is configured to melt with a different amount of heat than the connection terminal, the volume of the first dummy terminal is larger than the volume of the connection terminal, and the volume of the second dummy terminal is the connection Smaller than the volume of the terminal,
When the dummy pad is configured to melt with a heat quantity different from that of the pad, the volume of the first dummy pad is larger than the volume of the pad, and the volume of the second dummy pad is The semiconductor device according to claim 8, wherein the semiconductor device is smaller than a volume of the pad. When the dummy terminal is configured to melt with a different amount of heat from the connection terminal, the melting point of the material forming the first dummy terminal is higher than the melting point of the material forming the connection terminal, and the second The melting point of the material constituting the dummy terminal is lower than the melting point of the material constituting the connection terminal,
When the dummy pad is configured to melt with a heat quantity different from that of the pad, the melting point of the material forming the first dummy pad is higher than the melting point of the material forming the pad, and the second 10. The semiconductor device according to claim 8, wherein a melting point of a material constituting the dummy pad is lower than a melting point of the material constituting the pad. 11. The dummy terminal has substantially the same height as the connection terminal from the connection terminal forming surface of the semiconductor package to the terminal vertex,
11. The semiconductor device according to claim 1, wherein the dummy pad has substantially the same height from the pad forming surface of the substrate to the pad apex as the pad.   The semiconductor device according to claim 1, wherein the plurality of dummy terminals are formed adjacent to each other and have a terminal pitch substantially the same as that of the connection terminals.   The semiconductor device according to claim 1, wherein the dummy terminal is formed at an outermost peripheral position of a connection terminal formation region in the semiconductor package.   The semiconductor device according to claim 1, wherein the dummy terminals are formed at four corners of a connection terminal formation region in the semiconductor package.   The semiconductor device according to claim 1, wherein the dummy terminal is formed in a central region on a connection terminal formation surface of the semiconductor package, and is surrounded by the connection terminal. . A mounting inspection method for inspecting a connection state between the semiconductor package and the substrate in the semiconductor device according to claim 1,
A semiconductor device mounting inspection method, comprising: measuring a resistance value between the electrically connected test pads and comparing the resistance value with a predetermined reference value.

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