JP2001217390A - High integrated circuit chip having element to be evaluated, and method of inspecting the element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high integrated circuit chip having an element to be evaluated which can secure an empty space on a chip relatively easily without causing a drop of its integration density, and also to provide a method of inspecting the element. SOLUTION: In the high integrated circuit chip which can test electrical characteristics of an element to be evaluated formed on the chip via a probe electrode pad contacted by an inspecting probe, the elements to be evaluated with respect to electronic function elements provided on the chip are collectively provided in an empty area around an internal cell region, electrode pads for a probe common thereto are provided, and gaps for securing routes necessary for connection wiring with the electrode pads are provided to the empty area.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a highly integrated circuit chip having a structure capable of testing the electrical characteristics of a device to be evaluated formed on a chip through a probe electrode pad contacted by a test probe, and a high integrated circuit chip having the same. The present invention relates to a device to be evaluated inspection method.

[0002]

2. Description of the Related Art In a highly integrated circuit chip, it is necessary to inspect and evaluate the characteristics of various electronic functional elements (for example, electron emission elements, circuit resistance elements, MOS transistors, etc.) formed on the chip. It is important for understanding the circuit characteristics. Therefore, conventionally, in the early stage of the design of a highly integrated circuit, in order to evaluate the characteristics of each electronic functional element, when the electronic functional element is configured on a substrate, an element to be evaluated for inspection (so-called, , Check element)
Corresponding to this, a test probe is brought into contact with a required probe electrode pad formed on the chip to test and evaluate the device to be evaluated.

However, usually, the number of elements to be evaluated does not drop to ten on one chip, and therefore the number of elements to be evaluated corresponding to the number and the probe electrode prepared for each element to be evaluated. Since the arrangement of the pads occupies a considerable area, there is a fear that the integration density of the chip is reduced with respect to essential functions. In particular, since the size of the probe electrode pad is usually designed to be 100 μm square due to the restriction due to the size of the inspection probe, the area occupied by the chip on the chip becomes considerably large.

Therefore, as described in, for example, Japanese Patent Publication No. 1-53513, elements to be evaluated are collectively provided in an empty area on a chip, and a probe electrode shared by each element to be evaluated. A pad is provided, and the electrode pad and each device to be evaluated are connected in advance by a common connection wiring or are set in a connectable state, and a FIB (Focused Ion Beam) is provided.
), It is proposed that when an object to be tested is specified (any device to be evaluated is selected), unnecessary connection wiring portions are cut or required connection wiring portions are connected. I have. And, in this way, by reducing the occupied area by sharing the probe electrode pad,
It is possible to avoid that the degree of chip concentration is reduced.

[0005]

However, the problem here is that the provision of common connection wiring in advance requires a considerable occupied space, and that the selected device to be evaluated and the probe are required. There is considerable variation in the wiring resistance between the wiring electrode and the electrode pad, which affects the evaluation at the time of inspection.

The present invention has been made based on the above circumstances, and a first object of the present invention is to avoid a space occupied by providing a common wiring and to connect wiring only to a selected device under evaluation. By providing, the occupied space occupied by the device to be evaluated and the corresponding common probe electrode pad can be reduced, and the empty area on the chip can be relatively easily secured without lowering the integration degree. Another object of the present invention is to provide a highly integrated circuit chip having a device to be evaluated and a method for inspecting the device to be evaluated.

A second object of the present invention is to provide a connection wiring to a common probe electrode pad for each device to be evaluated formed on a chip, and to select a device to be evaluated selected at the time of inspection. By disconnecting the connection wiring between the electrode pad and another device to be evaluated, the connection wiring between each device to be evaluated and the electrode pad can be prepared in advance with a wiring resistance that does not affect the evaluation at the time of inspection. It is another object of the present invention to provide a highly integrated circuit chip having a device to be evaluated and a method for testing the device to be evaluated.

[0008]

In order to achieve the first object, according to the present invention, the electric potential of an element to be evaluated formed on a chip is set via a probe electrode pad with which a test probe contacts. In a high-integrated circuit chip with a configuration capable of testing dynamic characteristics, devices to be evaluated for electronic functional devices formed on the chip are collectively configured in an empty region around the internal cell region, and shared therewith. The present invention is characterized in that a probe electrode pad to be provided is provided, and a gap for securing a route necessary for connection wiring with the electrode pad is provided in the empty area for the element to be evaluated.

Further, according to the present invention, there is provided a method for testing a device to be evaluated in a highly integrated circuit chip having a device to be evaluated on the chip via a probe electrode pad with which a test probe contacts. In advance, in a vacant area around the internal cell area, elements to be evaluated for electronic functional elements formed on the chip are collectively configured, and a probe electrode pad shared therewith is provided. At the same time, for the device to be evaluated, a gap for securing a route necessary for the connection wiring with the electrode pad is provided in the empty region, and when the device to be tested is selected, the energy is In order to connect the element to be evaluated to the electrode pad by using a beam, the connection wiring is formed, and then a test for evaluation is performed.

Further, in order to achieve the second object,
According to the present invention, a highly integrated circuit chip having a configuration capable of testing the electrical characteristics of a device to be evaluated formed on a chip through a probe electrode pad contacted by a test probe,
In an empty area around the internal cell area, elements to be evaluated for the electronic functional elements formed on the chip are collectively configured, and a probe electrode pad shared therewith is provided. A connection wiring with the electrode pad is formed in the empty area for each element.

Further, according to the present invention, in a method for testing a device to be evaluated in a highly integrated circuit chip in which a device to be evaluated is formed on a chip via a probe electrode pad with which a test probe contacts, In advance, in a vacant area around the internal cell area, elements to be evaluated for electronic functional elements formed on the chip are collectively configured, and a probe electrode pad shared therewith is provided. At the same time, the connection wiring with the electrode pad is formed in the empty area for each device under evaluation, and at the stage when the device under test to be tested is selected, the selected device under evaluation and the electrode A connection wiring other than the connection wiring connecting to the pad and connected to another device to be evaluated related to the electrode pad is cut by using an energy beam.

[0012]

Next, the present invention will be specifically described with reference to the following two embodiments. FIG.
FIG. 2 is a schematic plan view of a highly integrated circuit board according to the present invention. FIGS. 2 to 6 show each device to be evaluated (a so-called check device) and a common probe electrode pad at the time of inspection in the first embodiment. FIG. 3 is a schematic diagram showing an example of the arrangement and connection wiring for these. FIG. 7 is a schematic view showing a modified example in which an electrode pad is formed at the same time when a connection wiring is formed.

FIG. 8 is a schematic diagram showing connection wiring in the second embodiment, and FIGS. 9 to 12 show cutting of connection wiring when a connection wiring is specified for a selected device under evaluation. It is a schematic diagram which shows a case.

FIG. 1 shows a configuration in which electrical characteristics of a device to be evaluated formed on a chip 1 can be tested via a probe electrode pad (described later) with which a test probe (not shown) contacts. Is shown. Note that, as usual, the chip 1 has an internal cell region 2 at the center thereof.
In addition, a large number of electrode pads 3 as external connection terminals are arranged and formed outside each edge of the internal cell region 2.

In this embodiment, a free area is provided at one corner of the chip 1 for evaluation of various electronic functional elements formed on the chip 1 (in particular, the internal cell area 2). The evaluation elements 4 to 7 and the common probe electrode pads 8a to 8c are collectively configured and arranged simultaneously with the configuration of the electronic functional element.

As another embodiment, a further element to be evaluated and a common probe electrode pad (both not shown) are divided into several parts such as another corner portion of the chip 1.
Needless to say, they may be configured and arranged collectively.

(First Embodiment) In the highly integrated circuit chip according to this embodiment, for the devices 4 to 7 to be evaluated, wirings necessary for connection with electrode pads 8a to 8c (described later) are required. A gap for securing a route is provided in the empty area. The devices to be evaluated 4 to 7 are, for example, an electron-emitting device, a metal capacitor, and a resistor.

The connection wiring selects an element to be evaluated,
At the time of testing, an energy beam such as FIB is formed in the gap so as to connect one of the selected devices to be evaluated and the corresponding electrode pad. Each of these cases is shown in FIGS.

That is, as shown in FIG. 2, no connection wiring is formed on the initial chip. However, when the device to be tested is selected, for example, the device as an electron-emitting device can be used. When the evaluation element 4 is selected for inspection,
Prior to the inspection using the inspection probe, first, metal ions such as Al are linearly implanted between the device under evaluation 4 and the electrode pads 8a and 8b by an energy beam such as FIB. Of the connection wiring 9a
Is formed (see FIG. 3).

Similarly, when the element 5 to be evaluated as a metal capacitance element is selected, prior to the inspection using the inspection probe, first, the element 5 to be evaluated and the electrode pads 8a and 8a
Metal ions, such as Al, are linearly implanted with an energy beam such as FIB between the gate electrode b and the connection wiring 9b to form the connection wiring 9b with a required wiring resistance value (see FIG. 3).

When the device to be evaluated 6 or 7 as a resistance element is selected, prior to the inspection using the inspection probe, first, between the device to be evaluated 6 or 7 and the electrode pads 8a and 8c. With an energy beam such as FIB, for example, metal ions such as Al are linearly implanted,
The connection wiring 9c or 9d is formed with a required wiring resistance value (see FIGS. 4 and 5).

It is preferable that a terminal portion for connection wiring is extended outside each of the devices to be evaluated. This is to avoid thermal effects on the device under evaluation due to the energy beam.

As described above, only the element to be evaluated and the common probe electrode pad are collectively constructed and arranged in the empty area, and there is no common connection wiring, so that the occupied area for that can be reduced. . All that is required here is to leave a space for providing a dedicated connection wiring between one selected device under evaluation and the corresponding electrode pad in the free space. That is, the gap is
Any width may be used as long as it passes through one wiring.

Thus, the space occupied by the device to be evaluated and the corresponding common probe electrode pad can be reduced, and an empty area on the chip can be relatively easily secured without lowering the degree of integration. .

As shown in FIG. 7, a part of the common probe electrode pad (although it may be all) is formed at the same time when the dedicated connection wiring is formed after selecting the device to be evaluated. May be. Such modifications belong to the technical category of the present invention.

(Second Embodiment) In this embodiment, connection wirings 9a to 9d to electrode pads 8a to 8c are provided for each of the devices 4 to 7 to be evaluated. Simultaneously with the configuration (not shown), when the device to be evaluated and the common probe electrode pad are collectively configured and arranged, they are previously formed in the empty area. The connection wiring in this embodiment is configured to be connected to the corresponding electrode pad by a dedicated line for each element to be evaluated (see FIG. 8).

Then, when a device to be evaluated is selected and a test for evaluating the characteristics thereof is performed, other than the connection wiring connecting the selected device to be evaluated and the electrode pad, another device related to the electrode pad is used. The connection wiring of the device under evaluation is cut using an energy beam such as FIB.

For example, FIG. 9 shows a case where the device under evaluation 4 is selected as an electron discharge device, and only a part of the connection wiring 9b to the metal capacitor 5 in the electrode pad 8b needs to be cut off. . This is because the inspection is performed by the contact of the inspection probe (not shown) with respect to the electrode pads 8a and 8b corresponding to the device under evaluation 4. In this case, the connection wiring with the electrode pad 8c is not related. Absent.

The configuration shown in FIG. 10 is a case where the device under evaluation 5 is selected as a metal capacitor. In this case, only the connection wiring 9a in the electronic pad 8b needs to be cut. Further, when the device under evaluation 6 (see FIG. 11) or the device under evaluation 7 (see FIG. 12) as the resistance element is selected, one of the unused connection lines 9d or 9c in the electronic pad 8c is disconnected. do it.

As described above, in this embodiment, the connection wirings 9a to 9d to the common probe electrode pads 8a to 8c are provided for each of the devices to be evaluated 4 to 7 formed on the chip 1, The connection wiring between the electrode pad and another device to be evaluated relating to the selected device to be evaluated is cut off. Therefore, since the connection wiring is independently provided for each element to be evaluated, the connection wiring between each element to be evaluated and the electrode pad can be prepared in advance with a wiring resistance which does not affect the evaluation at the time of inspection.

[0031]

Next, more specific examples of the present invention will be described below. Here, three probe electrode pads having a square area of 60 × 60 μm are used. For example, 20 electrode pads are used to evaluate various electronic functional elements on a chip. The elements to be evaluated are collectively constructed and arranged together with the electrode pads in an empty area on the chip.

Here, in the conventional arrangement, the device under evaluation 2
Dedicated electrode pads (3 each) for 0
Is provided (total: 60 electrode pads are required), from about 460 × 460 μm ² to about 100 × 10
The occupied area up to 0 μm ² can be reduced. This leads to a reduction in chip size and an improvement in the degree of integration in the above-described embodiments.

Further, as shown in the first embodiment,
In the type in which the connection wiring is performed after selecting the device to be evaluated for inspection, the connection wiring is provided in advance for all the devices to be evaluated with respect to the common electrode pad (partly disconnected,
As compared with (or partial connection), the installation area of the route required for the connection wiring can be reduced, so that the chip size is further reduced and the degree of integration is further improved.

[0034]

The present invention, as described in detail above, has a configuration in which the electrical characteristics of a device to be evaluated formed on a chip can be tested via a probe electrode pad with which a test probe contacts. In a high-integrated circuit chip, a device to be evaluated for an electronic functional device formed on the chip is collectively formed in a vacant region around the internal cell region, and a probe electrode pad shared therewith is formed. At the same time, a gap for securing a route necessary for connection wiring with the electrode pad is provided in the empty region for the element to be evaluated.

In the present invention, at the stage of selecting a device to be tested to be tested, the connection wiring is formed by using an energy beam to connect the device to be evaluated to the electrode pad; After that, a test for evaluation is performed.

Therefore, the space occupied by providing the common wiring is avoided, and the connection wiring is provided only for the selected device to be evaluated, so that the device to be evaluated and the corresponding common probe electrode pad occupy it. An empty area on a chip can be relatively easily secured without reducing the space and the integration degree.

According to the present invention, there is provided a highly integrated circuit chip having a structure capable of testing an electrical characteristic of a device to be evaluated formed on a chip through a probe electrode pad with which a test probe contacts. In the empty area around the area, the elements to be evaluated for the electronic functional elements formed on the chip are collectively configured, a probe electrode pad shared therewith is provided, and each of the elements to be evaluated is provided. In addition, the connection wiring with the electrode pad is formed in the empty area.

In the present invention, at the stage where the device to be tested is selected, other than the connection wiring for connecting the selected device to be evaluated and the electrode pad, The connection wiring of the device under evaluation is cut using an energy beam.

Therefore, it is possible to prepare in advance the connection wiring between each element to be evaluated and the electrode pad with a wiring resistance that does not affect the evaluation at the time of inspection.

[Brief description of the drawings]

FIG. 1 is a schematic plan view of a highly integrated circuit board according to the present invention.

FIG. 2 is a schematic diagram showing an example of arrangement with respect to each device to be evaluated and a common probe electrode pad at the time of inspection in the first embodiment.

FIG. 3 is a schematic diagram showing an example (1) of connection wiring between each device to be evaluated and a common probe electrode pad during an inspection.

FIG. 4 is a schematic diagram showing an example (2) of connection wiring for each device to be evaluated and a common probe electrode pad at the time of inspection.

FIG. 5 is a schematic diagram showing an example (3) of connection wiring for each device to be evaluated and the common probe electrode pad at the time of inspection.

FIG. 6 is a schematic diagram showing an example (4) of connection wiring between each device to be evaluated and the common probe electrode pad at the time of inspection.

FIG. 7 is a schematic diagram showing a modification of the connection wiring for each device to be evaluated and the common probe electrode pad at the time of inspection in the first embodiment.

FIG. 8 is a schematic diagram showing connection wiring according to a second embodiment of the present invention.

FIG. 9 is a schematic diagram showing an example (1) of disconnection of a connection wiring when a connection wiring is specified for a selected device under evaluation.

FIG. 10 is a schematic diagram showing an example (2) of disconnection of a connection wiring.

FIG. 11 is a schematic diagram showing an example (3) of disconnection of a connection wiring.

FIG. 12 is also a schematic diagram showing a case (4) of disconnection of a connection wiring.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Chip 2 Internal cell area 3 Electrode pad 4-7 Device under evaluation 8a-8c Probe electrode pad 9a-9d Connection wiring

Claims (9)

[Claims] In a highly integrated circuit chip having a structure capable of testing an electrical characteristic of a device to be evaluated formed on a chip via a probe electrode pad with which a test probe comes in contact, a periphery of an internal cell region is provided. In a certain empty area, an element to be evaluated for an electronic functional element formed on the chip,
Integrally configured and provided with a probe electrode pad shared therewith, and for the device under evaluation, a gap for securing a route necessary for connection wiring with the electrode pad is provided in the empty region. A highly integrated circuit chip having a device to be evaluated. 2. The method according to claim 1, wherein the connection wiring is formed in the gap so as to connect the device to be evaluated and the electrode pad by using an energy beam when a device to be evaluated is selected and tested. The highly integrated circuit chip according to claim 1, further comprising: a device to be evaluated. 3. The highly integrated circuit chip according to claim 2, wherein at least a part of said electrode pad is formed when said connection wiring is formed. 4. The highly integrated circuit chip according to claim 1, wherein the empty area is located at a corner of the chip. 5. A method for testing a device to be evaluated in a highly integrated circuit chip having a device to be evaluated on a chip via a probe electrode pad with which the test probe contacts, In a vacant area around the internal cell area, elements to be evaluated for the electronic functional elements formed on the chip are collectively configured, a probe electrode pad shared therewith is provided, and For the device, a gap for securing a route necessary for connection wiring with the electrode pad is provided in the vacant region, and at the stage of selecting a device under test to be tested, using an energy beam. A method for testing a device to be evaluated for a highly integrated circuit chip, wherein the connection wiring is formed to connect the device to be evaluated to the electrode pad, and then a test for evaluation is performed. 6. The method according to claim 5, wherein at least a part of the electrode pad is formed when the connection wiring is formed. 7. A highly integrated circuit chip having a configuration capable of testing an electrical characteristic of a device to be evaluated formed on a chip via a probe electrode pad with which a test probe comes into contact. In a certain empty area, an element to be evaluated for an electronic functional element formed on the chip,
A probe electrode pad commonly used for this purpose is provided, and a connection wiring with the electrode pad is formed in the empty area for each device to be evaluated. Highly integrated circuit chip with evaluation elements. 8. When a device to be evaluated is selected and a test is performed, connection of another device to be evaluated related to the electrode pad other than the connection wiring connecting the selected device to be evaluated and the electrode pad. 8. The highly integrated circuit chip provided with the device under evaluation according to claim 7, wherein the wiring is cut using an energy beam. 9. A method of testing a device to be evaluated in a highly integrated circuit chip having a device to be evaluated on a chip via a probe electrode pad with which the test probe contacts, In an empty area around the internal cell area, elements to be evaluated for the electronic functional elements formed on the chip are collectively configured, and a probe electrode pad shared therewith is provided. For each evaluation element, the connection wiring with the electrode pad is formed in the empty area, and at the stage of selecting the element to be tested to be tested,
Characterized in that, other than the connection wiring connecting the selected device under evaluation and the electrode pad, the connection wiring of another device under evaluation related to the electrode pad is cut using an energy beam, Inspection method for device under evaluation of integrated circuit chip.