JP2000031221A - Semiconductor integrated circuit device and testing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a semiconductor integrated circuit device capable of surely rejecting a faulty chip in the testing time also avoiding the expansion of chip size and the increase in testing time. SOLUTION: Separately from the pads for interface connected by inner circuit or power supply and a pad leading-out line 11a, a testing pad 3a for discriminating the breakage of the chip 1 is formed thereon. Next, this testing pad 3a and inner circuit or power supply is connected by a pad leading-out line 11b wired along the corners of the chip 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device capable of easily and reliably determining chip chipping, and a test method therefor.

[0002]

2. Description of the Related Art FIG. 18 is a plan view showing an example of a chip constituting a conventional semiconductor integrated circuit device. In the drawing, 1 is a chip of a semiconductor integrated circuit device, 2 is an interface pad arranged on the chip 1, and 11a is a pad lead-out line connecting the interface pad 2 to an internal circuit or power supply of the chip 1. is there.

FIG. 17 is a plan view showing an example of arranging chips 1 on a wafer in a process of manufacturing a semiconductor integrated circuit device. In the drawing, 100 is a wafer, 1a is a complete chip arranged on the wafer 100 without chip chipping, and 1b is an incomplete chip arranged on the wafer 100 with a part thereof chipped. In FIG. 17, incomplete chips 1b are hatched to distinguish them from complete chips 1a that are not hatched.

In the process of manufacturing a semiconductor integrated circuit device, FIG.
As shown in FIG. 7, since the rectangular chips 1 are arranged on the disc-shaped wafer 100, incomplete chips 1b partially missing therefrom are inevitably present. Such an incomplete chip 1b with chip missing is obviously a defective product, and it is necessary to reject it.

Here, such a chip 1 is attached to the wafer 10
A case where a part of the chip 1 is actually chipped when the chip 1 is built into 0 will be described. FIG. 19 is a plan view showing an example of an incomplete chip 1b in which a chip is missing. As shown in FIG. 19, even if a part of the chip 1 is chipped to become an incomplete chip 1b, the chip 1 constituting the conventional semiconductor integrated circuit device may not be able to perform a normal test depending on the chip chipping condition. Interface pad 2
, The internal circuit also operates normally, and may be determined to be non-defective. Therefore, it is impossible to reliably reject an incomplete chip 1b having a chip missing.

FIG. 20 is a plan view showing another example of the chip 1 constituting the conventional semiconductor integrated circuit device, and the corresponding parts are denoted by the same reference numerals as in FIG. 18 and will not be described. In the figure, reference numerals 1000 and 1001 are arranged in a chip 1 and connected to interface pads 2 by pad lead lines 11a, for example, DR
It is a circuit such as an AM circuit and a logic circuit, or an analog circuit and a logic circuit.

In the chip 1, when the circuit 1000 and the circuit 1001 are individually tested, for example, the chip 1 is connected to the DRAM circuit 1000 and the logic circuit 1
001 and the DRAM test and the logic test are performed separately. When the DRAM circuit 1000 is tested, the interface test of the interface pad 2 related to the normal DRAM circuit 1000 and the DRAM test are performed.
A circuit test of the circuit 1000 is performed, but a test of the logic circuit 1001 is not performed.

Here, such a chip 1 is attached to the wafer 10
A case will be described in which a chip is actually chipped when it is built into zero. FIG. 21 is a plan view showing an example of an incomplete chip 1b in which a chip is missing. FIG.
As shown in FIG. 1, even if an incomplete chip 1b in which a part of the circuit
In the test of 0, the interface pad 2 of the circuit 1000 alone can take an interface, and the circuit 1
000 may also operate normally and be determined to be good. Therefore, also in this case, similarly, the chip 1b having the chip missing cannot be reliably rejected at the time of the test.

However, in this case, the chip 1b having the chip missing can be rejected by testing the circuit 1001. However, the circuit 1000
In addition to the above test time, a test time for the circuit 1001 is required, and a great deal of time is wasted in the test.

[0010] Other documents that describe a semiconductor integrated circuit device capable of determining chip chipping include, for example, Japanese Patent Application Laid-Open Nos. 5-211222 and 4-199651. Japanese Patent Application Laid-Open No. H5-211222 discloses an arrangement in which a regular check pad for detecting chip chipping is disposed at a corner of a chip. Also, there is disclosed one in which a defect detection wiring for detecting chip chipping is arranged.

[0011]

Since the conventional semiconductor integrated circuit device is constructed as described above, the interface of the interface pad 2 may be changed in a normal test depending on the incomplete chipping of the chip 1b. Since the internal circuit also operates normally and may be determined to be a non-defective product, there is a problem that an incomplete chip 1b with chip missing cannot be reliably rejected.

Further, in the chip 1 including the plurality of circuits 1000 and 1001, even if one of the circuits (circuit 1001) becomes an incomplete chip 1b in which a part thereof is chipped, the other circuit (circuit 1000) is not tested. Since the interface pad 2 of only this circuit can take an interface and the internal circuit operates normally, it may be determined that the circuit is good. Therefore, also in this case, the chip 1b having the chip chip cannot be reliably rejected, and all the circuits 1000 and 1001 on the chip 1 are tested to surely reject the incomplete chip 1b. There is a problem that wasteful test time is wasted.

In the semiconductor integrated circuit device disclosed in Japanese Patent Application Laid-Open No. 5-211222, it is necessary to arrange a regular check pad for determining chip chipping near a corner of the chip. If there is a mark of a process or an assembly, or a regular check pad cannot be arranged at a corner due to wiring rules or the like, it cannot be applied, and even if it is applied, there is a problem that the chip size needs to be increased.

Further, in the semiconductor integrated circuit device disclosed in Japanese Patent Application Laid-Open No. 4-199651, it is necessary to arrange a defect detection wiring for determining chip chipping so as to surround the chip. To avoid this increase in chip size, even if the defect detection wiring is used as a buried layer, there is a problem that the pad becomes uneven and is not suitable for bonding.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and it is possible to reliably reject an incomplete chip having a chip chip during a test.
An object of the present invention is to provide a semiconductor integrated circuit device capable of suppressing an increase in chip size and preventing an increase in test time.

Another object of the present invention is to provide a method for testing a semiconductor integrated circuit device for determining chip chipping of a chip in the semiconductor integrated circuit device configured as described above.

[0017]

In a semiconductor integrated circuit device according to the present invention, a test pad for determining chip chipping of the chip is provided on the chip, and a pad lead-out line is provided along a corner of the chip. The test pad is connected to an internal circuit of the chip or a power supply.

A semiconductor integrated circuit device according to the present invention includes a test pad connected to an internal circuit or a power supply by a pad lead line wired along a corner of a chip, and a pad lead line arranged at a corner of the chip. And a test pad connected to an internal circuit or a power supply.

In the semiconductor integrated circuit device according to the present invention, a test pad for determining chip chip of the chip is provided on the chip, and a pad lead-out line is provided between the test pad and the interface pad. It is made to connect by.

In the semiconductor integrated circuit device according to the present invention, a test pad connected to an interface pad by a pad lead line is arranged at a corner of a chip.

In the semiconductor integrated circuit device according to the present invention, a test pad is connected to an interface pad by a pad lead line wired along a corner of a chip.

A semiconductor integrated circuit device according to the present invention comprises a test pad arranged at a corner of a chip and connected to an interface pad by a pad lead line, and a pad lead line wired along a corner of the chip. The test pads connected to the interface pads are mixed.

In the test method for a semiconductor integrated circuit device according to the present invention, a diode characteristic or a short-circuit characteristic of a protection circuit of an internal circuit is confirmed at the time of an interface test for determining chip chipping. .

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a plan view showing an example of a chip constituting a semiconductor integrated circuit device according to Embodiment 1 of the present invention. In the figure, reference numeral 1 denotes a chip constituting the semiconductor integrated circuit device. Reference numeral 2 denotes an interface pad disposed on the chip 1, and reference numeral 11a denotes a pad lead line connecting the interface pad 2 to an internal circuit of the chip 1 or a power supply. These are the same as those in the conventional semiconductor integrated circuit device shown by the same reference numerals in FIG.

Reference numeral 3a denotes a test pad arranged on the chip 1 together with the interface pad 2 for determining chip chipping. Reference numeral 11b denotes a pad lead line that is wired along a corner of the chip 1 and connects the test pad 3a to an internal circuit of the chip 1 or a power supply. Note that the test pad 3a, which is newly provided only for the purpose of determining chip chipping, shares the one already provided as the interface pad 2 used for a normal interface. Such a configuration may be used.

As described above, in the semiconductor integrated circuit device according to the first embodiment, the chip 1 has the test pads 3a
And a pad lead-out line 11b connected along a corner of the chip 1 for connecting the test pad 3a to an internal circuit or a power supply.

Next, a description will be given of a case where when such a chip 1 is formed on a wafer 100 as shown in FIG. 17, a part of the chip 1 is actually chipped and becomes an incomplete chip 1b. . FIG. 2 is a plan view showing an example of the incomplete chip 1b in which the chip has been chipped. As shown in FIG. 2, if the chip 1 is an incomplete chip 1 b partially chipped and chipped, the pad lead-out line 11 b wired along a corner of the chip 1 b is cut. . Since the pad lead-out line 11b connects the test pad 3a for determining chip chipping to an internal circuit or a power supply, if the pad is disconnected, the chip 1b is tested using the test pad 3a. By doing so, a defect can be detected.

Here, the definition of the corner of the chip 1 in this case will be described. FIG. 3 is a partial plan view showing a corner portion of chip 1 of the semiconductor integrated circuit device according to the first embodiment in an enlarged manner. In FIG. 3, reference numeral 301 denotes a dicing line for cutting off the chip 1 formed on the wafer 100, and reference numeral 500 denotes a probe needle which comes into contact with the test pad 3a during a test. The other parts are denoted by the same reference numerals as the corresponding parts in FIG. 2 and the description thereof is omitted.

[0029] In FIG. 3 (a), the pad lead lines 11b connected to the test pad 3a for discriminating chipping is spaced by a distance r ₁ from the boundary line between the chip 1 and the dicing line 301 Wired.
Such a chip 1 is placed on a wafer 10 as shown in FIG.
When it is made to be 0 and the chip is actually chipped, as shown in FIG. 3A, the pad lead-out line 11b is cut off by the chip chipping. Therefore, even if the probe needle 500 contacts the test pad 3a during the test, it cannot contact the internal circuit or the power supply. That is, the pad lead lines 11b connected to the test pad 3a is, when taking apart by a distance r ₁ from the boundary line between the chip 1 and the dicing line 301 is wired can determine the chipping during the test It is possible to do.

However, as shown in FIG. 3B, the pad lead-out line 11 to which the test pad 3a is connected
that b is, when are wired spaced from the boundary line by a distance r ₂ between the chip 1 and the dicing line 301, the pad lead lines 11b even in a state where the chip 1 is missing would be completely cut Not, but the connection is maintained in part. Therefore, when the probe needle 500 comes into contact with the test pad 3a, it becomes possible to make contact with an internal circuit, a power supply, or the like. Accordingly, the pad lead lines 11b the test pads 3a is connected, when wiring spaced a distance r ₂ from the boundary line of the chip 1 and the dicing line 301 is no longer possible to determine the chipping .

The same applies to the case shown in FIG.
When the chip 1 built at 00 is actually in a chipped state, the pad lead-out line 11b connected to the test pad 3a for determining the chipped part is
As shown in FIG. 4A, if the chip is wired at a distance of r ₃ from the boundary line between the chip 1 and the dicing line 301, chip chipping can be determined, but as shown in FIG. If you wire at intervals of r ₄ it can not determine the chipping.

That is, when the chip 1 is placed on the wafer 100 shown in FIG. 17, the test is performed from the boundary between the chip 1 and the dicing line 301 from which all the incomplete chips 1b can be rejected as defective. The distance to the pad lead line 11b to which the pad 3a is connected is defined as a corner.

As described above, the test pad 3a for determining chip chipping is provided, and the pad lead-out line 11a is provided.
Regardless of the state of the chip 1 in which b is wired along the corner in any state shown in FIG. 17, the incomplete chip 1b can be surely rejected during the test. Also, in the structure, a test pad 3a is provided, and a pad lead line 11b connected to the test pad 3a is
Since the wiring is only performed along the corners, the realization is easy.

In the first embodiment, a chip 1 of a conventional semiconductor integrated circuit device configured as shown in FIG.
It is also possible to apply to. That is, the test pad 3a is provided, and the pad lead line 11b to which the test pad 3a is connected is wired along the corner of the chip 1, and the circuit 1
000 circuit test and its test pad 3a
, An incomplete chip 1b can be reliably rejected. Further, if the incomplete chip 1b can be rejected in the test of the circuit 1000, the time for testing the circuit 1001 becomes unnecessary, and the increase in the test time can be suppressed.

Further, a test pad 3a for discriminating chip chipping is provided on the chip 1, and a pad lead-out line 11b connected to the test pad 3a is wired along a corner of the chip 1. It is not always necessary to provide the pad 3a at a corner. Therefore, chip 1
It is possible to cope with a case where a mark of a process or an assembly is provided at a corner of the chip 1 or the test pad 3a cannot be arranged at a corner of the chip 1 due to wiring rules or the like, thereby preventing an increase in chip size.

The test pad 3a is a pad newly provided only for determining chip chipping,
Since a pad shared with the interface pad may be used, this also effectively prevents the chip size from increasing.

As described above, according to the first embodiment, it is possible to reliably reject an incomplete chip 1b having a chip chip at the time of a test and to suppress an increase in chip size. This has the effect of realizing a semiconductor integrated circuit device that can prevent an increase in test time.

Embodiment 2 In the first embodiment, a test pad 3a for determining chip chipping is provided on a chip 1, and a pad lead-out line 1 connecting the test pad 3a to an internal circuit or a power supply is provided.
Although the case where 1b is wired along each corner of chip 1 has been described, some of test pads 3a for determining chip chipping may be arranged at the corner of chip 1. .

FIG. 5 shows such a second embodiment of the present invention.
1 is a plan view showing an example of a chip constituting a semiconductor integrated circuit device according to the present invention. In the drawing, reference numeral 3b denotes a test pad arranged at a corner of the chip 1 for determining chip chipping, and 11c denotes a pad lead-out line connecting the test pad 3b to an internal circuit or a power supply. It is. Similarly to the test pad 3a for testing, the test pad 3b for determining chip lack is a pad separately prepared only for the purpose of determining chip lack and is shared with a normal interface. Pad.

In the second embodiment, test pads 3b for determining chip chipping are arranged at two corners on one diagonal of chip 1, and pad lead-out lines 11c of chip 1 are provided. Not routed along corners. Further, two corners on the other diagonal line of the chip 1 are provided along the corners with the pad lead-out lines 11b connected to the test pads 3a.
Are wired. The other parts are denoted by the same reference numerals as the corresponding parts in FIG. 1, and the description thereof is omitted.

Next, a description will be given of a case where a part of the chip 1 is actually cut off when such a chip 1 is formed on the wafer 100 as shown in FIG. FIG. 6 is a plan view showing an example of an incomplete chip 1b in which a chip is missing. As shown in FIG. 6, when a part of the chip 1 is chipped and becomes an incomplete chip 1b, the chip 1b
The test pads 3b provided at the corners for determining chip chipping are missing or incomplete. Therefore, a test using the test pads 3b provided at the corners of the chip 1b cannot be performed, and a defect can be detected by testing the chip 1 using the test pads 3b.

Here, the definition of the corner of the chip 1 in this case will be described. FIG. 7 is an enlarged partial plan view showing a corner portion of chip 1 of the semiconductor integrated circuit device according to the second embodiment. Note that the same reference numerals as in FIG. 6 denote the same parts, and a description thereof will be omitted.

[0043] In FIG. 7 (a), the test pad 3b for discriminating chipping, are arranged spaced a distance r ₅ from the boundary line between the chip 1 and the dicing line 301. When such a chip 1 is formed on the wafer 100 and the chip is actually chipped, as shown in FIG. 7A, the probe needle 500 is brought into contact with the test pad 3b during the test. Even so, the test pad 3b does not exist due to chip lack, and the probe needle 500 cannot be brought into contact therewith. Therefore, the test pads 3b at the corners of the chip 1
But if it is arranged to take by a distance r ₅ from the boundary line between the chip 1 and the dicing line 301, it is possible to determine the chipping.

However, as shown in FIG. 7B, test pads 3b for determining chip chipping are arranged at a distance r ₆ from the boundary between chip 1 and dicing line 301. In this case, the test pad 3b exists even when the chip 1 is chipped. Therefore, when the probe needle 500 comes into contact with the test pad 3b, it can contact an internal circuit, a power supply, or the like. Therefore, the test pad 3b, when arranged spaced a distance r ₆ from the boundary line between the chip 1 and the dicing line 301 is no longer possible to determine the chipping.

The same applies to the case shown in FIG.
When the chip 1 formed at 00 is actually in a chipped state, the test pad 3b provided at the corner of the chip 1b for determining the chipped state is replaced by the test pad 3b shown in FIG.
As shown in, if it is arranged spaced by a distance r ₇ from the boundary line between the chip 1 and the dicing line 301, it can determine the chipping, but the distance r ₈ as shown in FIG. 8 (b) And chip missing can no longer be determined.

That is, when the chip 1 is placed on the wafer 100 shown in FIG. 17, all of the imperfect chips 1b can be rejected as defectives. 3b provided at the corner of chip 1b to determine chipping
The distance to is defined as the corner.

According to the second embodiment, as in the first embodiment, the incomplete chip 1b having a chip chip can be reliably rejected at the time of the test, so that the chip size can be increased and the test time can be reduced. A semiconductor integrated circuit device capable of preventing an increase can be realized, and a test pad 3b can be arranged at a corner of the chip 1 and a pad lead 11b from the test pad 3a can be wired. As a result, effects such as improvement in the degree of freedom of design can be obtained.

Embodiment 3 FIG. 9 is a plan view showing an example of a chip constituting a semiconductor integrated circuit device according to a third embodiment of the present invention. The corresponding portions are denoted by the same reference numerals as in FIG. 1 and description thereof is omitted. In the figure, 3c is chip 1
11d are test pads arranged at the corners for determining chip chipping.
This is a pad lead-out line connecting c to the interface pad 2. Therefore, the test pad 3c arranged at the corner of the chip 1 is connected to an internal circuit or a power supply via the pad lead line 11d, the interface pad 2, and the pad lead line 11a.

Next, a description will be given of a case where a part of the chip 1 is actually cut off when such a chip 1 is formed on the wafer 100 as shown in FIG. FIG. 10 is a plan view showing an example of an incomplete chip 1b in which a chip is missing. As shown in FIG. 10, when a part of the chip 1 is chipped to become an incomplete chip 1b, the test pad 3c provided at a corner of the chip 1b is lost or becomes incomplete.

Therefore, the test using the test pads 3c provided at the corners of the chip 1 cannot be performed. Therefore, by testing the chip 1b using the test pads 3c, it is possible to detect a defect. Become. Thus, the test pad 3c for determining chip chipping is provided at the corner of the chip 1, and the pad lead-out line 1c is provided.
FIG. 9 shows a connection with the interface pad 2 by 1d.
17 can be reliably rejected at the time of the test, regardless of the state shown in FIG.

In the semiconductor integrated circuit device according to the third embodiment, a test pad 3c for determining chip chip is provided at a corner of the chip 1, and the test pad 3c is connected to the interface pad 2 by a pad lead-out line 11d. This is easy to achieve.

Further, even when the present invention is applied to the chip 1 of the conventional semiconductor integrated circuit device configured as shown in FIG. 20, a test pad 3c for determining chip chip is provided at a corner of the chip 1, It is connected to the interface pad 2 by the pad lead line 11d,
Simultaneously with the test of the circuit 1000, its test pad 3
By performing the test using c, the incomplete chip 1b can be surely rejected, and if the incomplete chip 1b can be rejected in the test of the circuit 1000, the circuit 1001 can be rejected. No time is required, and an increase in test time can be suppressed.

Further, the test pads 3c arranged at the corners of the chip 1 are for determining chip chipping and do not need to be bonded at the time of assembly, so that the size of the test pads 3c is large. Can be reduced. Therefore, even if there is a process or assembly mark at the corner of the chip 1, the test pad 3c can be arranged at the corner of the chip 1, and the chip size can be prevented from increasing.

The test pads 3c arranged at the corners of the chip 1 are connected to the interface pads 2 by the pad lead lines 11d, so that the arrangement of the interface pads 2 is not affected. This is advantageous when wiring cannot be routed from the internal circuit or when the interface pad 2 cannot be moved due to wiring rules or the like, and it is possible to suppress an increase in chip size.

Further, by providing the test pads 3c arranged at the corners, a plurality of tests can be performed.
That is, in the chip 1 including the internal circuits 1000 and 1001 as shown in FIG. 20 that requires a plurality of tests, it is necessary to perform the needle application to the interface pad 2 a plurality of times during the plurality of tests. As a result, the interface pad 2 may be damaged, and when it affects the bonding, it is effective in preventing the bonding.

As described above, according to the third embodiment, an incomplete chip 1b having a chipped chip can be reliably rejected at the time of a test, and an increase in chip size and an increase in test time can be prevented. Along with
An effect is obtained that a semiconductor integrated circuit device that can withstand a plurality of tests can be realized.

In the above description, the test pads 3c for determining chip chipping are provided at the corners of the chip 1. However, as shown in FIG. 11, the interface pads 2 are arranged at the corners. If you have
The test pad 3c arranged at a position other than the corner may be connected to the interface pad 2 by the pad lead-out line 11d, and the same effect is obtained.

Embodiment 4 FIG. 12 is a plan view showing an example of a chip constituting a semiconductor integrated circuit device according to a fourth embodiment of the present invention. The corresponding parts are denoted by the same reference numerals as in FIG. 1 and description thereof is omitted. In the figure, reference numeral 3d denotes a test pad for determining chip chipping, and 11e denotes a pad lead line which is wired along a corner of the chip 1 and connects the test pad 3d to the interface pad 2. is there. Therefore, the test pad 3d is connected to the pad lead line 11e, the interface pad 2, and the pad lead line 11a.
Connected to internal circuit or power supply.

Next, a description will be given of a case where a part of the chip 1 is actually cut off when such a chip 1 is formed on the wafer 100 as shown in FIG. FIG. 13 is a plan view showing an example of an incomplete chip 1b in which a chip is missing. As shown in FIG. 13, an incomplete chip 1b in which the chip 1 is partially chipped.
In the case of, the pad lead-out line 11e wired along the corner of the chip 1b is cut.

The pad lead-out line 11e wired along this corner connects the test pad 3d for determining chip chipping and the interface pad 2, so that the test pad 3d is used for the chip. If the disconnection is detected by performing the test 1, the defect can be detected. Thus, the test pad 3d
The chip 1b shown in FIG. 11, which is connected to the interface pad 2 by a pad lead wire 11e laid out along the corner of the chip 1 in the state shown in FIG. Sometimes it can be rejected reliably.

In the semiconductor integrated circuit device according to the fourth embodiment, a test pad 3d for determining chip chipping is provided, and the test pad 3d is provided along a corner of the chip 1 by a pad lead-out line 11e. This is easy to implement because it is only connected to 2.

Also, when applied to a chip 1 of a conventional semiconductor integrated circuit device configured as shown in FIG.
A test pad 3d for determining chip chipping is provided, which is connected to the interface pad 2 by a pad lead wire 11e wired along a corner of the chip 1, and simultaneously with the circuit test of the circuit 1000, By performing an interface test using the test pad 3d, it is possible to reliably reject the incomplete chip 1b, and if the circuit 1000 can be rejected, the time for testing the circuit 1001 becomes unnecessary. An increase in time can be suppressed.

Further, the test pads 3d arranged at the corners of the chip 1 are for determining chip chipping, and need to be bonded at the time of assembly as in the case of the third embodiment. Therefore, the size of the test pad 3d can be reduced. Further, by connecting the test pad 3d to the interface pad 2 by a pad lead line 11e wired along the corner of the chip 1, it is not necessary to provide the test pad 3d at the corner of the chip 1. ing. This is advantageous when there are process or assembly marks at the corners of the chip 1 or when the test pads 3d cannot be arranged at the corners of the chip 1 due to wiring rules or the like, thereby suppressing an increase in chip size. it can.

Since the test pad 3d for determining chip chipping is connected to the interface pad 2 by the pad lead-out line 11e, it does not affect the arrangement of the interface pad 2. This is when wiring cannot be routed from the internal circuit,
Interface pad 2 according to wiring rules
This is advantageous when cannot be moved, and it is possible to suppress an increase in chip size.

Further, by providing the test pad 3d, a plurality of tests can be performed. That is, in the chip 1 including the internal circuits 1000 and 1001 as shown in FIG.
It is necessary to apply the needle to the interface pad 2 a plurality of times during a plurality of tests, thereby damaging the interface pad 2 and preventing it from affecting the bonding. It is effective to do.

As described above, according to the fourth embodiment, an incomplete chip 1b having a chip chip can be reliably rejected at the time of a test, and an increase in chip size and an increase in test time can be prevented. Along with
An effect is obtained that a semiconductor integrated circuit device that can withstand a plurality of tests can be realized.

Embodiment 5 In the fourth embodiment, a test pad 3d for determining chip lack is provided on the chip 1, and a pad lead-out line 11e connecting between the test pad 3d and the interface pad 2 is provided. Was described along each of the corners of the chip 1, but some of the test pads 3d for determining chip chipping were replaced with the same chip as in the third embodiment. Instead of the test pad 3c arranged at the first corner, the test pad 3c may be connected to the interface pad 2 by a pad lead line 11d.

FIG. 14 is a plan view showing an example of a chip constituting such a semiconductor integrated circuit device according to the fifth embodiment of the present invention. The semiconductor integrated circuit device according to the fifth embodiment is different from the above-described embodiment. 3 and a semiconductor integrated circuit device according to the fourth embodiment. Note that the same reference numerals as in FIG. 9 or FIG. 12 denote the same parts, and a description thereof will be omitted.

As shown in FIG. 14, the chip 1 is provided with interface pads 2 and test pads 3c and 3d for determining chip chipping. The interface pad 2 is connected to an internal circuit or a power supply by a pad lead line 11a. Also,
The test pads 3c arranged at the corners are connected to the interface pads 2 by pad lead lines 11d, and the other test pads 3d are connected to the interface pads by pad lead lines 11e wired along the corners of the chip 1. 2 is connected.

In the fifth embodiment, as in the third and fourth embodiments, an incomplete chip 1b having a chip chip can be surely rejected at the time of a test, and the chip size can be increased. And an increase in test time can be prevented, and a semiconductor integrated circuit device that can withstand a plurality of tests can be realized.
Since it is possible to arrange c and to arrange the pad lead-out line 11e from the test pad 3d, it is possible to obtain an effect that the degree of freedom in design can be improved.

Embodiment 6 FIG. In each of the above embodiments, the semiconductor integrated circuit device capable of reliably and easily discriminating a chip is shown. Next, a test method for discriminating a chip in such a semiconductor integrated circuit device will be described. explain. The test method of a semiconductor integrated circuit device according to the sixth embodiment of the present invention is similar to that of the first embodiment.
In the semiconductor integrated circuit device having the structure shown in the fifth embodiment, a test pad 3a for determining chip chipping is provided.
1 to 3d are performed, and FIG.
FIGS. 5 and 16 are explanatory diagrams showing an example of an interface test method for the test pads 3a to 3d.

FIG. 15A shows an interface test method using the test pads 3a to 3d utilizing the characteristics of the protection circuit of the input circuit. FIG. 15B shows the voltage V-current I of the protection circuit. Show characteristics. In FIG. 15A, reference numeral 1 denotes a chip to be tested, and reference numeral 2 denotes an interface pad. Numeral 3 generally indicates test pads 3a to 3d for determining chip chipping, and any of them may be used. 201 is P
A channel transistor 202 is an N-channel transistor, which forms an input circuit.
Reference numeral 203 denotes a protection circuit for the input circuit using a diode, and reference numeral 204 denotes a G connected to the interface pad 2.
ND electrode.

A test pad 3 for judging chip chipping is arranged on chip 1, and is connected to an input (gate terminal) of an input circuit composed of P-channel transistor 201 and N-channel transistor 202. One of the protection circuits 203 has its input (anode electrode) connected to the test pad 3, and the other has its output (cathode electrode) connected to the test pad 3. The source electrode of the N-channel transistor 202 constituting the input circuit is connected to the interface pad 2. At the time of the interface test, the interface pad 2 is connected to the GND electrode 204, and the voltage V-current I characteristic (diode characteristic) of the protection circuit 203 shown in FIG.
Is measured and the interface is confirmed.

Here, in the above description, confirmation of the interface of the input circuit has been described, but confirmation of the interface of the output circuit may be performed. In the case of an output circuit, the interface is confirmed by measuring the voltage V-current I characteristic (diode characteristic) of the protection circuit or the output transistor.

FIG. 16A shows an interface test method of the test pad 3 for confirming a short circuit with another interface pad 2 connected to the test pad 3 for determining chip chipping. FIG.
(B) shows the voltage V-current I characteristic (short characteristic). Note that the same reference numerals as in FIG. 15A denote the same parts in FIG. 16A, and a description thereof will be omitted.

At the time of the interface test, the interface pad 2 is connected to the GND electrode 204, and a voltage V is applied to the test pad 3 of the chip 1. The voltage V-current I characteristic (short characteristic) at that time shown in FIG. 16B is measured to confirm the interface.

As described above, according to the sixth embodiment, a method for confirming diode characteristics or a method for confirming short-circuit characteristics is used as an interface test of test pad 3 for determining chip chipping. Thus, an incomplete chip 1b can be reliably rejected by a simple test, and the effect of confirming the rejection in a short time can be obtained.

[0078]

As described above, according to the present invention, an internal circuit or a power supply of a chip is connected to a test pad provided on the chip by a pad lead line wired along a corner of the chip. Incomplete chip with chip missing can be reliably rejected at the time of testing, further suppressing chip size expansion,
In addition, a semiconductor integrated circuit device capable of preventing an increase in test time can be obtained.

According to the present invention, the internal circuit or the power supply mixes the test pads connected by the pad lead wires wired along the corners of the chip and the test pads arranged at the corners of the chip. With this configuration, incomplete chips can be reliably rejected at the time of testing, and it is possible to prevent an increase in chip size and test time, and to improve design flexibility. .

According to the present invention, since the test pad and the interface pad provided on the chip are connected by the pad lead-out line, an incomplete chip can be surely rejected at the time of the test, and the chip size can be reduced. It is possible to prevent an increase in test time and an increase in test time, and also to improve the durability against a plurality of tests.

According to the present invention, the test pad connected to the interface pad by the pad lead-out line is arranged at the corner of the chip, so that an incomplete chip can be reliably rejected at the time of testing. It is possible to prevent an increase in size and an increase in test time, and to improve the durability against a plurality of tests.

According to the present invention, the test pad is connected to the interface pad via the pad lead-out line arranged along the corner of the chip, so that an incomplete chip can be surely removed during the test. Rejection is possible, and it is possible to prevent an increase in chip size and an increase in test time, and to improve the durability against a plurality of tests.

According to the present invention, the test pads connected to the interface pads by the pad lead wires arranged along the corners of the chip and the test pads arranged at the corners of the chip are mixed. With this configuration, imperfect chips can be reliably rejected during testing, chip size and test time can be prevented, so that it can withstand multiple tests and design flexibility is improved. There are effects such as doing.

According to the present invention, a method for confirming the diode characteristics or a method for confirming the short-circuit characteristics is used as the interface test of the test pad. There is an effect that a test method for a semiconductor integrated circuit device which can be rejected and can be confirmed in a short time can be obtained.

[Brief description of the drawings]

FIG. 1 is a plan view showing an example of a chip of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a plan view showing an example of an incomplete chip according to the first embodiment.

FIG. 3 is an enlarged partial plan view showing an example of a corner portion of the chip according to the first embodiment;

FIG. 4 is an enlarged partial plan view showing another example of the corner portion of the chip according to the first embodiment;

FIG. 5 is a plan view showing an example of a chip of a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 6 is a plan view showing an example of an incomplete chip according to the second embodiment.

FIG. 7 is an enlarged partial plan view showing an example of a corner portion of a chip according to a second embodiment.

FIG. 8 is an enlarged partial plan view showing another example of the corner portion of the chip according to the second embodiment.

FIG. 9 is a plan view showing an example of a chip of a semiconductor integrated circuit device according to a third embodiment of the present invention.

FIG. 10 is a plan view showing an example of an incomplete chip according to a third embodiment.

FIG. 11 is a plan view showing another example of the chip of the semiconductor integrated circuit device according to the third embodiment.

FIG. 12 is a plan view showing an example of a chip of a semiconductor integrated circuit device according to a fourth embodiment of the present invention.

FIG. 13 is a plan view showing an example of an incomplete chip according to the fourth embodiment.

FIG. 14 is a plan view showing an example of a chip of a semiconductor integrated circuit device according to a fifth embodiment of the present invention.

FIG. 15 is an explanatory diagram showing an example of a test method for a semiconductor integrated circuit device according to a sixth embodiment of the present invention.

FIG. 16 is an explanatory diagram showing another example of the test method of the semiconductor integrated circuit device according to the sixth embodiment of the present invention.

FIG. 17 is a plan view showing an example of arranging chips on a wafer in the process of manufacturing the semiconductor integrated circuit device of the present invention and the conventional one.

FIG. 18 is a plan view showing an example of a chip of a conventional semiconductor integrated circuit device.

19 is a plan view showing an example of an incomplete chip of the conventional semiconductor integrated circuit device shown in FIG.

FIG. 20 is a plan view showing another example of a chip of a conventional semiconductor integrated circuit device.

21 is a plan view showing an example of an incomplete chip of the conventional semiconductor integrated circuit device shown in FIG.

[Explanation of symbols]

1 chip, 2 interface pads, 3, 3a ~
3d test pad, 11a to 11e pad lead wire, 203 protection circuit.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Nobuyuki Fujii, 2-3-2 Marunouchi, Chiyoda-ku, Tokyo, Japan Mitsui Electric Co., Ltd. Company F term (reference) 2G032 AA01 AB00 AD08 AE14 AK00 AK11 AL00 4M106 AA02 AC02 AC04 AC07 AD23 BA14 CA01 CA16 CA70

Claims (7)

[Claims] An interface pad formed on a chip and connected to an internal circuit or a power supply of the chip by a pad lead line, and the chip provided on the chip separately from the interface pad A semiconductor integrated circuit device comprising: a test pad for determining chip chipping; and a pad lead line wired along a corner of the chip to connect the test pad to the internal circuit or a power supply. . 2. An interface pad formed on a chip and connected to an internal circuit or power supply of the chip by a pad lead line; and the chip provided on the chip separately from the interface pad. A test pad for determining chip chipping; a pad lead wire wired along a corner of the chip to connect the test pad to the internal circuit or a power supply; and a corner on the chip. A test pad for determining chip chipping of the chip, which is different from the test pad and the interface pad, and a test pad arranged at a corner on the chip; Alternatively, a semiconductor integrated circuit device including a pad lead line for connecting to a power supply. 3. An interface pad formed on the chip and connected to an internal circuit or power supply of the chip by a pad lead line; and the chip provided on the chip separately from the interface pad. A semiconductor integrated circuit device comprising: a test pad for determining chip chipping; and a pad lead-out line for connecting the test pad to the interface pad. 4. The semiconductor integrated circuit device according to claim 3, wherein test pads for determining chip chipping of the chip are arranged at corners of said chip. 5. The semiconductor integrated circuit device according to claim 3, wherein pad lead lines to which test pads for determining chip chipping of the chip are connected are wired along corners of said chip. . 6. A part of a test pad for determining chip chipping of a chip is arranged at a corner of the chip, and a pad lead wire to which the remaining test pads are connected is connected to the chip. 4. The semiconductor integrated circuit device according to claim 3, wherein wiring is performed along the corner. 7. Using a test pad for determining chip chipping of a chip, determining chip chipping of the chip,
In a test method of a semiconductor integrated circuit device for rejecting an incomplete chip, a diode characteristic of a protection circuit of an internal circuit of the chip or a short-circuit characteristic of the test pad is confirmed as an interface test of the test pad. A test method for the semiconductor integrated circuit device, wherein the chip of the chip is determined.