TW398050B - Semiconductor device testing circuit and its testing method - Google Patents

Abstract

A new semiconductor device testing is disclosed. It can accurately excludes incompleted chips during testing to avoid chip size false enlargement and testing time increasing.

Description

V. Description of the invention (1) Technical field of the invention The present invention relates to a semiconductor integrated circuit device capable of easily and surely discriminating a wafer breakage and a test method thereof. Conventional Technology Fig. 18 is a plan view showing an example of a wafer constituting a conventional semiconductor integrated circuit device. In FIG. 18, 1 is a wafer of a semiconductor integrated circuit device, 2 is an interface pad disposed on the wafer 1, and 11a is a pad pulling between the interface pad 2 and the internal circuit or power supply of the wafer 1. Out of line. Fig. 17 is a plan view showing an example of the arrangement of the wafer 1 on the wafer in a semiconductor integrated circuit device manufacturing process. In FIG. 17, 100 series wafers, 1a series are complete wafers with wafers broken and arranged on wafer 1000 '1b are incomplete wafers with wafers broken and arranged on wafer 1000. In addition, in Fig. 17, the daytime oblique line of the incomplete wafer ib and the complete wafer 1a without the oblique line are shown.

The shape of the part is not complete. The defective product that is completely in the half of the wafer is divided into broken circuits in this part. There is a manufacturing process of the guided volume circuit device as shown in Figure 17, because it is on the 100 When the rectangular wafer 1 is arranged, a part of the damaged wafer 1 b must exist. Incomplete wafer displays due to wafer breakage need to be ruled out.忒 明 When the wafer was made into this wafer, the actual wafer i

And the status of the situation. As shown in FIG. 19, one of the wafers 1 becomes an incompletely placed wafer 1. Also, the beta wafer lb is used for constituting the conventional semiconductor acquisition and interface. The interface for judging the feeling of good products, the internal circuit is also normally negative. Therefore, it is impossible to reliably exclude the crystal Bu 1 | I Μ; J

Page 4

V. Description of the invention (2) Broken and incomplete wafer 1 b. Fig. 20 is a plan view showing another example of a conventional semiconductor integrated circuit chip-mounted chip, and the same reference numerals as those in Fig. 18 are assigned to corresponding portions, and descriptions thereof are omitted. In FIG. 2 '1 0 0 0 and 1 0 0 1 are circuits such as a DRAM circuit and a logic circuit, or an analog circuit and a logic circuit, which are arranged on the chip 1 and are connected to the interface pad 2 with pad pull-out wires 11 a. . In this wafer 1, the circuit 丨 〇 00 and the circuit 丨 〇 丨 are individually tested. For example, the chip 1 is composed of a DRAM circuit 1000 and a logic circuit, and a DRA M test and logic are performed separately. In the case of testing, when testing the ρ ra μ circuit 1,000, the interface test of pad 2 related to the DRAM circuit and the circuit test of the DRAM circuit 1000 are generally performed, but the circuit is not 1001. In this case, when the wafer 1 is made into the wafer 100, the wafer actually becomes a damaged state. FIG. 21 is a plan view showing an example where the wafer becomes damaged. It is shown in FIG. 21 that the electric voltage is 1 0 0 0 a # due to chip damage, and the right side f% ^ The king piece is also in the test circuit ^ When the interface pad 2 of the circuit 000 can obtain the interface, the circuit 1 0 0 0 also operates normally. Dead Fighter, Da Da ^ ^ ^ y may be judged as a good product. Therefore, in this case, it is also impossible to reliably exclude wafers with broken wafers during the test ... but; case 5: Test circuits 1001 can be used to exclude wafers with broken wafers. Τ: Test :: In addition to the test time of the circuit at 10 ° 0, the circuit 1001 = test time is also added, and the test wastes a lot of time. And /, he has planted a semiconductor integrated circuit in 3

V. Description of the invention (3) ~ "-The document of the road device 'is, for example, Japanese Patent Application Laid-Open No. 5-21 1 222 or Japanese Patent Application Laid-Open No. 4-1 9965. In the above-mentioned Japanese Patent Application Laid-Open No. 5_21 1 222, a square-shaped check pad for detecting chip damage and damage is disclosed at the corner of the wafer, and in Japanese Patent Application Laid-Open No. 4_1 99651, it is disclosed that it is configured to surround the wafer. Defect detection wiring for measuring chip breakage. 'Another problem to be solved is that the conventional semiconductor integrated circuit devices such as the above-mentioned chip of the chip lb are not damaged, in a general test J can be =:.: 2: 2 interface' The internal circuit also operates normally And it is judged that there is no way to reliably rule out the incompleteness of the chip damage. In the circuit containing the plural circuits 1000 and 100 (circuit 1001)-Qiu Babao r piece 1 Ai Cheng tests the other side's circuit (The incomplete chip lb of the lei / knife is incomplete. The interface can also be obtained at 2. When "1000", only the padding for the interface of the circuit is 1. Therefore, the inner / circuit also operates normally and it is judged For good wafer 1 b, for the rest of this case, it is not possible to reliably exclude all the circuits on the wafer from damage. Only the incomplete wafer 1 b and the test wafer 1 are excluded. 、 The situation of 1 0 0 1 ' There is a waste and useless test device, because the semiconductor integrated circuit disclosed in the ': 5, 21 1 222 publication is near the corner of the wafer. Second, the requirements for the layout of the square inspection pads for measuring the broken wafers, etc. The corner of the film has a process or assembly No., due to the application of the cloth, I want to apply ^ Right Christine, the square inspection pad is not available at the corner, and there is a problem that the size of the wafer needs to be increased. The solution to the problem is that the semiconductor integrated circuit device of the present invention makes 4 to distinguish The wafer is used for the wafer breakage test pad, and the test pad is pulled out through the wire pad, and the test pad is connected to the inside of the wire. 5. Description of the invention (4; In addition, '在 特 开平 4- The circuit device disclosed in Japanese Laid-Open Patent No. 99651 needs to be provided with a defect detection wiring for damaging the periphery of the wafer, which leads to an increase in the size of the wafer. To increase the chip size, the defect detection wiring is buried. There are many problems such as unsuitability for bonding. The present invention aims to provide the above-mentioned semiconductor integrated circuit design in order to solve the above-mentioned problems. During the test, it is possible to confirm incomplete wafers with broken wafers and reduce wafer size. The extended test time is increased. 〃 Also, the object of the present invention is to obtain a semiconducting test method for discriminating a broken wafer of a semiconducting wafer constructed in that way. A hand on the subject of dry V volume In the semiconductor integrated circuit of the present invention, the lead-out wire and the lead-out portion of the corner wiring of the semiconductor are arranged at the corner of the wafer and are connected to the test pad of the secondary power supply, and the 4 wires and the internal crystal are ::: It is used for test pads such as crystals ;: after the test pads for crystal loss, the volume of the chip is used to detect the chip breakage to avoid the crystals and the pads are also turned into. The purpose is to eliminate large and prevent the body circuit devices A test pad connected to the chip with a corner of the chip or a power supply on the chip is provided on the chip, or a power supply connection is provided to determine the line connection. 5. Description of the invention (5) The semiconductor integrated circuit device of the present invention will be pulled by a pad The test pads connected to the pads and the interface pads are arranged at the corners of the wafer. The semiconductor integrated circuit device of the present invention allows the test pads and the interface pads to be connected by using a pad pull-out line wired along the corners of the wafer. . The semiconductor integrated circuit device of the present invention is a test in which a test pad arranged at a corner of a wafer and connected by a pad pull-out line and an interface pad is connected to a pad pull-out line wired along a corner of the wafer and connected by an interface pad. Coexist with pads. The test method of the semiconductor integrated circuit device of the present invention is to confirm the diode characteristics or short-circuit characteristics of the protection circuit of the internal circuit during the interface test for discriminating the damage of the wafer. Embodiments of the Invention Embodiments of the present invention will be described below. Embodiment 1 FIG. 1A is a plan view showing an example of a wafer constituting a semiconductor integrated circuit device according to Embodiment 1 of the present invention. In Fig. 1, 1 is a wafer constituting the semiconductor integrated circuit device. 2 is an interface pad arranged on the wafer 1, and 11a is a pad drawing line connecting the interface pad 2 and the internal circuit or power supply of the wafer 1. In addition, these systems are the same as those in the conventional-semiconductor integrated circuit device indicated by the same symbols in FIG. 18. In addition, 3a is a test pad which is disposed on the wafer 1 together with the interface pad 2 and is used to judge the damage of the wafer. 11 b is a wire that is routed along the corner of the wafer 1 and that the test pads 3 a and the pads for the internal circuit or power connection of the wafer 1 are pulled out. In addition, these test pads 3 a may be newly installed only for the purpose of judging chip damage, or they may be used as interface pads 2 for general interfaces.

Page 8 V. Description of the invention (6) '~ " --- It can also be shared. Then, 'the semiconductor integrated circuit device of this embodiment 1 has a test pad 3a on the wafer and a pad pull-out line 1 1 b which connects the test pad 3a and the internal circuit or power supply along the corner of the wafer 1 It ’s different from the conventional one. Next, a description will be given of a case where such a wafer 1 is actually inserted into the wafer J 00 as shown in FIG. 7 and a part of the wafer 1 is actually broken to become an incomplete wafer i b. FIG. 2 is a plan view showing an example of an incomplete wafer i b which has become damaged. As shown in Fig. 2, if the chip 1 is partially damaged and becomes an incomplete wafer 1b in a wafer-broken state, the pad drawing line} i b along the corner of the wafer i b is cut. Because the pad's pull-out line lb is connected to the test and internal or power supply for discriminating the chip damage, if it is cut off, by using the test pad 3 a to test § Hai chip 1 b, the debt test can be defective. change

Here, the wafer 1 in this case will be explained. One of the corners of the wafer in Example 1 is the meaning of the corner. Fig. 3 is a plan view of a part enlarged after an example of Dan I. At 3, it is a line for cutting the sundial pattern formed on the wafer 1GG, and the line is the probe in contact with the test and test pad 3a. In addition, the same symbols are assigned to the corresponding parts of FIG. 2 in other parts, and the description is omitted. Art & ib iiu π and / to connect the test pad 3a to discriminate the damage of the wafer. Wiring transfer chip: The boundary between the slice 1 and the cutting line 3 0 1 is only separated by a distance r 1 for wiring. Such a wafer 1 is shown in FIG. 17%-, 丨 ^ ^ ^ ^ ^ ^ βΓ. 100 ^ ^ ^ ^ ^ The chip is broken and cut. Therefore, the a V 'pad lead-out wire 11b is in contact with the circuit or power source of the part connected to the test pin 3a because of the crystal. The boundary of the wire is only separated by # Μ 1 and the cutting away from the wire. In the test, the crystal can be discriminated.

5. Description of the invention (7) The piece is broken. 11 b With the pad connected to the chip 'T and pad 3a, the pull-out wire 1 becomes a broken green Λ with a distance r2 of wiring, and the crystal is in-partly supported and pinched; the pull-out wire 11 b will not It is completely cut off, and when the probe 501 is in contact with the test probe 3a, the pad pull-out wire iib3 is contacted with V. Therefore, in a case where the product connected to the r2 wiring for the test 塾 3a, the boundary between the wafer 1 and the cutting line 301 is only spaced apart from the wiring, it becomes impossible to judge the broken finger of the wafer. The same is true for the trial display. The pad pull-out line Ub used to determine the damage of the wafer and the connection to the test pad 33 is shown in Fig. 4 (a). As shown in the figure, in the case of an interval of one, no, that is, when the wafer 1 is arranged on the wafer 100 shown in Fig. ，, all the incomplete wafers lb can be regarded as the defective wafers from the wafer i. The distance from the boundary line of the cutting line 301 to the drawing line iib of the pad connected to the test pad 3a is defined as an angle. © Therefore, a test pad 用以 for judging the damage of the wafer is set, and the pad 1 is pulled out by the wire 11 b. The wafer 1 along the corner wiring is in any state shown in FIG. 7. Of the wafer b. In addition, since the structure is only provided after the test 塾 3a is provided, the 塾 out line 1 1b connected to the test pad 3a is wired along the wafer 1, which is easy to implement. In addition, the first embodiment can also be applied to a wafer 1 of a conventional semiconductor integrated circuit device configured as shown in FIG. 20. That is, by setting a test 塾

苐 10-page stand-by instructions (8) and test 塾 3a connected 塾 pull out ㈣ = circuit mo test at the same time use the chip! Wiring 'surface test, can definitely exclude incomplete pads The test of boundary line 1 0 0 0 can be excluded. If it is at the time of the electric axis, it can also suppress the increase: it is not necessary to test the pad 3a. In order to judge the damage of the wafer, the test pad was pulled out, and then the pad connected to the test pad was pulled out of the heart:] type j can be adapted to the process or group at the corner of the wafer! Due to the size expansion. In the case of the corner of the sheet 1, it is possible to prevent the wafer. In addition, the test pad 3a is only for the purpose of discriminating. The pad that is shared with the interface pad may also be used. Rule 2 The above households have shown that if this embodiment 1 is used, the effect can be realized, and the incomplete crystals with chip breakage can be reliably ruled out. Circuit device. 3 plus + conducting volume through Embodiment 2. In the above embodiment, the wafer is explained. Set up the test cell 3 & Germany, spleen > female stem, head J ^ ten leisurely q < ^ said that the connection of the film broken connection: the internal circuit or power supply of the post-designated chip Cases where each corner of 1 is wired separately: Several of 1: also 1 corners can be arranged for testing to determine wafer damage 晶片 3a 5. Description of the invention (9) FIG. 5 shows the second embodiment of the present invention as constructed A plan view of an example of a wafer of a semiconductor integrated circuit device. In Fig. 5, 3b is a test pad arranged on the wafer 1 to judge the damage of the wafer, and 11c is the test pad 3b and the internal circuit. Or the power supply connected pads. The test pad 3b used to determine the chip damage is also the same as the test pad 3a. It is also a pad prepared for the purpose of determining the chip damage. Interface common pads are also available.

In the second embodiment, a test pad 3b for discriminating a wafer is disposed at two corners on a diagonal of one of the wafers 1, and the pad pull-out line 11c is not wired along the corner of the wafer 1. In addition, 2 Q corners on the diagonal line of the other side of the wafer 1 are arranged along the corners to pull out the wires 1 1 b connected to the test pad 3 a. In addition, the other parts are given the same reference numerals as the corresponding parts in FIG. 1, and their descriptions are omitted. Next, a description will be given of a case where a part of the wafer 1 is actually broken when the wafer 1 is fabricated in the wafer 100 as shown in FIG. 17. Fig. 6 is a plan view showing an example of an incomplete wafer 1b which has become damaged. As shown in Fig. 6, when a part of the wafer 1 is damaged and becomes an incomplete wafer 1b, the test pad 3b provided at the corner of the wafer 1b for discriminating the wafer becomes non-existent or incomplete. Therefore, it is impossible to use the test 4 set at the corner of the wafer 1 b to perform a test with the pad 3 b. By using the test pad 3 b to test the wafer 1, a defect can be detected. Here, the definition of the corner of the wafer 1 in this case will be described. Fig. 7 is a partial plan view showing an enlarged corner portion of a wafer 1 of the semiconductor integrated circuit device of the second embodiment. In addition, corresponding parts corresponding to FIG. 3 and FIG. 6 are assigned to each part.

Page 12 V. Explanation of the invention (10) The same symbols will be omitted. In FIG. 7 (a), the test line i used to discriminate wafer damage and the boundary line between the cutting line 3i and the cutting line 3i are arranged at a distance of "5". This means that when the wafer m is actually in a broken state, "7U) =, during the test, the probe 500 is brought into contact with the test pad 也, because the wafer is broken" § 玄If the test pad 3b does not exist, the probe 500 cannot be brought into contact with it. Therefore, the test pad at the corner of the wafer i is placed at a distance of r5 from the boundary of the secant line 301, which can be judged ^ Broken knife. However, as shown in FIG. 7 (b), 1 is used to discriminate the damaged wafer 3b, and the boundary between the wafer 1 and the cutting line 30 is separated by a distance r6 to become damaged. 1 Trial 塾 3b also exists. Therefore, when the y-crystal contacts the test pad 3b, it can be in contact with the internal circuit or the power supply. Therefore, the oblique 500 will test the dislocation between the crystalline M and the cut material 3Q1, and it will become impossible to determine the chip damage. No. 8. The situation is the same. In the case where the wafer made by the wafer 100 is changed to a wafer break state, the test pad 3b located at the corner of the wafer ib and used to judge the damage of the wafer is shown in Figure 8 ( As shown in a), if the crystal is arranged only at a distance r7 from the boundary line of the cutting line 30 1, it can be judged that The wafer is broken, but as shown in Fig. 8 (b), there is no damage to the wafer when it is arranged at an interval of r8. ^% That is, when the wafer 1 is arranged on the wafer j 00 shown in Fig. 17, all the wafers are completely completed. 1 b is regarded as the defect exclusion from the boundary between the wafer worker and the cutting line 301 to the test pad set at the corner of the wafer jb to determine the damage of the wafer.

苐 Page 13

V. Explanation of the invention (11) The distance is defined as an angle. In addition, using this embodiment 2 is also the same as in embodiment 1. The effect gas can be used to reliably exclude the incomplete J with chip damage during the test. 1 b. A semiconductor integrated circuit device that can prevent wafer size expansion and test time increase, and can also be arranged with a test pad 3b at the corner of the wafer i, or it can be electrically drawn from the pad pullout line of the test pad 3a 丨 ib wiring , The degree of freedom of design is provided, Example 3

Fig. 9 is a plan view showing an example of a wafer constituting a semiconductor integrated circuit arrangement according to a third embodiment of the present invention, and the same reference numerals are assigned to corresponding portions ^ and descriptions thereof are omitted. In FIG. 9 ′ 3c are arranged at the corner of the wafer 1 for two rows = two broken test pads, and 1 d is a line where the test pads 3c and the interface are connected by 塾 1. Therefore, the test pin 3c disposed at the corner of the chip 1 is connected to the internal circuit or power supply through the pad pull-out line 11d, the interface pad 2 and the pad pull-out line 11a. °

Next, a description will be given of a case where a part of the wafer 1 is generally broken when the wafer 1 is manufactured into the wafer 100 as shown in FIG. 17. Fig. 10 is a plan view showing an example of an incomplete wafer 1b which has broken wafers. As shown in FIG. J ′, when a part of the wafer 1 is broken and becomes the incomplete wafer 1 b, the test pad 3c provided at the corner of the wafer 1 is absent and becomes incomplete. Therefore, "Because the test pad 3c provided at the corner of the wafer 1 cannot be used for testing" By using these test pads 3c to test the wafer 1b, the debt measurement can be bad. Then, a test 塾 3c for discriminating the damage of the wafer is provided at the corner of the wafer 1, and the pad drawing line lld connected to the wafer is connected to the interface pad 2 shown in FIG.

Fifth, the description of the invention (12) The slice 1 'is located in any state shown in Fig. 17 and can be eliminated during testing. In addition, since the semiconductor integrated circuit device of this embodiment 3 is only provided with a test pad 3c for discriminating the damage of the wafer at the corner of the wafer 1, and the pad drawing line 11d is used to connect the test pad 3c and the interface pad 2 ,easy to accomplish. In the case where 'f' is applied to wafer 1 of a conventional semiconductor integrated circuit device configured as shown in FIG. 20, a test 塾 3c for discriminating = chip breakage is provided at the corner of wafer 1 and the pad is pulled. The output line l ld is used in conjunction with the interface, & 2 connection, connection, 'in and circuit 1 00 test at the same time using these test pads 3c, Λ ground to exclude incomplete wafer lb, and if in the circuit 1 The test of 0 0 0 can be excluded; ^ — eight ^ ^ 1 η π 1 B * Μ ”The extraordinary king's chip 1 b, it is not necessary to test the circuit 1.0 〇 1 time, Α · 5τ々, also suppressed the test The time is increased. In addition, because it is arranged in gg ^^, the test pad 3C at the corner of RR A / is used to determine that the size has become smaller. Therefore, it is necessary to bond the wafer to the test pad. The corners of the 3C arrangement pads of these test pads are marked with a process or assembly, and also enlarged. At the corner of wafer 1, the size of the wafer can be prevented from being placed on the wafer; 1 ^ is connected to the pad 2 of the interface, and the boundary The test pad 3c uses the pad to pull out the wire 1 1 d. The wiring of the internal circuit cannot be used everywhere. The configuration of 塾 ^ has no effect. This is advantageous when the pad 2 is used for the mobile interface, and it is not possible when the cable is free or because of wiring regulations. In addition, the size of the wafer is increased by the arrangement and placement. Multiple tests. That is, it is used for the test of the angle: The pad 3c 'makes it possible to push a wafer composed of ~ 100 0 0 and 1001 / flying the internal lightning failure shown in Figure 20

It is necessary to make the contact pin in multiple tests: 5. Description of the invention (13) The pad 2 for the touch interface is damaged multiple times, and the pad 2 for the interface is damaged, which is effective to prevent the pad 2 when it affects the joint. As shown above, if this embodiment 3 is used, the effect is that incomplete wafers with wafer breakage can be reliably excluded during the test, and the wafer size can be prevented from increasing and the test time can be increased. Tested semiconductor integrated circuit device. In addition, in the above description, the test pad 3 c for judging the damage of the wafer is provided at the corner of the wafer 1, but as shown in FIG. 11, in the case where the interface pad 2 is disposed at the corner, the wire 11 is pulled out by the pad. d It is also possible to connect the test pad 3c disposed outside the corner with the interface pad 2 with the same effect. & Embodiment 4 FIG. 12 is a plan view showing an example of a wafer constituting a semiconductor integrated circuit device according to Embodiment 4 of the present invention, and the same symbols are assigned to corresponding portions, and descriptions thereof are omitted. In Fig. 12, 3d is a test pad for discriminating wafer damage, and 11e is a wire that is drawn along the corner of wafer 1 and is a pad that connects these test pads 3 and interface pads 2. Therefore, the test pad 3d is connected to the internal circuit or power supply through the pad pull-out wire 1 1e, the interface pad 2 and the pad pull-out wire 1 1a. Next, a description will be given of a case where a part of the wafer 1 is actually broken when the wafer 1 is fabricated into the wafer 100 as shown in FIG. 17. Fig. 13 is a plan view showing an example of an incomplete wafer 1b which has broken wafers. As shown in FIG. 13, in a case where a part of the wafer 1 is damaged and becomes an incomplete wafer 1 b, the pad pull-out line 1 1 e along the corner of the wafer 1 is cut. Because the pad pull-out line 11 e is wired along the corner of the wafer 1, the connection is used to identify the crystal.

Page 16 Description of the invention (14) Test pad with broken sheet 3d ^ κ. Λ and the pad 2 for the interface. By using the test pad 3d to test the film 1 KK Zhen Gang should be cut off, which can detect and measure the defect. Therefore, after the test 塾 3d is set, the corner along the wafer (connected to the shown wafer 1 is located as shown in Figure 乂; 乂 -like sadness can be reliably excluded during the martial arts test. Since the semiconductor integrated circuit device is only designed, it is easy to implement after measuring it by using a pull-out line ue that is wired along the corner of the wafer i to connect it with the pad 2 for the interface. In the case of the conventional wafer 1 of the semiconductor integrated circuit device, it is shown that the test pad 3d for discriminating the damage of the wafer is also provided, and then the pad pull-out line is used to connect it to the interface with 塾 2. The test of circuit 1 000 at the same time uses these test pads 3d for testing, which can exclude the incomplete crystal Mb, and if the test at the circuit = excludes incomplete wafer ib, it is not necessary to test circuit 1 The time of 〇〇1 can suppress the increase of the test time. In addition, the test output system arranged on the wafer i is used to determine the detection of the wafer. As in the case of Example 3, no bonding is required during assembly, so that The size of the test pad 3d becomes smaller. Connect the test pads 3 (1 and the interface pads 2 (1) to the test pads, corner wiring pads, and pull-out wires. 1 It is not necessary to set these test pads 3 (1 on the wafer) process or nr symbol, or Equality of wiring ^^: It is advantageous to arrange the pad 3d at the corner of the wafer 1 to suppress the expansion of the wafer size, because the test pad 3d used to discriminate the damage of the wafer uses the pad to pull out the wire

Page 17 V. Description of the invention G5) ______ The connection between lle and the pad 2 for the interface has no effect on the configuration of the interface 2 where the wiring from the internal circuit cannot go everywhere. This is advantageous when the pad 2 for the interface cannot be moved, and it can be in time or due to wiring regulations, etc. In addition, by setting up such tests; test. That is, in the case of a wafer i consisting of FIG. 24 that can be tested multiple times for 1001, which requires multiple tests, the internal circuit 1000 and pad 2 must be used for multiple tests, thus damaging the interface with a stylus. When it touches the interface, it is effective to prevent it. With 塾 2, this has an effect on the bonding as shown above. If the test is carried out using this method, it can be reliably excluded that the wafer is broken: 八 The result is that it can prevent the wafer size from increasing and increase the test time. Trial semiconductor integrated circuit device. W Chengzhang repeatedly tested Example 5 Damaged ΐ ΐ ΐ V㈣ The test pads 3d and the interface pads 2 are installed on the chip 1 to identify the chips, and each corner of the chip 1 is wired. Case, but test: Lit is implemented in the same way as in Example 3. It is arranged at the corner of wafer 1 to determine the number of wafers for testing. After that, it is connected to the interface pad 2 by using a pad pull-out cord lid also may. The electric circuit diagram of the semiconductor integrated circuit according to the fifth embodiment of the present invention in the form of a circuit "The semiconductor integrated circuit of the fifth embodiment ί ί ϊ The semiconductor integrated circuit banks of the third and fourth embodiments: t 20% . In addition, the stele corresponds to Fig. 9 or Fig. In each part. The same symbols are used, and the description is omitted.

Page 18 -i V. Description of the invention (16) As shown in Figure 14, on the wafer!塾 2 for configuration interface, 3c and 3d for broken test pads. The t2 interface pad 2 is connected to an internal circuit or a power source by using a pad pull; In addition, the test pad li3 pad lead that has been placed at the corner is connected to the pad 2 for the interface, and the other test pad "uses the pad pull line wired along the corner of the wafer 1 丨 e and the interface It is connected with the pad 2. In addition, this embodiment 5 is also the same as the above-mentioned embodiments 3 and 4. 'The effect is that the incomplete wafer 1 b' with wafer breakage can be reliably excluded during the current test and can be prevented. The semiconductor integrated circuit device which can increase the size of the wafer and increase the test time and can withstand multiple tests, and can also arrange the test 塾 3c at the corner of the wafer 1, and can also pull out the pad from the test pad 3d 11 e wiring can achieve effects such as improving the degree of freedom in design. Example 6 In each of the above examples, a semiconductor integrated circuit device that can reliably and easily discriminate a broken wafer is shown, followed by a description to identify the type of semiconductor integrated circuit. Test method for wafer breakage of circuit devices. The test method for a semiconductor integrated circuit device according to the sixth embodiment of the present invention is to determine the semiconductor integrated circuit device with the structure shown in the first to fifth embodiments Figures 15 and 16 of the interfacial test of wafer breakage test pads 3a to 3d are explanatory diagrams showing examples of the test methods of these test pads 3a to 3d. &Quot; Fig. 15 (a) shows The interface test method using the test pads 3a to 3d using the characteristics of the protection circuit of the input circuit 'Figure 15 (b) shows the voltage v-current I characteristics of the protection circuit. Figure 15 (a)' 1 is tested Wafers, 2 series interface pads. 3 series comprehensive meters are test pads used to judge wafer damage

Page 19 Description of the invention (17) — 3 = ~ 3d ° 201 series p-channel transistors, these two transistors form a turn-by-turn lightning system, and they are used by the electric sun and the sun to make use of the protection, Leiba circuit. 203 uses the input circuit of the polar body, and 204 is the GND electrode connected to the interface pad 2. The P channel is called a chip = a test pad 3 that is set to judge the chip breakage. This is the same as the input circuit consisting of the C passive channel transistor 202 and the test pad 3. X, protection circuit 20 3-square input (anode) is connected. Geunjie 仏 矣, the other output (cathode) is connected to the test pad 3 times. The source of the transistor 2 02 in the circuit channel is connected to the pad 2 of the interface. When measuring the picture, connect the interface with 塾 2 and ⑽ electrode 204 to confirm the voltage V—current I characteristic of the protection circuit 203 shown in FIG. The circuit 2 indicates the interface recognition of the input circuit, but the output protection circuit 戍 output is available. In addition, in the case of the output circuit, measure the voltage V-current 1 characteristic of the main crystal and confirm the interface. The difference between the connection = the non-confirmation of the spirit and the pad 3 method used to determine the damage of the wafer. The test surface of the pad 3 for the short-circuit test between the pad 2 is divided into ^ and Figure 5 ^ its voltage V — Current 1 characteristic. 16 (a) and the corresponding parts in FIG. 15 (a) have the same reference numerals, and descriptions thereof are omitted. After the interface of the chip 1 is connected with the 塾 2 and the GND electrode 204, a voltage v is applied to the radio-electrical plant characteristic 2. The electric motor i characteristics' confirmation screen at that time shown in Fig. 16 (b) is measured. Disadvantages: Secondly, if this embodiment 6 is used in the interface test of the method for judging chip breakage, by using the method of confirming the diode characteristics to confirm the new circuit characteristics, the simple test can be used to exclude the use of This emission line will be provided with a chip and a suppressor circuit, and the circuit or pad in the structural part coexist, and the chip size has a special effect. Because the structure is connected with the pad, the durability of the wafer is also increased. Because the structure is placed on the wafer, it can prevent the durability of the test. Because it is used in the structure and the interface, it can prevent the durability of the test. It is clear that the structural use of the test pad on the wafer and the internal test can reliably exclude the effects of the increase in the size of the crystal wafer and the prevention of test placement. It is ordered to use a test pad with a power supply connected along the corner of the chip. The test device and configuration can be used to reliably exclude non-enlargement and increase in test time during the test, as well as use of the pad, which will be used for measuring size expansion and higher effects. Corners, the expansion of the size of the chip is also improved, and the dimension of the wafer is also improved. V. The description of the invention (18) Incomplete wafer lb. The effect of the invention is as shown above. If the semiconductor circuit is connected to an external circuit or a power source, and the chip time of the chip is broken, the crystal time is increased. If the invention is used, the wire can be pulled out and the chip used for testing inside the corner of the chip can prevent the freedom of design. If the present invention is used, the test pads and the wafers with incomplete interfaces can be improved, and the resistance to multiple tests can be prevented. If the present invention is used, the connected test pads are configured to exclude incomplete wafers, and If the present invention is used for multiple tests, the pull-out line will also exclude the incomplete wafer for test 1 and the pull-out line will be set at the wafer test to reliably exclude the increase in test time. Adding and using 〇 pads to pull out the line and interface can be used to test the test results and increase the test time. And for multiple measurements

The wiring of the corners of the Japanese-Japanese film has the effect that it can be surely expanded when the test is started, and the time can be increased.

— Page 21, Description of the Invention (19)-If the present invention is used, the test pads connected to the corners of the wafer and the wiring pads and the interface pads are connected to the corners of the wafer in terms of structure. The coexistence of pads can effectively eliminate incomplete wafers during testing, prevent wafer size expansion and increase test time, and improve the design reliability. °° By using the present invention, the method of confirming the characteristics of the diode or the method of confirming the short-circuit characteristics is used in the test of the interface of the test pad on the structure, so that the incomplete wafer can be reliably excluded by a simple test. Simple illustration of the method of testing the semiconductor integrated circuit device that can be confirmed in a short time > Figure 1 shows an embodiment of the present invention! A plan view of an example of a semiconductor integrated circuit device wafer. Fig. 2 is a plan view showing an example of an incomplete wafer in the first embodiment.

Fig. 3 is a partial plan view showing an example of a corner portion of a wafer in an embodiment. P FIG. 4 is a partial plan view showing an enlarged example of a corner portion of a wafer in Example 丨. Fig. 5 is a plan view showing an example of a semiconductor integrated circuit device wafer according to a second embodiment of the present invention. Fig. 6 is a plan view showing an example of an incomplete wafer in the second embodiment. Fig. 7 is a partial plan view showing an example of a corner portion of a wafer of Example 2 in an enlarged manner. ° V. Description of the invention (20) Fig. 8 is a plan view of a part of the corner portion of the wafer of Example 2 after being enlarged. Fig. 9 is a plan view showing an example of a wafer of a semiconductor integrated circuit device according to a third embodiment of the present invention. Fig. 10 is a plan view showing an example of an incomplete wafer in the third embodiment. Fig. 11 is a plan view showing another example of the wafer of the semiconductor integrated circuit device of the third embodiment. Fig. 12 is a plan view showing an example of a wafer of a semiconductor integrated circuit device according to a fourth embodiment of the present invention. Fig. 13 is a plan view showing an example of an incomplete wafer in the fourth embodiment. Fig. 14 is a plan view showing an example of a wafer of a semiconductor integrated circuit device according to a fifth embodiment of the present invention. Fig. 15 is an explanatory diagram showing an example of a method for testing a semiconductor integrated circuit device according to a sixth embodiment of the present invention. Fig. 16 is an explanatory diagram showing another example of a method for testing a semiconductor integrated circuit device according to a sixth embodiment of the present invention. FIG. 17 is a plan view showing an example of a wafer-to-wafer arrangement in the process of the present invention and the conventional semiconductor integrated circuit device manufacturing process. FIG. 18 is a plan view showing an example of a conventional wafer of a semiconductor integrated circuit device. Fig. 19 is a plan view showing an example of an incomplete wafer of the conventional semiconductor integrated circuit device shown in Fig. 18; Page 23 V. Description of the invention (21) FIG. 20 is a plan view showing another example of a conventional wafer of a semiconductor integrated circuit device. FIG. 21 is a plan view showing an example of an incomplete wafer of the conventional semiconductor integrated circuit device shown in FIG. 20. FIG. Explanation of symbols 1 chip, 2 interface pads, 3, 3 a to 3 d test pads, 1 1 a to 1 1 e pad pull-out wires, 2 0 3 protection circuit

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Claims (1)

6. Patent claim 1. A semiconductor integrated circuit device, comprising: an interface pad, formed on a wafer and drawn with a pad and connected to the internal circuit or power supply of the wafer; more than one first test pad, And the interface pad is additionally provided on the wafer and used to discriminate the wafer breakage of the wafer, and the first pad pull-out line is wired along the corner of the wafer and used to connect the first test pad and the interior Circuit or power connection. 2. If the semiconductor integrated circuit device of item 1 of the patent application scope includes: 1 or more second test pads, arranged at the sum of the corners of the wafer, the # 1 test pad and the interface pad are separately provided And used to judge the chip of the chip is damaged; and a second pad pull-out line for connecting the corner disposed on the chip to the internal circuit or power supply. 3. A semiconductor integrated circuit device comprising: an interface pad, which is formed on a wafer and is connected to an internal circuit or a power supply of the wafer with a pad pull-out wire; a plurality of test pads, and the interface pad are additionally provided on the The wafer is used to judge the wafer damage of the wafer, and the pad is pulled out to connect the test pads to the interface pads. 4. In the case of a semiconductor integrated circuit device according to item 3 of the patent application, at least a part of a test pad for discriminating a wafer breakage of a wafer is placed at a corner of the wafer. 5. If the semiconductor integrated circuit device of the third scope of the application for a patent, Page 25 6. In the scope of patent application, the pad pull-out line connected to the test pad used to judge the wafer damage of the wafer is wired along the corner of the wafer. 6. If the semiconductor integrated circuit device of the third item of the patent application is applied, a part of the test pad used to judge the wafer damage of the wafer is arranged at the corner of the wafer, and the remaining test pads are connected The pad pull-out wires are routed along the corners of the wafer. 7. —A method for testing semiconductor integrated circuit devices, which uses a test method for determining the wafer breakage of the wafer, and discards the incomplete wafer after the wafer is discriminated. It is characterized in that: In the interface test, the wrong person confirms the diode characteristics of the protection circuit of the internal circuit of the chip or the short-circuit characteristics of the test pads to determine that the chip of the chip is damaged. Page 26