200931429 wf.doc/p 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種故障位置查找方法，且特別是有 關於一種查找積體電路内部之故障導線位置的方法。 【先前技術】 動態隨機存取記憶體（Dynamic Rand〇m Aceess Memory，簡稱DRAM)雖出現已久，但在市場上卻一直 ❹ 保有其不可被替代性。直至目前，在衫的電腦、顯示卡 或相關產品中，仍然免不了使用DRAM做為資料儲存裝 置。DRAM的内部構造一般如圖1所示，請參照圖丨，其 繪示出DRAM的局部結構。在圖1中繪示有位元線(bit line ’如標示102所示）、字元線(wordiine，如標示1〇4所 示）、基體(substrate ’如標示1〇6所示）、位元線與基體之 間的導電插塞(如標示108所示）、導線(如標示11〇所示）、 導線與字元線之間的導電插塞(如標示112所示）、以及絕 緣層（如標示114所示）。其中，字元線被絕緣層包覆而與 〇 圖示中的其他結構隔離’僅透過導電插塞(如標示H2所示） 連接導線。 在DRAM的檢測技術中，·電性故障分析(dectrical failure analysis)及物性故障分析(physical failure analysis) 是查找DRAM產品良率不佳之主因的常用手段。圖2即繪 示電性故障分析的一種測試結果。請參照圖2，標示210 即顯示出發生故障的位元線對’且在標示212所指的地方 也出現了反轉點。所謂的反轉點’就是在測試結果中所出 5 200931429 vf.doc/p 現的反轉位元故障標鼓、(flip_bit failing signature)，以標示 犯所指之處來說明的話，就是該處原本該呈現出標示2i4 所指之處的圖樣，然卻呈現出標示216所指之處的圖樣。 此反轉點指出該處的記憶單元(mem〇ry cell)發生了問題， 例如發生位兀線與基體之間的導電插塞以及字元線二者相 互短路的問題，如圖3所示。 ^圖3為圖1所示之局部結構發生短路的示意圖，其中 〇 軚不U6所指之星號即表示位元線與基體之間的導電插塞 以及子元線二者發生短路。因此，在電性故障分析之後， 可以^利用物性故障分析的方絲進行破壞性分析，將發 生故障的樣品逐層研磨，以找到造成故障的原因，例如查 看位兀線與基體之間的導電插塞以及字元線二者是否真的 發生短路。然而，若電性故障分析的測試結果只有標示出 發生故障的位元線對，而沒有呈現出任何的反轉點，如圖 斤示其緣示電性故障分析的另一種測試結果。那麼， Q 更了推測有可月b疋一條位元線之間發生短路，或者是二條 位元線終端的輸入/輸出（ini)ut/〇utput)接頭處發生了短路。 然後，再利用物性故障分析的方式來確認上述推測是否正 確〇 一儘官如此，若物性故障分析的結果已確認並非是二條 元線之間發生短路，也並非是二條位元線終端的輸入/ 出接頭處發生短路，然而電性故障分析的測試結果也沒 f呈現出任何的反轉點，在這樣的情況下，由於物性故障 刀析乃是搭配採用電子顯微鏡來微觀地探討故障主因，而 200931429 w£doc/p Γ障分析❹m結果卻餘得知是哪個記憶單元發 生了問碭，以致於讓測試者根本無從查起。 【發明内容】 =:月的目的之一就是提供一種故障位置查找方 構字元_位置，讓賴者可將電性故 :刀析所取㈣故障位元線位置與故障字元線位置相互交 ;二=故障記憶單元的位置’以利探討故障記憶 ，發明的另一目的就是提供一種故障位置查找方 、八可查找出積體電路内部之故障導線位置。 基於上述及其他目的，本發明提出一種故障位置查找 法’適於查找-積體電路内部之複數條第—導線中，發 ί故障之每—第—導線的位置，其中上述之第-導線係沿 第:預設方向排列。此方法包括下列步驟，首先，使上述 之苐-導線皆呈現浮接狀態。接著，利用粒子束掃描上述BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fault location finding method, and more particularly to a method of finding a faulty conductor position inside an integrated circuit. [Prior Art] Dynamic Random Access Memory (DRAM) has been around for a long time, but it has been irreplaceable in the market. Until now, in the computer, display card or related products of the shirt, DRAM is still inevitably used as a data storage device. The internal structure of the DRAM is generally as shown in Fig. 1. Referring to the figure, the partial structure of the DRAM is shown. In FIG. 1, a bit line (bit line ' as indicated by numeral 102), a word line (wordiine, as indicated by reference numeral 1), a substrate (substrate ' as indicated by numeral 1〇6), and a bit are shown. a conductive plug between the wire and the substrate (as indicated by numeral 108), a wire (as indicated by reference numeral 11), a conductive plug between the wire and the word line (as indicated by numeral 112), and an insulating layer (As indicated at 114). Wherein, the word lines are covered by an insulating layer to be isolated from other structures in the figure, and the wires are connected only through conductive plugs (as indicated by the designation H2). Among the DRAM detection technologies, dectrical failure analysis and physical failure analysis are common methods for finding the main cause of poor yield of DRAM products. Figure 2 shows a test result of electrical fault analysis. Referring to Figure 2, the indication 210 shows the bit line pair 'where the fault occurred' and the reversal point also appears where the indication 212 points. The so-called reversal point is the result of the 2009-11429 vf.doc/p reversal bit faulting drum (flip_bit failing signature), which is used to indicate what is meant by the crime. It should have been presented with a design indicating the location indicated by 2i4, but showing the pattern indicated by the indication 216. This reversal point indicates that there is a problem with the memory cell (mem〇ry cell), such as the occurrence of a short circuit between the conductive plug between the bit line and the substrate and the word line, as shown in Fig. 3. FIG. 3 is a schematic diagram of a short circuit of the local structure shown in FIG. 1, wherein the asterisk indicated by 〇 軚 not U6 indicates that the conductive plug between the bit line and the substrate and the sub-line are short-circuited. Therefore, after the electrical failure analysis, the destructive analysis can be performed by using the square wire of the physical failure analysis, and the failed sample is ground layer by layer to find the cause of the failure, for example, to observe the conduction between the bit line and the substrate. Whether the plug and the word line are really short-circuited. However, if the test result of the electrical fault analysis only indicates the bit line pair that has failed, and does not exhibit any reversal point, the figure shows another test result of the electrical fault analysis. Then, Q is more speculated that there is a short circuit between one bit line, or a short circuit at the input/output (ini) ut/〇utput) of the two bit line terminals. Then, using the physical failure analysis method to confirm whether the above speculation is correct or not, if the result of the physical failure analysis has confirmed that it is not a short circuit between the two elements, it is not the input of the two bit line terminals / A short circuit occurs at the joint, but the test result of the electrical fault analysis does not show any reversal point. In this case, the physical fault is analyzed by using an electron microscope to microscopically discuss the main cause of the fault. 200931429 w£doc/p The analysis of the ❹m results, but I know which memory unit has been asked, so that the tester can not find it. [Summary of the Invention] =: One of the purposes of the month is to provide a fault location to find the square character_location, so that the relying person can take the electrical property: the knife is taken (four) the fault bit line position and the fault word line position are mutually Intersection; 2 = location of the fault memory unit to facilitate the discussion of fault memory, another object of the invention is to provide a fault location seeker, eight to find the location of the faulty conductor inside the integrated circuit. Based on the above and other objects, the present invention provides a fault location finding method that is adapted to find the position of each of the plurality of conductors in the plurality of first conductors within the integrated circuit, wherein the first conductor is Along the: preset direction. The method includes the following steps. First, the above-described 苐-wires are all in a floating state. Then, using the particle beam to scan the above
之第-導線’並依據激發出來的表面電子訊號來查找發生 故障之每一第一導線的位置。 在上述故障位置查找方法的—實施例中，該積體電路 内部還包括有複數個第-導電插塞及複數條第三導線，且 該些第-導線及該些第—導輪塞係包覆在—絕緣層中， 每-第-導線皆透過該些第—導電插塞的其中之一而電性 連接至該些第三導_其巾之—。在此綱述之故障位置 ，找方法巾’係透過躺該些第三導線來使該些第一導線 王現浮接狀悲，並利用粒子束來掃描被截斷的該些第三導 7 200931429 —--wf.doc/p 第—導電插塞電性連接的部分，以依據激發出 來的表面電子訊號來查找發生故障之每一第一導線的位置。 =明因使待測導線呈現浮接狀態，並將待測導 =一導線)附近的導體_至共同電位，然後再利 掃描待測導線，或是掃描被截斷的該些第三導線虚 塞=連接的部分，並依據激發出來的表面電子訊 ❹ ίtitb(passive voltage —, :，、、=、，，σ果查找發生短路故障之待，線的位置。假若待 ^導線為記紐内部之字元線，那麼測試者便可將電性故 位元線位置與故障字元線位置相互交 單^故憶單元的位置，以利探討故障記憶 ^發明的再―目的是提供另—種故障 ΐ是過程中，先行檢驗積體電路二 以判別及故障導線之可能位置，據 其於積體電路的良率’並進行後續分析。 方法，本發明提出一種故障位置查找 之複數純的過程中’查找積體電路内部 個第-導有任一可能與積體電路内部之複數 ί測於切割道上製作測試鍵，所 v電插塞，且每一仿第-導線之其中-端 8 200931429 ^f.doc/p Α電性連ϊ上述之仿第二導電插塞其中之…並呈現浮接狀 i激利用粒子束掃描上述之仿第二導電插塞，並依 來的表面電子訊縣查歸生短路故障之每一仿 置，鱗_騎之第—導財是时任-可能 Ο 雷致=卜1在本發明所提出的另—方法中，更在製作積體 的同時’於切割道上另外製作特殊的測試鍵 鍵與上述之積體電路二者的結構幾乎相同，然不同之斤 於該測試财之每—仿_導線(即^ 端皆會電性連接至該替第二㈣插塞H)的其中一 =子束掃描該些仿第二導電插塞，並依據激;出= 果^發生短路故障之仿待測導線的位置，以推測相^ 之待測導線中是否有任-可能發生短 : 生故障之待測導線的位置。如此一來，二;x及可起發 Ο ，電路的過程中，先行檢驗積體電路内部是 故障導線’以及故障導線之可能 <立置 :〔、有 積體電路的良率，並進行後續分析。 '斤製造之 為讓本發明之上述和其他目的、特徵和優 易懂，下文特舉較佳實施例，並配合所.、月b更月顯 明如下。 。所附圖式’作詳細說 【實施方式】 9 ❹The first-wire' is based on the surface electronic signal that is excited to find the position of each of the first wires that have failed. In the embodiment of the fault location finding method, the integrated circuit further includes a plurality of first conductive plugs and a plurality of third conductive wires, and the first conductive wires and the first conductive guide plug packages In the insulating layer, each of the -first wires is electrically connected to the third conductive vias through one of the first conductive plugs. In the fault location of this outline, the method towel is used to lie the third wires to make the first wire kings float, and use the particle beam to scan the third guides that are truncated 7 200931429 --- -wf.doc/p - The portion of the conductive plug that is electrically connected to find the position of each of the first wires that have failed according to the surface electronic signal that is excited. = The cause of the conductor to be tested is in a floating state, and the conductor to be tested = a conductor) to the common potential, and then scan the wire to be tested, or scan the third wire that is cut off = connected part, and according to the surface signal 激发 t ί ί ί ί pass pass pass pass pass pass pass pass pass pass pass pass pass pass pass 查找 查找 查找 查找 查找 查找 查找 查找 查找 查找 查找 查找 查找 查找 查找 查找 查找 查找 查找 查找 查找 查找 查找 查找 查找 查找 查找 查找 查找 查找Word line, then the tester can cross the position of the electrical position line and the position of the fault word line to each other. Therefore, the position of the unit is recalled to facilitate the discussion of the fault memory. The purpose of the invention is to provide another fault. In the process, the integrated circuit 2 is first checked to determine the possible position of the faulty conductor, according to the yield of the integrated circuit' and subsequent analysis. The method proposes a complex pure process in the fault location search. 'Find the internal circuit of the integrated circuit--there is any possibility to compare with the internal part of the integrated circuit. Measure the test button on the cutting path, the v-plug, and the end-end of each analog-wire. 200931429 ^ F.doc/p Α The above-mentioned imitation second conductive plug is... and exhibits a floating shape, and the particle beam is scanned by the particle beam to scan the above-mentioned second conductive plug, and the surface electronic signal is returned to each other. Imitation, scales _ riding the first - guide money is the time - possible Ο Lei Zhi = Bu 1 in the other method proposed by the present invention, while making the integrated body while making a special test key on the scribe line The structure of the key and the above-mentioned integrated circuit are almost the same, but different ones of the test money - one of the analog wires (that is, the terminals are electrically connected to the second (four) plug H) = the beamlet scans the second-like conductive plugs, and according to the excitation; the result of the short-circuit fault, the position of the analog conductor to be tested, to estimate whether there is any fault in the conductor to be tested - may occur short: The position of the wire to be tested for the fault. In this way, in the process of the circuit, the circuit is first checked for the faulty conductor inside the faulty circuit and the possibility of the faulty conductor. The yield of the body circuit, and the subsequent analysis. And other objects, features and advantages of comprehensible, preferred embodiments cited, and with the., Dated May b significantly more clear below. The drawings' made in detail [Embodiment 9 ❹
Q 200931429 *vf.doc/p 仍然各實施例 的例舉方式並杨嫩；^細本發_ ，然這樣 構發二如圖4Γ:，其繪示DRAM之局部結 元線與基體====， DRAM樣品係發生圖3所示的短路故障，然2 故障刀析中卻都沒有辦法找出標示u 分析的結果已確認並非是二二： 二條位元線終端的輸入/輸出接頭處 發紐路，，、、、'而電性故障分析的測試結果也 在這樣的情況下，便可採用本發明之 找出^ 116所指之故障點，進—步取得對應之故 障記憶單元的位置，㈣探討故障記鮮元的故障^因。 經由電性故障分析，其職結果必定會標㈣發生短路 故障的位元線。接下來够關5來進行解釋。圖 發明-實施例之故障位置查找方法的示意圖。如圖所示1 本方法中’首先是使該些字元線104皆呈現浮接狀態。此 步驟可利用聚焦離子束(focusedionbeam，簡稱FIB冰切斷導 ，no，也就是利用電路修補(circuit edit)的方式來達到。接 者，利用粒子束掃描標示118及12〇所指的地方。由於標 示118及120所指之處，由於導電插塞112皆與字元線 電性連接，所以等同於利用粒子束掃描字元線' 1〇4丨在此 例中，所使用的粒子東為以鎵(GaUium，Ga+)作為離子源的 200931429 wf.doc/p =子束。另外，在姻粒子束掃描圖 %’此故障樣品係擺置在提供粒子 斤不々丈障樣时 广土公-、， κ電子顯微鏡的今屬承二 (常未心 ⑽皆透過該金屬平台而接地。 ％插塞1〇8及基體 〇 在利用粒子束掃描標示118另 =二=方會開始累積正電荷’並激發出表: 其中-種。於是，便可依據激發 號的 找發生故障之字元線的位置。在此例中的；== (passive v〇ltage contrast)法來查找故雷 顯$鏡具有二次電子_器，藉以收集二次電子線且== ^部分構件接地’因此接地部分及非接地部分所激發‘ ::人電子義量_)不同，使得電子顯微鏡可贿據二^ ❹ 動電壓對比法。以此例所職的電子顯微鏡 是當掃/Γ某一定點時’若二次電子偵測器收 ==該定點所呈現的影像便是-個亮 口此在圖5 t ’與標不118所指之處電性連接的字 =線104 ’其係依序透過導電插塞1〇8、基體ι〇6及金屬平 =接地’使得標* 118所指之處的正電荷被導引至地， 於該;的正電荷累積速度緩慢，因而使得該處激發出 勺--人電子不容易被吸引回來。反之，與標示12〇所指 200931429 -----—._. -Wf.doc/p 之處電性連接的字元線1()4,其由於無法透過導電插塞 108、基體106及金屬平台來接地’以致於讓標示12〇所指 之處的正電荷累積速度較快，因而使得該處激發出來的二 -人電子=易被吸引回來。所以，在電子顯微鏡所呈現的影像 中’標示118所指之處會呈現亮，點，而標示12〇所指之處 會呈現暗點。於是，便可根據這樣的結果，來判斷字元線 104是否有發生短路故障，並得到發生故障之字元線1〇4 ❹ 驗置。接下來，便可將電性故障分析所取得的故障位元 線位置與故障字元線位置相互交錯，進—步取得故障記慎 單元的位置(例如圖5中之標示116所指之處），以利探^ 故障記憶單元的故障主因。 藉由上述貫施例的教示，可以歸納出此實施例之故障 位置查找方法的一些基本操作步驟，擴展來說，其適於查 找一積體電路(例如記憶體）内部之複數條第一導線(例如 έ己憶體中之字元線）中，發生故障之每一第一導線的位置， 其中上述之第一導線係沿第一預設方向排列。此方法的基 〇 t操作步驟如圖6所示’圖6為依照本發明—實施例之故 障位置查找方法的流程圖。請參照圖6，首先，使上述之 第一導線皆呈現浮接狀態(如步驟602所示）。接著，利用 粒子束掃描上述之第一導線，並依據激發出來的表面電子 訊號來查找發生故障之每一第一導線的位置(如步驟6〇4 所示）。 當然，若上述之積體電路是記憶體，那麼此積體電路 内部一定還包括有複數條第二導線(例如記憶體中的位元 12 200931429 wf.doc/p 二導線係沿—第二預設方向排列。那麼，在 步驟中、，更包括利用電性故障分析的方式 羊之第一導線的位置。此外，在上述實施例 識者束疋以離子束來實施，但此領域具有通常知 ㈣，即使粒子束是以電子束來實施，仍然是可 依"?、本發明之精神來查找故障導線的位置。 ❹Q 200931429 *vf.doc/p Still the examples of the various embodiments and Yang Nen; ^ fine hair _, then the structure of the two as shown in Figure 4:, which shows the local junction line of the DRAM and the matrix === =, the DRAM sample system has the short circuit fault shown in Figure 3. However, there is no way to find out the result of the u analysis. The result of the analysis is confirmed to be not two or two: The input/output connector of the two bit line terminals is sent. Newway,,,,, and the test results of the electrical fault analysis are also in such a case, the fault point indicated by the method of the present invention can be used to obtain the position of the corresponding fault memory unit. (4) Exploring the faults of faults and fresh elements. Through the electrical fault analysis, the results of the job must be marked (4) the bit line of the short-circuit fault. Next, close 5 to explain. BRIEF DESCRIPTION OF THE DRAWINGS A schematic diagram of a fault location lookup method of an embodiment. As shown in Fig. 1, in the method, the word lines 104 are first rendered in a floating state. This step can be achieved by using a focused beam (referred to as FIB ice-cutting guide, no, that is, using circuit edit). The particle beam scan is used to mark the places indicated by 118 and 12〇. Since the indications 118 and 120 point out that since the conductive plugs 112 are electrically connected to the word lines, it is equivalent to scanning the word line '1〇4' with the particle beam. In this example, the particles used are 200931429 wf.doc/p = beamlet with gallium (GaUium, Ga+) as the ion source. In addition, in the particle beam scan image%' this fault sample is placed in the case of providing particles. -,, κ electron microscopy of the current two (usually unhearted (10) are grounded through the metal platform. % plug 1 〇 8 and substrate 〇 in the use of particle beam scanning to indicate 118 = two = square will begin to accumulate positive charge 'And stimulate the table: Among them. So, you can find the position of the faulty character line according to the excitation number. In this case; == (passive v〇ltage contrast) method to find the original Ray Xian $ The mirror has a secondary electron _ device to collect the secondary electron beam and == ^ Part of the component is grounded 'so the grounded part and the ungrounded part are excited by ': human electronic quantity _), so that the electron microscope can be used to compare the two voltages. The electron microscope used in this example is the sweep. /ΓA certain point when 'If the secondary electronic detector receives == the image presented by the fixed point is a bright port. This is the word=line electrically connected to the point indicated by the label no. 104' is passed through the conductive plug 1〇8, the base ι〇6 and the metal flat=ground' so that the positive charge indicated by the mark *118 is guided to the ground, and the positive charge accumulation rate is slow. Thus, the place is inspired to scoop up - the human electrons are not easily attracted back. Conversely, the characters electrically connected to the 200931429 -----... -Wf.doc/p indicated by 12〇 Line 1 () 4, which cannot be grounded through the conductive plug 108, the base body 106, and the metal platform, so that the positive charge accumulation speed at the point indicated by the mark 12〇 is faster, thereby causing the two excited at the place - Human electronics = easy to be attracted back. Therefore, in the image presented by the electron microscope, the indications indicated by the '118 mark will appear. , point, and the point indicated by the 12 会 will appear dark. Therefore, based on such a result, it can be judged whether the word line 104 has a short-circuit fault, and the character line 1 〇 4 发生Next, the fault bit line position obtained by the electrical fault analysis and the fault word line position can be interleaved, and the position of the fault scrutiny unit is obtained step by step (for example, the indication 116 in FIG. 5 refers to In order to find the fault main cause of the fault memory unit, the basic operation steps of the fault location search method of this embodiment can be summarized by the teachings of the above embodiments, and it is suitable for finding a product. a plurality of first wires (eg, word lines in a memory) in a body circuit (eg, a memory), wherein a position of each of the first wires that is faulty occurs, wherein the first wire is along the first Set the direction. The operation steps of this method are as shown in Fig. 6. Fig. 6 is a flow chart showing a method for finding a fault location in accordance with an embodiment of the present invention. Referring to Figure 6, first, the first wires are all in a floating state (as shown in step 602). Then, the first wire is scanned by the particle beam, and the position of each of the first wires that have failed is found according to the surface electronic signal that is excited (as shown in step 6〇4). Of course, if the integrated circuit is a memory, the integrated circuit must also include a plurality of second wires (for example, a bit in the memory 12 200931429 wf.doc/p two-wire system--second pre- In the step, the position of the first wire of the sheep in the manner of electrical failure analysis is further included. Further, in the above embodiment, the beam is implemented by an ion beam, but the field has a common knowledge (4). Even if the particle beam is implemented by an electron beam, it is still possible to find the position of the faulty wire according to the spirit of the present invention.
基於上述查找故障導線位置的基本精神，在本發明所 提出的另-故障位置查找方法中，首先在製作DRAM晶片 的同時，於切割道(scribe line)上另外製作特殊的測試鍵 (test key)，以在製作DRAM晶片的過程中，先行檢驗 DRAIV[晶片内部是否可能具有故障導線，以及故障導線之 可能位置，據以判別所製造之DRAM晶片的良率，並進行 後續分析。簡明地課，就是進行晶片製程先期檢驗。所述 測試鍵的結構如圖7所示，其繪示測試鍵之其中一種實施 方式的俯視圖。在圖7中，標示730所指之區域係利用光 罩來進行修改而得’而其餘部分的構造則與DRAM晶片之 構造相同。由於測試鍵與DRAM晶片係以相同製程來製 ’因此在測试鍵中具有相同構造的部分主要是用來模擬 dram晶片内部的構造。 清繼續參照圖7 ’此測试鍵具有仿字元線(如標示702 所示）、仿位元線(如標示704所示）、絕緣層（如標示所 示），以及二種仿導電插塞(分別如標示708及710所示）。 絕緣層706例如使用氧化物(oxide)來實現，或使用多種不 同的氧化物來實現，可視實際的設計需要而改變。圖8繪 13 200931429 'wf.doc/p 示圖7中之線段A-Al的截面圖，請參照圖g，其中標示 7一〇2同樣表示仿字元線，標示7〇4同樣表示仿位元線 不706同樣表示絕緣層，而標示7〇8則表示其中一種仿^ 電插塞。圖9緣示圖7中之線段腿的截面圖，請參照 圖9 ’其中標示702同樣表示仿字元線，標* 7〇6同樣表 示絕緣層，至於標示710則為另一種仿導電插塞。由圖7〜 圖9可知，每一仿字元線7〇2的其中一端皆電性連接仿 ❹ I插塞710，且由於每一仿字元線702及每-仿導電插塞 710皆沒有耦接其他的導電物質，故使得每一仿字元線 皆呈現浮接狀態。 假若在製造DRAM晶片的過程中，DRAM晶片的位 二線截面已可呈現出如圖8所示的構造，那麼便可開始進 仃先行檢驗的程序。因此，接下來便可利用粒子束掃描仿 導電插塞710,並依據激發出來的表面電子訊號來進行被 ，電壓對比分析，以依照分析結果查找發生短路故障之仿 字7G線702的位置，並進一步推測DRAM晶片内部相對應 之子元線中是否有任一可能發生短路故障，以及可能發生 故障之字元線的位置。以下請依照說明之需要而參照圖7〜 圖9。請先參照圖8及圖9，在使用粒子束掃描的過程中， 由於這二個圖式所示截面的底部皆會透過提供粒子束之電 子顯微鏡的金屬平台而接地(即共同電位），然其中只有圖8所 示的仿導電插塞7〇8會接地，而圖9所示的仿導電插塞71〇 並不會接地。因此，若有某條仿字元線7〇2與某個仿導電插塞 708發生短路’例如在圖8中之標示712所指之處發生短路， 14 200931429 —…一 .vf.doc/p 那麼在電子顯微鏡所呈現的影像中，圖9中之標示 指的仿導電插塞710會呈現出亮點，至於其他的仿導電插 塞710則會呈現出暗點。 導電插 Ο ❹ 如此一來，便可依據亮點的多寡來判斷同一製 DRAM晶片㈣’是否也村能發生字元線輯的現象 進一步判定該製程的良率好壞，也就是進行線上監測 (mime monitor)。假若良率不合格’便可將該批製程所製造 之DRAM晶片報廢、回收或重工，不進行後續製程處理， 以免浪費製造成本。當然，既然已知道發生短路故障之仿 字元線的位置’便可用來推測在DRAM晶片内部相對應的 字元線中是否有任一可能發生短路故障，以及可能發生故 障之字元線的位置，以進行後續分析，作為改善良率之依 據。此外，在圖7所示的測試鍵實施例中，雖然仿導電插 基710係分散在圖式中的上下二側，然而使用者亦可按照 實際的需要而將該些仿導電插塞710設置在同一側。 §然’上述之測试鍵亦有其他種類的實現方式，如圖 10〜12所示。其中，圖10緣示測試鍵之另一種實施方式的 俯視圖’圖11繪示圖10中之線段A-A1的截面圖，而圖 12則緣示圖1〇中之線段B-B1的截面圖。圖7〜9所示之測 試鍵結構和圖10〜12所示之測試鍵結構的不同之處在於， 圖10〜12所示之測試鍵結構不具有仿位元線704。此外， 圖10〜12所示之測試鍵結構有一個好處，就是在利用粒子 束掃描其中一個仿導電插塞708時，若該處在電子顯微鏡 的影像中呈現出暗點，就表示該仿導電插塞7〇8並沒有電 15 »vf.doc/p 200931429 性連接至地。在這種情況之下，便可推測有可能是光罩沒 有疋義好，以致於該處根本沒有形成仿導電插塞7〇8，也 有可能是蝕刻的時候沒有處理好，以致於使得該仿導電插 塞708太短，根本沒辦法電性連接至地。 ΟBased on the basic spirit of finding the faulty wire position as described above, in the alternative-fault location finding method proposed by the present invention, first, a special test key is additionally prepared on the scribe line while the DRAM wafer is being fabricated. In the process of fabricating the DRAM chip, the DRAIV is first checked [whether the faulty wire inside the wafer and the possible position of the faulty wire are determined, so as to determine the yield of the manufactured DRAM chip and perform subsequent analysis. Concise lessons are the pre-test of the wafer process. The structure of the test key is shown in Figure 7, which shows a top view of one of the embodiments of the test key. In Fig. 7, the area indicated by the symbol 730 is modified by the reticle and the rest is constructed in the same manner as the DRAM chip. Since the test key and the DRAM chip are manufactured in the same process, the portion having the same configuration in the test key is mainly used to simulate the internal structure of the dram wafer. Continue to refer to Figure 7 'This test button has a dummy word line (as indicated by the symbol 702), a dummy bit line (as indicated by the symbol 704), an insulating layer (as indicated by the label), and two imitation conductive plugs. Plug (shown as indicated by markers 708 and 710, respectively). The insulating layer 706 is realized, for example, using an oxide, or using a plurality of different oxides, which may vary depending on actual design needs. Figure 8 draws 13 200931429 'wf.doc/p shows the cross-section of the line segment A-Al in Figure 7, please refer to Figure g, where the mark 7 〇 2 also represents the imitation word line, the mark 7 〇 4 also represents the morph The element line 706 also represents the insulating layer, while the designation 7〇8 indicates one of the imitation electric plugs. 9 is a cross-sectional view of the leg of the line segment in FIG. 7, please refer to FIG. 9 'where the symbol 702 also represents the imitation word line, the standard *7〇6 also represents the insulating layer, and the indicator 710 is another imitation conductive plug. . As can be seen from FIG. 7 to FIG. 9, one end of each of the dummy word lines 7〇2 is electrically connected to the dummy plug 710, and since each of the dummy word lines 702 and each of the dummy conductive plugs 710 are not The other conductive materials are coupled, so that each of the dummy word lines is in a floating state. If the two-line cross-section of the DRAM wafer can be constructed as shown in Figure 8 during the manufacture of the DRAM wafer, then the procedure for the first inspection can be started. Therefore, the particle beam can be used to scan the conductive plug 710, and the voltage is compared according to the excited surface electronic signal, so as to find the position of the 7G line 702 where the short circuit fault occurs according to the analysis result, and It is further speculated whether there is any short-circuit fault in the corresponding sub-line inside the DRAM chip, and the position of the word line where the fault may occur. Please refer to FIG. 7 to FIG. 9 as needed in the following description. Referring first to FIG. 8 and FIG. 9, in the process of using the particle beam scanning, since the bottoms of the sections shown in the two figures are grounded (ie, the common potential) through the metal platform of the electron microscope providing the particle beam, Only the conductive plug 7 8 shown in FIG. 8 will be grounded, and the conductive plug 71 shown in FIG. 9 will not be grounded. Therefore, if a certain word line 7〇2 is short-circuited with a certain conductive plug 708, for example, a short circuit occurs at the point indicated by the mark 712 in FIG. 8, 14 200931429 — ... a. vf.doc/p Then, in the image presented by the electron microscope, the imitation conductive plug 710 indicated in FIG. 9 will show a bright spot, and the other imitation conductive plug 710 will exhibit a dark spot. Conductive plug Ο In this way, based on the number of bright spots, it can be judged whether the same DRAM chip (4) 'can also have a character line series phenomenon. Further determine the yield of the process, that is, perform online monitoring (mime) Monitor). If the yield is unqualified, the DRAM wafers manufactured by the batch process can be scrapped, recycled or reworked without subsequent processing to avoid wasting manufacturing costs. Of course, since the position of the dummy word line where the short-circuit fault has occurred is known, it can be used to infer whether there is any short-circuit fault in the corresponding word line inside the DRAM chip, and the position of the word line where the fault may occur. For subsequent analysis as a basis for improving yield. In addition, in the test button embodiment shown in FIG. 7, although the conductive conductive interposer 710 is dispersed on the upper and lower sides of the drawing, the user can also set the imitation conductive plugs 710 according to actual needs. On the same side. § However, the above test buttons also have other types of implementations, as shown in Figures 10-12. 10 is a top view of another embodiment of the test key. FIG. 11 is a cross-sectional view of the line segment A-A1 of FIG. 10, and FIG. 12 is a cross-sectional view of the line segment B-B1 of FIG. . The test key structure shown in Figs. 7 to 9 is different from the test key structure shown in Figs. 10 to 12 in that the test key structure shown in Figs. 10 to 12 does not have the dummy bit line 704. In addition, the test key structure shown in FIGS. 10 to 12 has an advantage in that when one of the conductive plugs 708 is scanned by the particle beam, if the dark spot appears in the image of the electron microscope, the imitation is indicated. Plug 7〇8 does not have electricity 15 »vf.doc/p 200931429 is connected to the ground. Under this circumstance, it can be speculated that it is possible that the photomask is not so good that the imitation conductive plug 7〇8 is not formed at all, and it may be that the etching is not handled well, so that the imitation is made. The conductive plug 708 is too short to be electrically connected to the ground. Ο
在上迷的測試鍵實施例中，雖然都是以深溝渠(和卬 trench)式的DRAM架構來進行本發明之解說，然此領域具 有通常知識者應當知道，即使是堆疊(staek)式的dram架 構，或者是靜態隨機存取記憶體（statie rand〇m aceess memory，簡稱SRAM)，亦可實施本發明。 藉由上述實施例的教示，可以歸納出上述所提出之另 -故障位置查找方法的—些基本操作步驟，擴展來說，其 適於在製作積體電路(例如記憶體）的過程巾，查找積體電 路内部之複數條第-導線(例如記憶體㈣之字元線)是否 =任-可能與積體電路内部之複數個第—導電插塞(例如 穿设於字70線之_導電插塞，然不以此為限)的其中之一 =生，其中上述之第一導線係沿第-預設方向排 ㈣-眘1的基本操作步驟如圖13所示，圖13為依照本 、方例之另一故障位置查找方法的流程圖。請表昭 在製作積體電路的同時，於_道上製作測 線）、肺ίΛί鍵具有複數條仿第—導線(例如仿字元 每-仿H方弟一導電插塞及複數個仿第二導電插塞，且 塞1中之二中—端電性連接上述之仿第二導電插 利用粒子纽^王現洋接狀態(如步驟1302所示）。接著， 田上述之仿第二導電插塞，並依據激發出來 16 〇 o 200931429 ,v^f.doc/p 的表面電子訊絲查找發生短路故 位置(如步驟13G4所示），_ 1 ^線的 有任-可能發生短路故障。 于應之弟-導線中是否 綜上所述’本發明因使待測導線 待測導線(即第一導線)附近的導體•接至：=，= := 塞T電導:連二， 的心電子訊號來進行被動 1〇ΓΓ 域照分析妓錢發生贿故障之待 導線的位置。假若待測導線為記憶 廢 ===障分析所取得的故障位=置= ^子兀= 立置相互父錯，進一步取得故障記憶單元的位 置，以利探討故障記憶單元的故障主因。 此外，在本㈣所提έ{;{的另—方 =的同時，於切割道上另外製作特殊的刻試鍵 鍵與上述之積體電路二者的結構幾乎相同，然不同之處在 ==試鍵中之每—仿待測導線(即仿第—導線)的其= 端普會電性連接至該些仿第二導電插塞其中之—。 用粒子束掃描該4b仿第-導雷杯宜 面電子依據激發出來的表 動電壓對比分析，就可以依照分析* =找發生短路故障之仿待測導_ : =導線中是否有任—可能發生短路故障，以及可= 待測導線的位置。如此一來，測試者便可在製作 積體電路的過程中，先行檢驗積體電路内部是否可能具有 17 200931429 vf.doc/p 以及故障導線之可能位置，據以判別所製造之 積體電路的良率，並進行後續分析。 Η樣破 限定ίίί發明已以較佳實施儀露如上，然其並非用以 *任何熟冑此技藝者，在残離本發明之精神 内’‘可作些許之更動與潤飾，因此本發明之伴護 範圍當視後此ΐ料纖圍所狀者鲜。 遵 【圖式簡單說明】In the above test key embodiment, although the description of the present invention is carried out in a deep trench (and trench) type DRAM architecture, those skilled in the art should know that even a stacked (staek) type of dram The present invention may also be implemented by an architecture, or a static random access memory (SRAM). Through the teachings of the above embodiments, some basic operational steps of the above-mentioned another-fault location finding method can be summarized. For expansion, it is suitable for processing a process towel of an integrated circuit (for example, a memory). Whether a plurality of first-wires (for example, word lines of memory (4)) inside the integrated circuit are = may be a plurality of first conductive plugs inside the integrated circuit (for example, a conductive plug inserted in the line of word 70) One of the plugs, but not limited thereto, is the raw operation, wherein the first operation of the first wire is arranged along the first predetermined direction (four) - the first operation step is as shown in FIG. 13 , and FIG. 13 is according to the present invention. A flow chart of another method for finding a fault location in a square example. Please show that while making the integrated circuit, make the line on the _ road), the lung Λ Λ button has a plurality of imitation first-wire (for example, the imitation character per-like H-square-electrical plug and a plurality of imitation second conductive a plug, and the middle end of the plug 1 is electrically connected to the second conductive plug according to the state of the particle (as shown in step 1302). Then, the second conductive plug is imitation, and According to the excitation of 16 〇o 200931429, v^f.doc/p surface electronic signal to find the location of the short circuit (as shown in step 13G4), _ 1 ^ line of the role - may occur short circuit fault. - In the wire, whether or not the above-mentioned invention is connected to the conductor in the vicinity of the wire to be tested (ie, the first wire) to be connected to: =, = := plug T conductance: connect the second, the heart electronic signal to carry out Passive 1 〇ΓΓ 照 照 〇ΓΓ 〇ΓΓ 〇ΓΓ 〇ΓΓ 〇ΓΓ 〇ΓΓ 〇ΓΓ 〇ΓΓ 〇ΓΓ 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The location of the fault memory unit to facilitate the discussion of the fault cause of the fault memory unit. In addition, at the same time as the other side of the (4), the special test key is additionally formed on the scribe line and the structure of the integrated circuit is almost the same, but the difference is == Each of the test keys - the analog wire (ie, the analog wire - the wire) is electrically connected to the second conductive plugs. The particle beam is used to scan the 4b analog-lead According to the analysis of the surface voltage of the cup, the surface of the cup can be analyzed according to the analysis. * = Look for the short-circuit fault to be detected _ : = = whether there is any wire in the wire - short circuit fault may occur, and = the wire to be tested In this way, the tester can first check whether there is a possible position inside the integrated circuit and the possible position of the faulty wire during the process of making the integrated circuit, thereby judging the manufactured body. The yield of the circuit, and the subsequent analysis. 发明 破 ί ί ί ί ί ί ί ί ί 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明a little change and retouch, so the invention When the protective scope of this ΐ view around the fiber-like material by fresh. Compliance figures briefly described []
圖1繪示dram的局部結構。 圖2繪示電性故障分析的一種測試結果。 圖3為圖1所示之局部結構發生短路的示意圖。 圖4纷示電性故障分析的另一種測試結果。 圖5為依照本發明—實施例之故障位置查找方法 意圖。 圖6為依照本發明一實施例之故障位置查找方法的流 程圖。 圖7繪示測試鍵之其中，種實施方式的俯視圖。 圖8繪示圖7中之線段A-A1的截面圖。 圖9綠示圖7中之線段b_b 1的截面圖。 圖緣示測試鍵之另〆種實施方式的俯視圖。 圖丨1繪示圖1〇中之線段A-A1的截面圖。 圖丨2繪示圖1〇中之線段B-B1的截面圖。 圖13為依照本發明一實施例之另一故障位置杳 法的流程圖。 【主要元件符號說明】 18 200931429 wf.doc/p 102 :位元線 104 :字元線 106 :基體 108、112 :導電插塞 110 :導線 114 :絕緣層 116、118、120、210〜216、712、714、730 :標示 602、604、1302、1304 :步驟 702 :仿字元線 704 :仿位元線 706 :絕緣層 708、710 :仿導電插塞 e_ :二次電子 〇 19Figure 1 shows the local structure of the dram. Figure 2 illustrates a test result of an electrical fault analysis. FIG. 3 is a schematic view showing a short circuit of the partial structure shown in FIG. 1. FIG. Figure 4 shows another test result of electrical fault analysis. Figure 5 is a diagram of a fault location lookup method in accordance with an embodiment of the present invention. Figure 6 is a flow diagram of a fault location lookup method in accordance with an embodiment of the present invention. Figure 7 illustrates a top view of one embodiment of a test key. Figure 8 is a cross-sectional view of the line segment A-A1 of Figure 7. Figure 9 is a green cross-sectional view of the line segment b_b 1 in Figure 7. The figure shows a top view of another embodiment of the test button. Figure 1 is a cross-sectional view showing a line segment A-A1 in Figure 1A. Figure 2 is a cross-sectional view showing the line segment B-B1 in Figure 1A. Figure 13 is a flow diagram of another fault location method in accordance with an embodiment of the present invention. [Major component symbol description] 18 200931429 wf.doc/p 102: bit line 104: word line 106: substrate 108, 112: conductive plug 110: wire 114: insulating layer 116, 118, 120, 210~216, 712, 714, 730: designation 602, 604, 1302, 1304: step 702: imitation word line 704: emulation bit line 706: insulating layer 708, 710: imitation conductive plug e_: secondary electron 〇 19