JP5055871B2 - Wiring failure detection test structure and wiring failure detection method - Google Patents

Description

  The present invention relates to a wiring defect detection test structure and a wiring defect detection method using the same, and more particularly to a wiring defect detection test structure applicable to systemically generated defects and a wiring defect detection method using the same. About.

  Wiring defects in a semiconductor device, in particular, disconnection or short-circuiting of wiring are fatal defects, and a semiconductor device having such a defect cannot be shipped as a non-defective product. That is, the wiring defect has a great influence on the manufacturing yield of the semiconductor device. Therefore, in order to improve the yield, it is extremely important to prevent wiring defects.

  In order to prevent such wiring defects in advance, a wiring defect detection wafer is periodically flowed to a semiconductor manufacturing line to evaluate the presence and degree of wiring defects. As a method for detecting a defective portion, there are methods using an optical inspection method and a scanning electron microscope (SEM).

  The optical inspection method has a high throughput, but it is difficult to confirm the shape of minute foreign matters or defects. On the other hand, the SEM method can easily observe fine foreign matters and defects, but has a problem of low throughput (processing amount).

  Although the above inspection method is for observing the shape of the wiring, an electrical test for conducting an energization test on the wiring to be inspected is also performed (for example, see Patent Document 1). However, for this electrical test, it is necessary to provide a pad in advance at the end of the wiring to be inspected and bring the electrical probe into contact with this pad.

  Recently, new test methods using SEM, which are different from these inspection methods, have begun to be used. This method is called a voltage contrast method (see, for example, Patent Document 2).

  The voltage contrast method retains the characteristic of the SEM method that it is easy to inspect fine wiring, while eliminating the low throughput that has been a problem of the conventional SEM method. Further, according to this method, it is possible to determine whether or not the wiring is electrically disconnected without providing a pad for the electric probe.

  The voltage contrast method detects an electrical defect of a wiring from the difference in secondary electron image intensity. When a conductive pattern such as wiring is irradiated with an electron beam, the conductive pattern is charged according to its electrical environment (for example, whether it is electrically connected to or insulated from the semiconductor substrate), and according to the amount of charge. Have a potential. The difference in potential generated in this way affects the amount of secondary electrons generated by electron beam irradiation. That is, many secondary electrons are emitted from the conductive pattern having a low potential, and a bright SEM image is obtained. On the other hand, only a small amount of secondary electrons are emitted from the conductive pattern having a high potential, resulting in a dark SEM image. The voltage contrast method is an inspection method for detecting whether or not there is a defect such as a disconnection in the conductive pattern using the difference in brightness (contrast).

The test object of the voltage contrast method is a structure having conductivity. For this reason, the whole is charged only by irradiating a part of it with an electron beam. Therefore, in the voltage contrast method, unlike the conventional SEM method, it is not necessary to irradiate the entire wiring with the electron beam, and it is sufficient to irradiate a part of the wiring. Therefore, compared to the conventional SEM method for observing the entire image of the wiring, the voltage contrast method dramatically improved the measurement speed and the throughput.
Japanese translation of PCT publication No. 2004-501505 (paragraph [0005]) JP-A-11-330181 (paragraph [0005] to paragraph ([0008])

  In the voltage contrast method, “array inspection” is usually performed. The voltage contrast method has the highest throughput when this “array inspection” is executed.

  However, array inspection has a problem that it does not function effectively against defects that occur systematically (defects that inevitably occur under certain process conditions). This point will be described in detail below.

  15 and 16 show an example of a wiring defect detection test structure (hereinafter abbreviated as “test structure”) used in the voltage contrast method. FIG. 15 is a plan view of the test structure, and FIG. 16 is a sectional view taken along the line AA ′.

  The array inspection is performed using a test structure in which wirings 1 having the same shape are formed on the insulating film 2 at a constant period as shown in FIG. One end of each wiring 1 is connected to a wiring (ground contact 4) electrically connected to the semiconductor substrate 3 as shown in FIG. The ground contact 4 is connected to a diffusion layer 6 provided in the semiconductor substrate 3 through a via 5 as shown in FIG. Accordingly, the wiring 1 has the same potential as that of the semiconductor substrate 3.

  An elongated rectangular array inspection region 19 that surrounds the other end of the wiring 1 is set in the test structure configured as described above, and the inside of the region is scanned with an SEM electron beam.

  If the wiring 1 is not defective, even if the electron beam is irradiated and two electrons are emitted, the wiring 1 is connected to the semiconductor substrate and is not charged and the potential does not change. That is, the potential of the wiring 1 is maintained at the same potential as the sample stage of the SEM with which the semiconductor substrate 3 is in contact.

  However, when the defect 8 is present in a part of the wiring 1 and the wiring 1 is disconnected as shown in FIG. 17, even if secondary electrons are emitted, no charge is supplied from the semiconductor substrate 3. For this reason, the wiring 9 ahead of the defect 8 is charged up to increase the potential.

  Therefore, as shown in FIG. 18, the SEM image obtained for the array inspection region 19 is dark in the wiring 9 that is disconnected due to the defect 8 and bright in the wiring 10 that is not disconnected. Although the SEM image is darkest on the insulating film 2, the insulating film is displayed brightest for easy comparison with FIG.

  Next, the obtained SEM image is divided into comparison sections 12 that are repeated at the same period as the repetition period 11 of the wiring 1 (in FIG. 18, it is described that the comparison sections are separated. They are in contact with each other.

  Here, when the SEM image signals of the adjacent comparison sections are compared, there is no difference in the comparison results between the unbroken sections, but in the SEM image of the unbroken wiring 10 and the disconnected wiring 9 Differences occur in the comparison results. Therefore, it is possible to identify the disconnected wiring 9 from this comparison result. Specifically, the difference in image signal intensity between adjacent sections is determined, and whether or not there is a disconnection is determined based on whether or not the difference exceeds a certain threshold.

  As described above, in the “array inspection”, it is possible to determine the presence / absence of disconnection only by observing the SEM image at one end of the repeatedly formed wiring 1. Moreover, the presence or absence of disconnection can be determined by dividing the SEM image of the wiring end into small sections for each wiring image and comparing the image signal for each adjacent small section. Thus, high throughput inspection is achieved. However, array inspection has the following problems.

  The array inspection of the test structure as shown in FIG. 15 is effective in finding defects that occur accidentally in the process of forming the wiring 1, for example, disconnection due to dust adhesion. However, it is difficult to find defects that occur inevitably under certain conditions (systematic defects).

  The simplest systematic defect is the in-plane distribution of dry etching. In dry etching, for example, under certain conditions, the etching rate tends to be high at the center of the wafer and low at the periphery. Therefore, when the wiring is formed by processing the metal layer formed on the insulating film by dry etching, disconnection is likely to occur at the center of the wafer. Further, when a via hole is formed by etching the insulating film, the via hole does not penetrate the insulating film in the peripheral portion of the wafer and is easily disconnected.

  The etching rate of dry etching is also affected by the wiring interval and the like. For example, when wiring is formed at a specific interval, disconnection may easily occur. A similar phenomenon occurs in various processes other than dry etching, such as a photolithography process. A combination of these phenomena may inevitably cause defects in the wiring pattern in the manufacturing process of the semiconductor device.

  In the test structure as shown in FIG. 15, when the distance between the wirings 1 is such that a systematic defect is generated, the defects are simultaneously generated for all the wirings 1. Further, in the test structure in which the wiring groups 17a, 17b, and 17c having different wiring intervals are juxtaposed as shown in FIG. 3, when the wiring group 17b generates a systematic defect, all the wirings in the wiring group 17b are used. A defect (for example, disconnection) occurs in the wiring groups 17a and 17c, and the defect hardly occurs.

  In such a case, in the test structure of FIG. 15, the SEM image in the array inspection region 19 is dark for all wirings. On the other hand, if a defect occurs accidentally, the SEM image of the array inspection area 19 is a mixture of bright and dark wiring as shown in FIG.

  When an array inspection is performed on an SEM image in which all wiring images have become dark due to the occurrence of systematic defects, there is no difference in image signals between adjacent sections, leading to an erroneous inspection result that there is no disconnection. Will be. That is, the array inspection in the voltage contrast method has a problem that it is difficult to detect systematic defects.

  Therefore, an object of the present invention is to provide a test structure capable of array inspection even for systematic defects and a wiring failure detection method using the test structure.

  In order to achieve the above object, according to a first aspect of the present invention, a wiring defect detection wiring group in which a plurality of predetermined wirings are arranged in a certain direction is repeatedly arranged in a predetermined direction at a certain period. Wiring defect detection consisting of a defect detection area and an array inspection area in which a comparison section including a number of inspection wirings extending from the wiring is different from the wiring defect detection wiring group is repeatedly arranged in a predetermined direction at a constant period. Test structure for use.

  According to a second aspect of the present invention, a secondary electron image of the array inspection region is taken using the test structure according to the first aspect as a test object, and the intensity of the secondary electron image is measured between adjacent contrast sections. This is a method for detecting a wiring defect, characterized in that an electrical defect is detected in comparison with the above.

  Therefore, according to the present invention, the number of constituent wirings differs between the wiring pattern repeatedly arranged in the wiring defect detection area and the wiring pattern repeatedly arranged in the array inspection area. For this reason, even if a systematic defect occurs, the position of the array inspection wiring in which the defect has occurred differs in the adjacent comparison section. Therefore, the array inspection can be performed even for systematic defects. Further, according to the present invention, since one type of wiring pattern is repeatedly arranged in the wiring defect detection area, the coverage characteristic of the inspection pattern is high.

  According to a third aspect of the present invention, there is a wiring failure in which a plurality of wiring failure detection wiring groups in which a plurality of predetermined wirings are arranged in a certain direction while changing the pitch between the wirings are repeatedly arranged in a certain direction at a certain period. A test structure for detection.

  According to a fourth aspect of the present invention, the test structure according to the third aspect is used as a test object, a secondary electron image of the end portion of the wiring for detecting a wiring defect is photographed, and the intensity of the secondary electron image is measured adjacently. It is to detect an electrical defect in contrast between contrasted sections.

  Therefore, according to the present invention, since one type of wiring pattern is repeatedly arranged in the wiring defect detection area, the coverage characteristic of the inspection pattern is high.

  According to the present invention, even when an electrical defect is periodically generated in a specific wiring on a wiring pattern repeatedly arranged at a constant period, the electrical defect is efficiently detected using the array inspection of the voltage contrast method. can do. That is, even if a systematic defect occurs on a wiring pattern that is repeatedly arranged, an array inspection characterized by high throughput is possible, and the inspection efficiency can be improved.

  Further, since the test structure according to the present invention is composed of only one type of inspection pattern, the coverage characteristic of the inspection pattern is improved.

  Embodiments of the present invention will be described below with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to the matters described in the claims and equivalents thereof.

(1) First Embodiment An example of a test structure according to the present invention will be described. The test structure described below may be formed as a component of a dedicated chip arranged at regular intervals in the wafer, or may be formed in a scribe region. The wafer on which the test structure is formed is periodically flowed to the semiconductor manufacturing line in order to prevent wiring defects due to defects in the semiconductor manufacturing line. After completion of the wiring process in the semiconductor manufacturing line, it is inspected by the voltage contrast method whether or not the wiring has been normally formed in the manufacturing line.

  Further, the test structure may be formed on the entire wafer. Such a wafer is effective in determining the value of a manufacturing parameter when a new manufacturing process is introduced. For this purpose, first, the test structure shown in FIG. 1 is formed on the entire surface of the wafer by changing various parameter values of the manufacturing process to be introduced. By inspecting the wafer formed in this way by the voltage contrast method, it is possible to know the suitability of the used manufacturing parameters.

(Configuration of test structure)
FIG. 1 is a plan view of a test structure according to the present embodiment. FIG. 2 is a sectional view taken along the line AA ′.

  The test structure according to the present embodiment includes an insulating film 2 formed on a semiconductor substrate 3 and a wiring defect detecting wiring 13 having a certain shape, parallel to the insulating film 2 while gradually increasing the pitch 14 thereof. The wiring defect detection wiring group 15 is formed. Further, the wiring failure detection wiring group 15 is repeatedly arranged at a constant period in a direction perpendicular to the wiring failure detection wiring 13 to constitute a wiring failure detection region 40.

  Here, “pitch” means the distance between the center lines penetrating in the longitudinal direction through the centers of the wirings repeatedly arranged in parallel.

  One end of the wiring defect detection wiring 13 is connected to a wiring (ground contact 4) electrically connected to the semiconductor substrate 3. The ground contact 4 is connected to the semiconductor substrate 3 through a via 5 as shown in FIG.

  On the other hand, the other end of the wiring failure detection wiring 13 is arranged at equal intervals after being extended and bent into a crank shape. The wiring ends arranged at equal intervals are used as secondary electron image observation wiring (hereinafter referred to as inspection wiring or array inspection wiring 16).

  The region including the array inspection wiring 16 constitutes a comparison section 12 for array inspection, and the comparison section 12 is repeatedly arranged in a direction perpendicular to the array inspection wiring 16 at a constant period to form an array inspection area 19.

  The material, film thickness, line width, etc. of each wiring 13 are determined by the process of the production line to be inspected. For example, the material is Cu and the film thickness is 200 nm. The intervals between the wiring defect detection wirings 13 are 100 nm, 200 nm, 400 nm, 800 nm, and 800 nm in order from the left end. On the other hand, the interval between the array inspection wirings 16 is uniform at 460 nm. The length 13a of the wiring failure detection wiring 13 is about 900 μm, and the length 16a of the array inspection wiring 16 is about 100 μm.

  The wiring defect detection wiring 13 does not need to have the same shape, and may be appropriately changed depending on the content of the wiring defect to be inspected. For example, the width of the wiring defect detection wiring 13 may change for each wiring. Even in this case, the width of the array inspection wiring 16 is preferably constant.

  Further, it is not always necessary to gradually increase the pitch 14 of the wiring defect detection wiring 13. It may be gradually decreased or changed randomly. Further, the width of the wiring defect detection wiring 13 may be changed while the pitch is constant.

  That is, the shape and pitch of the wiring defect detection wiring 13 may be changed as appropriate according to the content of the wiring defect to be inspected.

(Function)
Next, why such a configuration is effective for systematic defects will be described.

  In order to detect systematic defects, the inventors first devised a simple structure test structure which is an improvement over the conventional test structure. However, it has been found that using such a test structure causes various problems.

  FIG. 3 shows a plan view of the test structure first considered by the inventors. This test structure is provided with a first wiring failure detection wiring group 17a with a constant pitch between wirings, and then a second wiring failure detection wiring group 17b with a slightly increased pitch is adjacent. Thereafter, the third and fourth wiring defect detection wiring groups are formed while gradually increasing the pitch. One end of each wiring is connected to the ground contact 4. That is, this test structure is a structure in which conventional test structures are juxtaposed in the horizontal direction while gradually increasing the pitch.

  In the test structure of FIG. 3, array inspection regions 19 having different pitches are individually set at the ends of the wiring failure detection wiring groups opposite to the ground contacts 4. The reason why the array inspection area 19 is set individually is that the wiring pitch is different for each wiring failure detection wiring group. That is, the width of the section to be compared is different for each wiring failure detection wiring group.

  When a systematic defect occurs in such a test structure, the occurrence of the defect cannot be detected even if the array inspection is performed only in the same wiring defect detection wiring group.

  For example, when a systematic defect occurs in the second wiring defect detection wiring group 17b and no systematic defect occurs in the first and third wiring defect detection wiring groups 17a and 17c, the second The SEM images of the wiring failure detection wiring group 17b are all dark (the SEM images of the first and third wiring failure detection wiring groups 17a and 17c are all bright). Therefore, even if the SEM images of the comparison section 19 are compared only within the second wiring failure detection wiring group 17b in which a defect has occurred, no difference occurs.

  However, systematic defects can be detected by performing an array inspection between a wiring defect detection wiring group in which no defect has occurred and a wiring defect detection wiring group in which a defect has occurred.

  The SEM image of the comparison section located at the rightmost end of the first wiring failure detection wiring group 17a is bright, and the SEM image is dark in the comparison section positioned at the leftmost end of the second wiring failure detection wiring group 17b. Therefore, a systematic defect can be detected by comparing the SEM images in the comparison section between the rightmost end of the first wiring failure detection wiring group 17a and the leftmost end of the second wiring failure detection wiring group 17b. .

  However, such a test structure has the following drawbacks. First, as already described, since the width of the section 21 to be compared in each array inspection area 19 is different, there is a drawback that a different section width must be set in the inspection apparatus for each array inspection area.

  Another problem arises when the systematic defect generation condition depends on the position in the wafer or dedicated chip.

  For example, whether or not a systematic defect occurs does not depend only on the wiring structure such as the wiring interval and the process conditions such as the reaction gas flow rate, but the arrangement position of the wiring group for detecting the wiring defect in the dedicated chip. For example, it depends on whether it is arranged at the end of the dedicated chip or at the center.

  For example, the first wiring failure detection wiring group 17a with a narrow pitch is a dedicated chip arranged inside the second wiring failure detection wiring group 17b with a large pitch, and is connected to the first wiring failure detection wiring group 17a. Systematic defects shall occur. However, assuming that such a defect does not occur in the vicinity of the end of the dedicated chip, when a dedicated chip in which the first wiring defect detection wiring group 17a is arranged at the left end of the dedicated chip is prepared, systematic The occurrence of defects cannot be detected. This is a problem caused by the low coverage (coverage) of the dedicated chip or the entire wafer by the wiring group having a specific pitch.

  A wiring structure that solves such a problem is the wiring defect detection wiring group 15 of FIG.

  In the wiring failure detection wiring group 15 in FIG. 1, the pitch between the wirings gradually increases inside the wiring failure detection wiring group. That is, various wiring intervals are realized by one type of wiring pattern. Therefore, it is possible to detect a systematic defect depending on the wiring interval only by repeatedly arranging the wiring group at a constant period 22 as shown in FIG.

  Moreover, in the test structure of FIG. 4, there is only one type of wiring group. Therefore, the coverage is 100%. That is, the problem of coverage is solved.

  However, when such a structure is adopted, a new problem peculiar to array inspection occurs.

  The repeating unit in the test structure of FIG. 4 is the wiring defect detection wiring group 15. Accordingly, the comparison section 23 as a unit of array inspection includes all the wirings included in the wiring defect detection wiring group 15.

  On the other hand, the systematic defect 8 occurs in the wiring corresponding to a specific pitch inside the wiring failure detection wiring group 15 as shown in FIG. Therefore, the secondary electron image obtained by scanning the array inspection region 19 with the electron beam, that is, the SEM image, is the same regardless of the contrast section 23 as shown in FIG. For this reason, when an array inspection is performed on the test structure of FIG. 4, an erroneous conclusion that no defect exists is obtained.

  Such a problem is solved in the test structure of the present invention shown in FIG.

  The test structure shown in FIG. 1 is arranged at equal intervals in the test structure shown in FIG. 4 after the end of the wiring failure wiring 13 is extended and bent into a crank shape on the side opposite to the contact ground 4. ing.

  FIG. 7 is an SEM image when a systematic defect 8 occurs in the test structure shown in FIG. In the array inspection area 19 in which the wiring intervals are equal, the areas 26, 27, 28, 29, and 30 including only one wiring are the unit of repetition. If this section is a unit of contrast of SEM images in the array inspection, that is, a comparison section, the occurrence of systematic defects can be detected.

  FIG. 8 is an SEM image used for array inspection, that is, an SEM image of the array inspection region 19. The SEM images coincide in the first contrast section 26 and the second contrast section 27, but the SEM is different in the second contrast section 27 and the third contrast section 28. Similarly, the SEM images are different in the third contrast section 28 and the fourth contrast section 29, and the SEM images are the same in the fourth contrast section 29 and the fifth contrast section 30. From this result, it can be seen that there is a defect in the wiring defect detection wiring whose end is extended to the third contrast section 28.

  The systematic defect can be detected by the test structure shown in FIG. 1 because the wiring defect detection wiring groups 15 having different pitches between the built-in wirings are repeatedly arranged, and the array inspection. This is because the period in which the wiring extended in the region 19 is repeatedly arranged is different.

  In FIG. 1, the number of inspection wirings included in the comparison section is one. However, as a requirement for the array inspection to function effectively, it is not essential that the number of wirings included in the comparison section is one. Absent. For example, when the number of wirings included in the wiring failure detection wiring group 15 is 10, the number of wirings included in the comparison section may be 5 (or 15).

  As the number of wirings included in the comparison section is smaller, the sensitivity of the comparison inspection is higher. On the other hand, if the number of wirings included in the comparison section is increased, the inspection efficiency is improved accordingly. Therefore, the number of wirings included in the comparison section may be appropriately designed in consideration of the conditions for confirming the existence of wiring defects.

  For example, when the inspection sensitivity is important, the number of wirings is one, and when the inspection efficiency is important, the number of wirings included in the wiring defect detection wiring group 15 is 0.5 as in the above-described example. Double or 1.5 times is preferable (however, the wiring included in the wiring defect detection wiring group 15 is an even number of 4 or more).

  However, the number of wirings included in the comparison section must not be an integral multiple (× 1, × 2, × 3...) Of the number of wirings included in the wiring failure detection wiring group 15. For example, in the test structure of FIG. 1, the number of wirings included in the wiring defect detection wiring group 15 is five, so the number of inspection wirings included in the comparison section is five, ten, and fifteen. It must not be ... This is because in such a case, the SEM images in each comparison section are the same for systematic defects.

  The wiring pitch in the comparison section does not need to be constant. This is because, even if the pitch is not constant, SEM images can be compared if the comparison sections having the same structure are arranged periodically and repeatedly.

  As described above, according to the present embodiment, it is possible to efficiently detect defects that occur systematically. In addition, the coverage characteristics of the inspection pattern (wiring group serving as a unit of defect detection) are improved.

(2) Second Embodiment Next, another example of the test structure according to the present invention will be described.

  FIG. 9 is a plan view of a test structure according to the second embodiment. FIG. 10 is a sectional view thereof.

  This test structure has a wiring failure detection wiring group 15 in which wiring failure detection wirings 13 made of via chains are formed in parallel while the pitch is gradually increased. Further, the wiring failure detection wiring group 15 has a wiring failure detection area 40 that is repeatedly arranged at a constant period in a direction perpendicular to the wiring failure detection wiring 13.

  The wiring defect detection wiring 13 is composed of first and second metal layers 31 and 32 embedded in the first to fourth interlayer insulating films 2a, 2b, 2c and 2d and vias 5 connecting them. Is done.

  One end of each wiring failure detection wiring 13 constituting the wiring failure detection wiring group 15 is connected to a wiring (ground contact 4) electrically connected to the semiconductor substrate 3. The ground contact 4 is connected to the semiconductor substrate 3 via ground contact vias 5a and 5b as shown in FIG.

  On the other hand, the other ends of the wiring failure detection wirings 13 are extended and bent into a crank shape, and then arranged at equal intervals. The ends of the wirings arranged at equal intervals are used as voltage contrast measurement wirings, that is, array inspection wirings 16.

  The structure of the wiring 13 depends on the manufacturing process to be tested. As an example, the material of the first and second metal layers 31 and 32 is Cu, and the film thickness is 200 nm. The via 5 is made of Cu (material). The film thicknesses of the first to fourth interlayer insulating films 2a, 2b, 2c and 2d are 200 nm, respectively. The intervals of the wiring defect detection wirings are 100 nm, 200 nm, 400 nm, 800 nm, 800 nm, 100 nm, 200 nm,... In order from the left end. The planar shape of the via hole is a square with a side of 100 nm, and the via interval is 200 nm. On the other hand, the interval between the array inspection wirings 16 is constant at 460 nm. The length of the wiring defect detection wiring is about 900 μm, and the length of the array inspection wiring is about 100 μm.

  When such a test structure is used, a defect in the multilayer wiring can be detected. For example, disconnection due to poor formation of via holes can be found.

(3) Third Embodiment Next, a wiring failure detection method according to an embodiment of the present invention will be described. FIG. 11 is a schematic diagram of an inspection apparatus used in this detection method. FIG. 12 is a flowchart of an inspection program used in this inspection apparatus.

  As a pre-stage of implementation of this inspection method, first, an inspection sample to be subjected to this inspection method is manufactured on a semiconductor element manufacturing line where it is desired to determine the quality of the wiring process.

  As a test sample, a dedicated chip comprising the test structure shown in FIG. 1 or FIG. 9 is arranged on a semiconductor wafer at regular intervals in a vertical direction and a fixed direction together with an integrated circuit being produced on the same manufacturing line. use. Further, the test structure of FIG. 1 or FIG. 9 may be arranged in the scribe region of the semiconductor wafer.

  Further, a dedicated wafer in which the dedicated chip is arranged on the entire surface of the semiconductor wafer may be used. Such a dedicated wafer can be effectively used to determine process parameters in the introduction or development of a new semiconductor process.

  In this embodiment, the quality of wiring is inspected by the voltage contrast method using the wafer prepared in this way as an inspection sample.

  In the voltage contrast method, a plurality of conductors (for example, wirings) arranged on an insulating film are charged by irradiating them with an electron beam to detect electrical defects in the conductors. Instead of an electron beam, a particle beam capable of generating secondary electrons such as a focused ion beam or a light beam (particle beam made of photons) can be used. The amount of charge due to particle beam irradiation varies depending on the electrical environment of the conductor (for example, the wiring is disconnected halfway and electrically separated from the semiconductor substrate). Different electric potentials are generated in the respective conductors according to the difference in the charge amount. This difference in potential affects the intensity of secondary electrons generated from the conductor. That is, the higher the potential of a charged conductor, the more strongly the electrons are attracted, so the amount of secondary electrons generated is reduced. Therefore, the electrical environment in which the conductor is placed can be detected by taking a secondary electron image of the conductor.

  In the voltage contrast method, a secondary electron image is usually used for analysis. The secondary electron image is an image of the intensity distribution of secondary electrons generated by particle beam irradiation. However, in the voltage contrast method, a planar two-dimensional image is not essential, and analysis can also be performed based on a one-dimensional image obtained by scanning a particle beam linearly.

  Although there are a plurality of methods for analyzing the secondary electron image, the test structure according to the present invention is particularly suitable for array inspection. As shown in FIG. 1, the test structure according to the present invention has an array inspection region 19 in which a section including a predetermined number of ends formed by extending the conductor is repeatedly arranged in a predetermined direction at a constant cycle. is doing.

  In the array inspection of this embodiment, the secondary electron image of the array inspection area 19 is divided in units of the above sections. Next, the intensity of the secondary electron image corresponding to each section is compared with the adjacent section to detect a difference in secondary electron image intensity between the two sections. Based on this result, an electrical environment (for example, presence or absence of disconnection or the like) in which the conductor is placed is detected.

  Next, the voltage contrast inspection apparatus in FIG. 11 and the inspection program in FIG. 12 will be described.

  The voltage contrast inspection apparatus includes an electron gun 51 for generating an electron beam, a condenser lens 52 that focuses the electron beam into a parallel beam, a deflection coil 53 for deflecting the focused electron beam, and a deflected beam. Electron beam control for controlling the objective lens 54 for focusing the electron beam on the sample surface, the sample stage 56 for placing the sample 55, the secondary electron detector 57 for detecting secondary electrons generated from the sample 55, the electron gun 51 and the like. A scanning electron microscope main body (SEM main body 60) including an apparatus 58 and a stage control unit 59 that controls movement of the sample stage is included.

  The voltage contrast inspection apparatus further includes a main body control unit 61 that controls the SEM main body 60 to capture a secondary electron image, a control program 64 for the SEM main body 60, and a recording device 66 that records a program 65 for array inspection. And a recording device 63 for recording image information (image file 62) of the captured secondary electron image.

  A series of steps from taking a secondary electron image to the test structure to array inspection is controlled by the main body control unit 61. FIG. 12 is a flowchart of a program for this control. The procedure of this inspection method will be described according to this flowchart.

  The operator of this inspection apparatus places the above-described wiring failure detection wafer, that is, the sample 55 on the sample stage 56 of the SEM main body 60 and sets the sample stage 56 so that the left end (or right end) of the array inspection region is positioned at the center of the stage. Adjust the position. The control program 64 of the SEM main body 60 is read from the recording device 66 into the main body control unit 61 before these processes.

  Next, the operator causes the main body control unit 61 to read the array inspection program 65 stored in the recording device 66. Thereafter, the inspection program is started, and the parameters for array inspection (the length and width of the comparison section, the number of comparison section repetitions, the position of each test structure in the wafer, and the secondary electron image of the adjacent comparison section are compared. (Threshold value or the like) is input (S1).

  When the parameters are input, the main body control unit 61 operates the SEM main body 60 based on the input parameters to take a secondary electron image of the array inspection region 19 of each test structure (S2). The obtained secondary electron image is digitized and recorded in the recording device 63 as an image file (S2).

  The secondary electron image is obtained by scanning the surface of the sample with an electron beam in a plane and measuring the intensity of the secondary electron beam generated at that time. The surface scanning of the electron beam is obtained by repeatedly scanning the electron beam generated by the electron gun 51 in the oblique direction with the deflection coil 53 and scanning the sample stage in one direction.

  Secondary electrons generated by the electron beam irradiation are detected by the secondary electron detector 57, and the intensity is recorded. The main body control unit 61 constructs a secondary electron image from the recorded secondary electron intensity and the irradiation position of the electron beam.

  When the secondary electron image capturing of all the test structures is completed, the main body control unit 61 reads the recorded image file from the recording device 62 (S3).

  Next, the main body control unit 61 divides the read image file for each comparison section based on the parameters (S4). Thereafter, the secondary electron images are compared between adjacent comparison sections, and whether or not the comparison result exceeds the input “threshold value” is compared (S5).

  If the comparison result is equal to or less than the threshold value, the result of normality is recorded, and if the comparison result is equal to or greater than the threshold value, the result of abnormality is recorded together with the combination of the respective comparison sections (S6). The above steps (S5 to S6) are repeated for all the comparison sections divided in the fourth step (S4) (S7).

  When the above processing is completed for all the comparison sections, the main body control unit 61 outputs the inspection result (the combination of the comparison sections determined to be abnormal and their positions) to the output unit such as a display screen, and the inspection program is completed. (S8).

  Next, how the quality of the wiring and the like is judged from the secondary electron image obtained according to the above process and the electron image will be described.

  First, the case where an electron beam is irradiated to the test structure in which the defect 8 exists as shown in FIG. 13 will be described. The wiring failure detection wiring 13 is connected to the ground contact 4. If there is no defect in the wiring defect detection wiring 13, even if two electrons are emitted by electron beam irradiation, the wiring defect detection wiring 13 is replenished with electrons from the semiconductor substrate 3. Is not charged and the potential does not change. That is, the potential of the wiring defect detection wiring 13 is kept at the same potential as the SEM sample stage with which the semiconductor substrate 3 is in contact. Therefore, the amount of secondary electrons generated is not affected by electron beam irradiation. For this reason, the secondary electron image of the wiring defect detection wiring 13 remains bright.

  On the other hand, when the electron beam is irradiated to the wiring 35 that is disconnected by the defect 8 and secondary electrons are generated, electrons are not supplied from the semiconductor substrate 3 before the defect 8. For this reason, in the part ahead of the defect 8, the wiring 35 is charged up and the potential becomes high. Therefore, the generation amount of secondary electrons is reduced as compared with the case where there is no defect 8, and the secondary electron image becomes dark.

  Therefore, if the entire test structure of FIG. 13 is irradiated with an electron beam, a secondary electron image as shown in FIG. 7 is obtained.

  In step S3 of the inspection program of FIG. 13, only the secondary electron image for the array inspection area 19 shown in FIG. 7 is taken. The obtained secondary electron image is dark in the wiring 35 obtained by extending the wiring defect detection wiring that is disconnected due to the defect 8 and bright in the wiring 13 obtained by extending the wiring defect detection wiring in which the defect 8 does not exist.

  In step S4, the obtained secondary electron image is divided as shown in FIG. 8 based on the width of the inputted comparison section, and in step S5, the intensity of the secondary electron images in the adjacent comparison sections 26 to 30 is compared. Then, it is determined whether or not the comparison result exceeds the input “threshold value”. The combination of the comparison section 26 and the comparison section 27 is determined to be “threshold value” or less, and the combination of the comparison section 27 and the comparison section 28 is determined to be “threshold value” or more. Similarly, the combination of the comparison section 28 and the comparison section 29 is determined to be “threshold value” or more, and the combination of the comparison section 29 and the comparison section 30 is determined to be “threshold value” or less. These results are recorded with each contrast interval combination.

  The comparison section does not have to include one array inspection wiring line as shown in FIG. For example, two pieces may be included, or four pieces may be included. However, it should not be the same number (5) as the number of wires included in the wiring failure detection wiring group, or an integer multiple thereof (10, 15...). This is because in such a case, the repetition period of the contrast interval coincides with the systematic defect generation period (or an integer multiple thereof).

  FIG. 14 is an example of an actual SEM image of the test structure according to the present invention. This photograph was taken in the vicinity of the array inspection area 19. In this example, there are two disconnected wires 36 in one wiring failure detection wiring group 15.

(4) Fourth Embodiment According to the above embodiments, defects that occur systematically can be detected efficiently and the coverage characteristics of the inspection pattern are improved. However, in the evaluation of wiring defects in a semiconductor production line, only the occurrence of accidental defects due to dust or the like may be subject to evaluation.

  In such a case, even without using a complicated test structure as shown in FIG. 1, the test structure as shown in FIG. 4 can inspect a wiring defect with improved coverage characteristics of the inspection pattern. .

  In this test structure, the wiring group 15 whose pitch is gradually increased is regularly repeated. Since the pitch is gradually increased, the wiring group 15 is effective for defects of different sizes. Therefore, the test structure of FIG. 4 is composed of only one type of wiring pattern, and the coverage of the inspection pattern is 100%.

  The inspection of the wiring defect using this test structure is performed using the voltage contrast method and the array inspection method as in the third embodiment. However, the number of wirings included in the comparison section 23 is as shown in FIG. And the same number as the number of wiring groups 15 (or an integer multiple thereof). Even in this way, an accidental wiring failure based on a defect due to dust or the like can be detected.

  The present invention can be used in the semiconductor manufacturing industry. It can also be used in a test and inspection industry that inspects a semiconductor device in response to a request from a person who operates a semiconductor manufacturing industry.

FIG. 3 is a plan view of a test structure for detecting a wiring defect according to the first embodiment. Sectional drawing of the test structure for wiring defect detection by 1st Embodiment A plan view of a first test structure first devised by the present inventor to detect systematic defects A plan view of a second test structure first devised by the inventor to detect systematic defects. Schematic diagram showing the case where systematic defects occur in the test structure of FIG. SEM image of array inspection area of test structure shown in FIG. SEM image when systematic defect 8 occurs in the test structure shown in FIG. SEM image used for array inspection (SEM image of array inspection region 19) Plan view of a test structure for detecting a wiring defect according to the second embodiment Sectional drawing of the test structure for wiring defect detection by 2nd Embodiment Schematic of the inspection device used in the third embodiment Flow chart of the inspection program used in the third embodiment Plan view of a test structure used in the third embodiment SEM image (photo) of test structure according to the present invention Plan view of a test structure for a conventional voltage contrast method Sectional view of a test structure for a conventional voltage contrast method Conceptual diagram when a defect occurs in a conventional test structure Schematic diagram when array inspection is performed on a conventional test structure

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Wiring 2 Insulating film 3 Semiconductor substrate 8 Defect 13 Wiring defect detection wiring 15 Wiring defect detection wiring group 16 Array inspection wiring 19 Array inspection area 23 Contrast section 40 Wiring defect detection area

Claims (4)

An insulating film formed on a semiconductor substrate, in test structure used to interconnect defect detection by voltage contrast method and a plurality of wirings disposed on the insulating film,
Wherein a plurality of wiring defect detecting lines arranged in a predetermined direction on an insulating film, wiring pitch or width of the wiring defect detecting wiring between the wiring defect detecting wiring is formed so as to differ from each other A wiring defect detection area in which the defect detection wiring group is repeatedly arranged in a predetermined direction at a constant cycle;
The wiring defect detection wiring is formed by extending the wiring defect detection wiring, and the number does not match an integer multiple (excluding 0) of the number of wiring defect detection wirings included in the wiring defect detection wiring group. A test structure for detecting a wiring defect, comprising an array inspection region in which a comparison section including the inspection wiring is repeatedly arranged in a predetermined direction at a constant period. Secondary electron images of the plurality of conductors caused by the difference in potential generated according to the charge amount by irradiating and charging a plurality of conductors arranged on the insulating film with a particle beam capable of generating secondary electrons. In the method of detecting a wiring defect that detects an electrical defect of the conductor using the difference in strength of
The test structure according to claim 1 is used as a test object, and a first step of taking a secondary electron image of the array inspection region is compared between the adjacent comparison sections. And a second step of detecting an electrical defect generated in the wiring failure detection wiring. An insulating film formed on a semiconductor substrate, in test structure used to interconnect defect detection by voltage contrast method and a plurality of wirings disposed on the insulating film,
Wherein on the insulating film a plurality of wiring defect detecting lines arranged in a predetermined direction, a wiring defect detecting wire group pitch is different by Uni formed mutually between the wiring defect detecting wiring, predetermined A test structure for detecting defective wiring, which is repeatedly arranged in a direction at a constant cycle. Secondary electron images of the plurality of conductors caused by the difference in potential generated according to the charge amount by irradiating and charging a plurality of conductors arranged on the insulating film with a particle beam capable of generating secondary electrons. In the method of detecting a wiring defect that detects an electrical defect of the conductor using the difference in strength of
A first step of taking a secondary electron image of an end of the plurality of wiring defect detection wirings, using the test structure according to claim 3 as a test target;
A second step of dividing the secondary electron image into a plurality of contrast sections having wirings equal to or an integral multiple of the number of wiring failure detection wirings constituting the wiring failure detection wiring group;
And a third step of detecting an electrical defect occurring in the wiring defect detection wiring by comparing the intensity of the secondary electron image between the adjacent contrast sections. Detection method.

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