JP2005347773A5 - - Google Patents

Description

Semiconductor device inspection method and inspection device, and semiconductor device manufacturing method

  The present invention relates to a sample inspection apparatus, a method and an apparatus for manufacturing a substrate having a fine circuit pattern such as a semiconductor device, and further, an evaluation technique of electrical characteristics by a wafer in the course of manufacturing a semiconductor device and an electrical characteristic of a wafer that has completed the manufacturing process. In particular, the present invention relates to a technique for identifying an electrical failure portion of a wiring.

  A semiconductor wafer inspection will be described as an example.

  In a semiconductor device, a transistor, a capacitor, and a wiring are sequentially formed. Since the wiring process is often formed after transistors and capacitors are formed, and since the wiring is directly connected to the quality of electrical characteristics, the quality of the semiconductor device is greatly affected. That is, if a defect occurs in the wiring after all the transistors and capacitors are formed, a large loss occurs in manufacturing the semiconductor device. Therefore, it is very important that the manufacturing process of the wiring process can stably manufacture good products.

  Since the completeness of the above wiring process is important, in the semiconductor manufacturing line, a test pattern for early evaluation of only the wiring process part is manufactured at the product development stage, the quality of the wiring process is judged, and the process conditions are determined. Optimize. Such a test pattern for the wiring process is hereinafter referred to as a wiring TEG (Test Element Group). Even after the process optimization is completed, the wiring TEG is periodically manufactured and the quality is judged to grasp the fluctuation of the process state.

  An example of the wiring TEG will be briefly described below. Details are described in the Examples. For the wiring TEG, an insulating layer, for example, a SiO2 film is formed on a Si substrate, and a wiring pattern is formed thereon. The wiring pattern may be a single layer or a multilayer. For example, in the wiring TEG for evaluating the disconnection defect of the wiring, a long linear pattern is formed on the insulating layer, and a probe contact pad pattern is formed at both ends of the wiring. A probe is brought into contact with the pads at both ends of the wiring, a predetermined voltage is applied between the probes, the resistance of the wiring is measured, and the quality is compared with a desired resistance value. When the resistance between the wirings thus measured is higher than the desired resistance, it is determined that there is a disconnection defect between the wirings.

  A prober is used as a means for measuring the resistance between wirings. As described above, after the wiring TEG is formed, the resistance between the wirings is measured with a probe, whereby the presence or absence of a defect can be detected for each unit of the wiring TEG pattern based on the level of the resistance.

  A method is known in which when a defect occurs, the surface of the wiring pattern in which the defect has occurred is observed with an optical microscope to check for the presence of foreign matter or shape defects. However, there are many cases where a foreign matter or shape defect that can be observed on the surface and electrical characteristics such as wiring resistance do not correspond one-on-one, and this does not lead to a countermeasure for the true cause of the defect. In addition, in the case of defects such as internal defects or shorts, disconnections, or voids, the surface shape is often normal and defects are generated inside, and cannot be recognized by observation with an optical microscope. Even in normal SEM observation, since the internal defect cannot be recognized, it is difficult to grasp the cause of the defect, and it takes a long time to take countermeasures.

  As a technique for identifying such a wiring internal defect occurrence location using an electron beam, Japanese Patent Laid-Open No. 6-326165 (Patent Document 1) measures the ratio of the amount of secondary electrons generated on the surface and the substrate absorption current. The method of evaluating by doing is described.

  Japanese Patent Application Laid-Open No. 11-87451 (Patent Document 2) describes a method for evaluating characteristics by measuring a substrate absorption current via a wiring connected to a pn junction.

  Furthermore, Japanese Patent Laid-Open No. 2000-36525 (Patent Document 3) describes a method for inspecting an electrical defect of a semiconductor circuit using a potential contrast while applying a pulsed potential to a semiconductor power line. .

  In JP-A-6-326165 and JP-A-11-87451, a method for evaluating the presence or absence of defects by measuring the substrate absorption current is described. However, since the substrate current is weak, the electron beam It is necessary to scan at a low scanning speed, and it is not possible to evaluate a wide area at high speed. Moreover, there is no description about the method for inspecting the wiring pattern insulated from the substrate as described above.

Next, Japanese Patent Laid-Open No. 2000-36525 describes a failure analysis method using an EB tester that determines the content of a defect from a secondary electron image while inputting a pulse generator signal to a power supply line or a ground line. However, there is no description about the method for inspecting the wiring pattern insulated from the substrate as described above.
JP-A-6-326165 Japanese Patent Laid-Open No. 11-87451 JP 2000-36525 A

  As described in the above prior art, using a wiring TEG for evaluating a wiring process in a short period of time, in order to identify a defect occurrence location in a wafer formed with a wiring process insulated from the substrate in the shape of a Si substrate There was only an observation method using an optical microscope or a normal SEM.

  However, observation with an optical microscope or SEM cannot identify the cause of the failure because it is difficult to cope with an electrical conduction state such as a disconnection failure, high resistance failure, or short failure. It took time from the occurrence of defects to the implementation of countermeasures. In addition, observation with an optical microscope or SEM cannot recognize the above-mentioned poor electrical continuity, particularly defects that occur not on the surface, but cannot identify the location and cause of failure. Since there is no other way than to repeat the evaluation of manufacturing the wiring TEG by changing the process conditions and measuring the electrical characteristics, it takes a lot of time for several months to take measures, and delays the development period of semiconductor development, especially the wiring process It was a factor.

  In addition, in the inspection method of irradiating a transistor with an electron beam and measuring the amount of leakage with the absorbed current, the amount of absorbed current is very weak, so it takes an enormous amount of time to measure one point, and a wide area. There was a problem that it was inappropriate for the inspection to find the defective part from the inside. Further, the wiring TEG insulated from the substrate has a problem that the absorption current does not flow through the substrate, and thus evaluation by the substrate current measurement is impossible.

The object of the present invention is to solve the above-mentioned problems, provide an inspection technique for identifying a defective part generated on the wiring TEG, and also detect internal or lower layer disconnection, high resistance, short circuit, etc. that cannot be identified by the surface shape. Ru Ah to provide an inspection method of identifying a defective portion on the electrical properties.

  Another object of the present invention is to provide a method for searching and identifying a defective part at a high speed at the wafer level, thereby easily analyzing the cause of the defect that could not be grasped conventionally and taking measures at an early stage. It is in.

Furthermore, another object of the present invention, and the proportion of highly fatal defects by evaluation to determine the breakdown of the defect content, provides a technique to make a yield prediction by applying the wiring process using the process There is.

Further, another object of the present invention is to optimize the wiring process and manage the process by applying these technologies to various kinds of multi-step semiconductor devices and other fine circuit patterns at an early stage. An object of the present invention is to provide an inspection method and apparatus, and a semiconductor device manufacturing method, which are reflected in the manufacturing conditions and contribute to increasing the reliability of the semiconductor device and the like and reducing the defect rate.

  As a method for inspecting a semiconductor device with an electron beam, fine shape observation and line width measurement are performed by narrowing down an electron beam of a minute current and irradiating the wafer to form an image like a length measuring SEM, for example. Although there is a method, even if the shape can be observed, it is impossible to detect a defect such as a breakage in the wiring or in the lower layer.

  According to the study by the present inventors, in order to identify a defect occurrence location using an electron beam in the wiring TEG, first, an insulating layer is formed on the Si substrate, and a wafer on which the wiring TEG pattern is formed is formed. It is possible to identify a defective portion by measuring the current flowing through the probe while making the probe contact the pads on both ends or one side of the wiring and scanning the electron beam on the pattern to be inspected. I found out that I can do it.

Since the wiring is insulated from the substrate, a part of the electron beam irradiated to the wiring becomes secondary electrons, and the rest flows as electric current on the wiring. When an electron beam is applied to the wiring that is connected to or connected to the wiring pad that is in contact with the probe , a current flows through the probe as described above. No current flows through the probe even when the previous wiring is irradiated with an electron beam. Therefore, the disconnection location can be specified by specifying the location where the current stops flowing.

In the conventional technology, evaluation was made based on the absorption current image formed by measuring the current flowing through the Si substrate. However, because the resistivity of the Si substrate is high, the current flowing through the substrate is compared with the irradiated beam current. It was extremely small. In a normal SEM, the electron beam current is several pA to several tens pA, so that it is difficult to measure current when the current is very small. When this substrate current is imaged, the image has a large signal noise and a poor S / N ratio. For this reason, scanning an electron beam over several screens for several tens of seconds, increasing the amount of signal over time, and adding them to improve the S / N ratio. Therefore, it is difficult to search for a defect occurrence place at high speed.

Further, the wiring pattern insulated from the Si substrate cannot be measured because the substrate current does not flow. However, the wiring TEG usually forms an insulating film on a Si substrate and forms a wiring pattern thereon. The inventors have found that in such a wiring TEG, it is necessary to measure the current flowing on the surface of the wiring.

  Originally, in the wiring TEG, pads are arranged at both ends of the wiring pattern, and an ordinary prober measures the resistance by bringing a probe into contact with the pads at both ends, and determines the quality of the wiring pattern based on the resistance value. . The present inventors have found that a current flows through the wiring more efficiently and with a lower resistance than the Si substrate by irradiating the wiring with an electron beam with a probe in contact with one or both of the pads. .

For example, a probe is brought into contact with the pads at both ends of the wiring, one probe is used to make a ground potential, and the current is measured with the other probe. When a disconnection failure occurs in the middle of the wiring, when the electron beam is applied to the wiring on the side where the current is measured, the current flows and the ground potential is When the wiring is irradiated with an electron beam, no current flows. When the signal on the side where the current is measured, that is, the current is converted into a voltage, amplified, and displayed as an image signal in synchronization with the signal scanning the electron beam, the search is performed in the same manner as the secondary electron image. An image of the current flowing through the needle can be displayed. The present inventors have found that the location where the disconnection occurs can be specified by the contrast of the probe current image.

  The inventors of the present invention examined conditions for irradiating an electron beam in order to realize the above-described defective portion specifying inspection. As a result, if the electron beam current applied to the wiring pattern is set to 100 pA or more, the current flowing through the probe can be converted into a voltage signal and amplified at the same speed as the normal SEM scanning speed. I found.

  Further, when a defect occurrence location is searched after the probe contacts the wiring pad by the above method, the probe needs to remain in contact with the wafer or chip to be inspected. The scanning deflection range of the electron beam is about several hundred μm, and it is difficult to search the entire TEG pattern.

  Therefore, a unit for holding the probe was installed on the sample stage, that is, the XY stage. This allows the probe to move with the sample when the stage is moved when searching for a defect occurrence location, so that the probe remains in contact with the wiring pad over a wide range, for example, several centimeters. It becomes possible to search for a defective portion.

  In addition, for easy and high-speed search, the secondary electron signal and the current signal flowing through the probe can be arbitrarily switched by selecting switches, buttons, or items on the screen for the input signal to the image monitor. I did it. As a result, the secondary electron image is observed until the probe contacts the pad, and whether or not the probe is in contact is monitored by monitoring the probe current while irradiating the electron beam, and whether the current is also flowing through the wiring is simplified. Can be discriminated. In addition, when searching for a defect occurrence location such as disconnection and specifying the position, by switching the defect location to a secondary electron image and observing, the cause of the defect is due to a shape defect or foreign matter that can be observed from the surface, It is possible to determine whether it is an internal defect.

  In this way, an inspection for identifying a defective portion is performed, but the probe can be measured by contacting a pad on one side of the wiring TEG pattern, and contacting one end and grounding one side. It is also possible to measure the current with the other probe.

For example, when the resistance between the wirings TEG is slightly higher than the normal part and the high resistance is defective, the wirings are not completely disconnected, and a leakage current is generated between the wirings. In such cases, it is possible to suppress an increase in leakage current due to charging by electron beam irradiation by using a method in which a probe is brought into contact with both ends of the wiring, one side is grounded, and the current is measured with the other probe. It has been found that high resistance defects can be revealed with high sensitivity.

By carrying out these inspection methods and using an inspection apparatus equipped with these functions, defects that occur in the wiring TEG and cannot be identified only by the surface shape can be easily found at the wafer or chip level, for example, damascene. by using the above-described inspection method as failure cause determining means when the condition is out of the process, the cause of early failure becomes possible to shorten the time to process optimization take measures for grasp. The contents examined in order to realize such an inspection method are described below.

The first means is to bring a probe into contact with one or both sides of the pad at both ends of the wiring TEG pattern insulated from the substrate, and in this state irradiate the wiring pattern to be inspected with both or one of the two. The current flowing through the probe was measured. As a result, when an electron beam is applied to the wiring that is connected to the pad that is in contact with the probe that is measuring the current, current flows. Since the current does not flow even when the electron beam is irradiated, the defective portion can be specified. Since the wiring pattern has a high conductivity, the current can be measured more efficiently than the Si substrate current. For this reason, it is possible to measure the current at a beam scanning speed of about 1 MHz, for example, equivalent to acquiring a normal SEM image.

  The second means converts the current flowing through the probe into a voltage when the electron beam is irradiated onto the wiring pattern to be inspected, amplifies it, converts the voltage signal into a digital value in synchronization with the scanning signal, and outputs an image. It is to display as the brightness. As a result, the current value of the probe at the same location can be observed as a two-dimensional image by the same operation as when acquiring a secondary electron image in SEM. As described in the first means, since the location where a defect has occurred can be identified without current flowing / flowing, the image becomes bright when flowing, and dark when not flowing. Therefore, it is possible to easily identify the defect occurrence location.

The third means is that the unit for holding the probe is arranged on the sample stage or the XY stage on which the sample stage is placed. The unit that holds the probe has a mechanism that adjusts the position of the probe and a mechanism that fixes the probe. As a result, the probe is moved above the desired wiring or pad, and the vertical position is adjusted so as to contact the pad, and is fixed after the contact. After the probe contacts and is fixed to the pad, as described in the second means, the current of the probe is displayed and observed while irradiating the inspection target wiring pattern with the electron beam, and the change in brightness is observed. Search for occurrences. When the stage is moved for searching, the entire probe unit moves together with the sample, so that a wide range can be searched while maintaining the state in contact with the wiring.

  The fourth means is that the current of the irradiated electron beam is set to 100 pA or more. As a result, a sufficient signal can be obtained when imaging the current flowing through the probe described in the second means, so that the image can be imaged without extremely slowing down the scanning speed of the electron beam. It became possible. As a result, the current image of the probe can be acquired at the same speed as when observing a normal secondary electron image. It became possible to explore.

  In the fifth means, the probe is brought into contact with both ends of the wiring, and the current of the other probe is measured while grounding or applying a potential to the wiring on one side using the probe on one side. That is. Thereby, the influence of charging due to the irradiation of the electron beam can be suppressed, the contrast in the probe current image can be improved with respect to the wiring on both sides of the defective portion, and the defective portion can be identified with high sensitivity.

  The sixth means is that the inspection by the above means is applied when setting the semiconductor wiring process manufacturing conditions, and when a resistance defect occurs in the wiring TEG, the above means is inspected and the defective part is immediately identified. is there. As a result, the cause can be grasped at an early stage by analyzing the cross section of the defective portion without changing and dividing the process conditions for evaluation.

  With the various means described above, it is possible to quickly identify defective locations such as disconnection and high resistance that cannot be identified by shape in semiconductor devices, especially wiring TEG, with simple operations similar to SEM observation. Furthermore, by analyzing the location specified by this inspection, it becomes possible to immediately grasp the cause of the occurrence of a true defect. Further, in the semiconductor wiring process, since the cause of the true defect can be grasped at an early stage, appropriate measures can be taken at an early stage, and conditions can be optimized in an early cycle. As a result, it is possible to take measures against the cause of defects in the manufacturing process of various substrates including a semiconductor device at a higher speed and with higher accuracy than the conventional method and the conventional apparatus, and at the same time, it is possible to secure a high yield, that is, a non-defective product rate, and to generate defects It is possible to shorten TAT from detection to countermeasure.

  A typical effect obtained by the present invention will be briefly described below.

  In the conventional method, the wiring TEG is manufactured, the resistance is measured with a prober, and the normal pattern and the abnormal pattern are identified by the resistance value of the wiring. However, although it is possible to judge pass / fail by resistance value, it was difficult to determine the cause of the failure by performing analysis etc. because the actual failure location could not be specified. Since it was handled by methods such as manufacturing and measuring the resistance, it took several months to take measures against the failure.

  On the other hand, by using the inspection method of the present invention after the wiring TEG is manufactured and the pass / fail judgment is made by the prober resistance measurement, the defective portion can be immediately identified and analyzed.

Also, if possible identified broken portion or a high resistance defect portion, because it also supports the evaluation of the surface shape by simultaneously secondary electron image, it was possible to greatly reduce the time required for failure analysis.

  As a result, when optimizing the process conditions, it is possible to immediately determine the quality of the process and efficiently analyze and identify the problem process, so that the efficiency of the countermeasure is greatly improved. The development period and yield improvement period can be greatly shortened.

Various defective portion generated in the wiring TEG These effects can be identified at high speed, it is possible to analyze with high efficiency, ing to the failure cause That problem can be grasped accurately immediately. As a result, it is possible to take an abnormality countermeasure process promptly in the wiring manufacturing process, and as a result, it is possible to reduce the defect rate of semiconductor devices and other substrates and increase productivity.

  Also, by applying the above inspection, the wiring process can reduce defects quickly and efficiently, so the yield of the entire semiconductor process can be improved, and furthermore, problems can be detected quickly, so compared with the conventional method. Thus, measures can be taken at an early stage, and a large amount of defects can be prevented, so that the development period can be greatly shortened.

  As a result, the occurrence of defects itself can be reduced, so that the reliability of semiconductor devices and the like can be improved, the development efficiency of new products and the like can be improved, and the manufacturing cost can be reduced.

  Hereinafter, an example of an inspection method and an apparatus according to an embodiment of the present invention will be described in detail with reference to the drawings.

(Example 1)
In this embodiment, an inspection method and an inspection apparatus for specifying a defect occurrence point in a wiring TEG composed of two wiring layers will be described.

First, FIG. 1 shows the configuration of a semiconductor device inspection apparatus according to this embodiment. The semiconductor device inspection device includes an electron gun 1, a condenser lens 2, a blanking control electrode 3, a movable diaphragm 4, a deflector 5, an objective lens 6, a secondary electron detector 7, a sample stage 8, an XY stage 9, and a probe 10, probe holding unit 11, preamplifier 12, amplifier 13, signal input switching switch 14, video board 15, SEM display 16, personal computer monitor 17, sample exchange chamber 18, and vacuum exhaust system 19.

  FIG. 2 shows an enlarged view of the sample 20, the probe 10, and the probe current signal detection system in FIG.

The timing of irradiating the sample 20 with the electron beam 21 is controlled by the blanking control electrode 3, and an unnecessary electron beam is not irradiated to the sample 20 at a time other than the time when the inspection is performed. When the sample 20 is irradiated with the electron beam 21, the deflector 5 controls the scanning speed and the scanning area. The irradiation energy of the electron beam was about 3 keV. As a result, the amount of secondary electrons generated is smaller than the amount of the electron beam 21 to be irradiated, the current flowing through the wiring pattern 22 can be increased, and at the same time, the primary electron beam is applied to the Si substrate 20 under the wiring pattern 22. It is possible to prevent 21 from being transmitted. Further, the current of the electron beam 21 to be irradiated is 100 pA or more, and is set to 1 to 5 nA here. A part of the irradiating electron beam 21 flows into the wiring pattern 22, and this is measured from the probe. In order to measure the current while scanning the electron beam at high speed, it is desirable that the beam current is large.

  The probe 10 is previously brought into contact with the pad on the wiring pattern 22 on the surface of the sample 20, and in this state, the electron beam 21 is irradiated to a desired region including the wiring pattern 22 in contact with the probe 10 of the sample 20. . By irradiating the electron beam 21, secondary electrons 25 are generated from the surface, and at the same time, a current flows through the wiring pattern 22. This current is transmitted through the probe 10 that is in contact with the wiring pattern 22, converted into a voltage signal by the preamplifier 12, and amplified at the same time, goes out of the vacuum chamber through the feedthrough 24, and is further amplified by the amplifier 13. After that, it is input to the video board 15. Then, it is displayed on the display 16 or the personal computer monitor 17.

Normally, when displaying an electron beam image, the signal detected by the secondary electron detector 7 is amplified in the middle, converted into a digital signal via the video board 15, and displayed on the display 16 or the personal computer monitor 17. it is although, switch 14 for switching the signal flowing in the secondary electron signal and the probe in this device to arbitrarily switch switch is disposed in front, whether to display signal of the video board 15 Can be selected.

  The video board 15 converts the signal in synchronization with the electron beam scanning. Therefore, it is possible to alternately observe the signal of the secondary electrons 25, that is, the SEM image and the current signal flowing through the probe 10, that is, the probe current image, while scanning the same location with the electron beam 21. Here, as the preamplifier 12 and the amplifier 13 for amplifying the signal flowing through the probe 10, high-speed amplifiers having a response speed of 400 KHz or more are used. As a result, the signal can be amplified at a speed equivalent to the scanning speed of a normal SEM, and a probe current image can be displayed.

  As shown in FIG. 2, when there is a portion 23 where the wiring is disconnected in any portion of the wiring pattern 22, the region irradiated with the electron beam 21 is on the side where the probe 10 is in contact with the disconnected portion 23. In this case, a current flows through the probe 10, but even if the electron beam 21 is irradiated on the opposite side, the current does not flow through the probe 10 because the resistance of the broken portion 23 is high. For this reason, a region where the signal is large, that is, a region where the image is bright and a region where there is almost no signal, that is, a region where the image is dark, are generated at the disconnection point 23 as a boundary. On the other hand, in the secondary electron signal, secondary electrons are generated from any region of the surface, so that it is difficult to change the brightness and darkness compared to the probe current image, and it is difficult to specify the disconnection point 23. .

FIG. 3 shows an inspection flow. The sample 20 to be inspected has a structure shown in FIG. It is a structure generally called a contact chain in which two layers of isolated wirings are long connected by a contact hole. After the contact chain wiring is formed (26 in FIG. 3), first, resistances at both ends of the wiring are measured with a prober or a tester (27 in FIG. 3). The resistance measurement result is output as a resistance value data sheet 37 as shown in FIG. For example, the resistance value 38 of a normal pattern and the resistance value 39 of a pattern in which a disconnection failure or the like has occurred can be output in different colors. The sample 20 to be inspected is inserted into the inspection apparatus from the sample exchange chamber 18 and placed on the sample stage 8.

Then, the probe 10 is operated from the outside as shown in FIG. 1 and FIG. 2 for a portion (resistance value 39) that seems to be a defective product having a resistance value higher than that of a normal product (resistance value 38) in FIG. Then, it is brought into contact with the wiring pattern 22 on the surface of the sample 20 (28 in FIG. 3). Then, when contacted, the region of the wiring pattern 22 is moved on the XY stage 9 while irradiating the electron beam, and the probe current image is displayed on the display 16 or the personal computer monitor 17, and the position where the brightness of the image changes is displayed. Search (29 in FIG. 3). At this time, in order to observe a wide area, the scanning area of the electron beam 21 is wide, that is, it is more efficient to observe with a low magnification.

  When a spot where the brightness of the probe current image changes is found, the spot is moved to the center of the field of view, and the high magnification, that is, the scanning deflection width is reduced to identify the pattern in which the defect has occurred (30 in FIG. 3). Then, if necessary, the image signal to be displayed on the display 16 or the personal computer monitor 17 is switched to the secondary electron signal by the switch 14, and the SEM image is observed to observe whether there is any abnormality in the surface shape (FIG. 3 of 31).

The result of concrete implementation of this flow is shown in FIG. Here, the wiring TEG was formed using a Cu damascene process. A pattern to be inspected (resistance value 39) is selected from the data sheet 37 actually obtained by resistance measurement (27 in FIG. 3) using a prober (40 in FIG. 6). A probe current image is acquired (41 in FIG. 6). The part with light and darkness is further observed at a high magnification to identify the disconnection part (42 in FIG. 6).

  And it switches to a SEM image and observes the presence or absence of the abnormality of the surface (43 of FIG. 6). Here, it has been found that the wiring on the surface has also disappeared due to a defect called void, in which the inside of the wiring becomes hollow when Cu is embedded.

  In the SEM image, only the defective part looks dark, and it cannot be determined whether or not this causes a disconnection defect. Therefore, the above-described inspection for identifying the disconnection location by monitoring the probe current is effective.

(Example 2)
Example 2 is the same as Example 1 except that two probes are provided. FIG. 7 shows a schematic diagram when there are two probes.

A first pad 33 and a second pad 45 exist at both ends of the wiring pattern 22. The first probe 10 is brought into contact with the first pad 33, and the second probe 44 is brought into contact with the second pad 45 . The second probe 44 is grounded. Other configurations are the same as those in the first embodiment .

In this state, the wiring pattern 22 is inspected by the procedure described in the first embodiment . Since the wiring pattern 22 is floating from the sample 20 (Si substrate), it is charged by irradiating the electron beam 21 with a large current for a long time. As charging progresses, a leak current is generated at a defective portion having a high resistance. When a leak current occurs, the amount of current flowing through the probe cannot be differentiated with a defective portion as a boundary.

  Therefore, when observing the probe current image, it becomes impossible to make the brightness dark and dark with the defective portion as a boundary. Therefore, in this embodiment, the second probe 44 is brought into contact with the second pad 45 on the opposite side of the wiring and grounded so that the disconnected wiring is not charged.

  As a result, the influence of the leakage current due to charging is reduced, and more subtle resistance defects can be realized as compared with the normal pattern. For example, if the resistance of a normal contact chain wiring pattern (pattern consisting of 1 million contacts) is 10E6 [Ω], and the inspection is performed with only one probe, the location is 10E8 [Ω] However, when one side is grounded with the two probes described in this example, it is possible to identify the disconnection location for the 10E7 [Ω] location. It was.

(Example 3)
In Example 3 , the pattern to be inspected is not a contact chain structure but a long wiring structure. FIG. 8 shows the configuration of the wiring pattern. The inspection method is the same as in Example 1 or Example 2 . In the contact chain structure of FIG. 4, it was possible to confirm the continuity of the contact connecting the two-layer wiring, but in this embodiment, it is possible to inspect the resistance of the wiring itself and the presence or absence of the disconnection.

Example 4
Example 4 is the configuration of the two probes described in Example 2 , and applies a potential to the second probe. It is possible to apply a positive or negative potential arbitrarily.

When the surface of the sample 20 is irradiated with a high-current electron beam 21 for a long time or many times, not only the wiring but also the silicon oxide film on the surface is charged. As charging progresses, charged charges accumulated in the silicon oxide film may flow into the wiring. Therefore, as described in the second embodiment, an extra current flows through the wiring, and as a result, it becomes difficult to make a difference in the amount of current with the disconnected portion as a boundary.

  That is, the difference between the brightness and darkness of the probe current image is difficult to occur with the disconnection point as a boundary, and it becomes difficult to specify the defective point. Therefore, in this embodiment, the probe current is measured in a state where a potential is applied so that the wiring has a potential equivalent to that of the surrounding silicon oxide film. As a result, it became possible to reveal the defective portion even in the sample where it was difficult to reveal the defective portion due to charging.

(Example 5)
In the present embodiment 5 will be described the case of applying the above test method the semiconductor manufacturing method.

FIG. 9 shows a flow of manufacturing the Cu damascene wiring TEG in the semiconductor manufacturing process. A silicon oxide film 46 is formed on the Si substrate 47 , and a groove pattern is formed in the silicon oxide film 46 . A Cu layer 48 is formed thereon by plating, and then the surface is polished and flattened. Thereafter, a silicon oxide film 46 is further formed, a hole pattern and a groove pattern are formed thereon, and thereafter a Cu layer 48 is similarly formed by plating, and then the surface is polished.

  As a result, a two-layer wiring pattern and a contact connecting it can be formed. When forming the wiring TEG by this Cu damascene process, defects such as conduction failure 49 during hole formation or embedding failure 50 during Cu layer formation are likely to occur, and these cannot be detected by surface observation. is there.

  FIG. 10 shows a flow of a defect analysis method according to the conventional method. In the conventional method, after the wiring TEG is formed (51 in FIG. 10), the resistance is measured by probe inspection (52 in FIG. 10), the defect occurrence point is selected (53 in FIG. 10), and then the optical microscope or electron microscope is used. The surface was observed (54 in FIG. 10), and it was examined whether there was an abnormality on the surface (55 in FIG. 10). If there was, the FIB cross-section was analyzed (56 in FIG. 10).

  However, as shown in the flow of FIG. 9, many defects generated inside the Cu damascene wiring also occur, and it was difficult to identify a defective portion by surface shape observation. Therefore, if the surface shape abnormality cannot be observed, the analysis is abandoned, and even if an abnormality such as a foreign object is found and the FIB cross-section analysis is performed, the correspondence with the actual disconnection failure point is poor and the analysis time is reduced. In short, the cause of the failure could not be determined.

  On the other hand, when the inspection of the present invention is executed, disconnection and high resistance failure can be reliably detected. In addition, since the presence or absence of surface shape abnormality can be confirmed by observing the surface of the same location after identifying the disconnection location, it is possible to immediately determine whether the failure is caused by the surface shape abnormality, internal continuity failure 49 or embedding failure 50 it can.

Therefore, by applying the inspection method and apparatus of the present invention , it becomes possible to immediately grasp the presence or absence of defects due to defects in the manufacturing conditions of the wiring pattern, so that a large number of defects can be prevented in advance. .

In addition, by applying the inspection method and apparatus of the present invention , it becomes possible to determine the manufacturing process conditions of the wafer to be inspected efficiently and accurately in a short time, and as a result, a more appropriate process can be applied to the manufacturing process. Reliability can be improved.

  In addition, since the inspection of the present invention is automated, the occurrence of defects can be detected at an early stage, so that the productivity of the semiconductor device can be increased.

As described above, the configuration of the representative apparatus and the inspection method of the present invention have been described with respect to the specific inspection flow, the action of each part, the flow for determining the inspection conditions, and the embodiment of the inspection. An inspection method and an inspection apparatus that combine a plurality of features described in the claims without departing from the scope of the invention are also possible.

It is a figure which shows the structure of a semiconductor inspection apparatus. It is an expansion conceptual diagram of an inspection device. It is a figure which shows a test | inspection flow. It is a figure which shows the structure of a wiring pattern. It is a figure which shows a resistance measurement result. It is a figure which shows the inspection method. It is a figure which shows the structure in the case of two probes. It is a figure which shows the structure of the test pattern for a disconnection test | inspection. It is a figure which shows the manufacturing process flow of a wiring test pattern. It is a figure which shows the conventional inspection method.

Explanation of symbols

1 ... electron gun, 2 ... condenser lens, 3 ... blanking control electrode, 4 ... movable diaphragm, 5 ... deflector, 6 ... objective lens, 7 ... secondary electron detector, 8 ... sample stage, 9 ... XY stage, 10 ... 1st probe, 11 ... Probe holding unit, 12 ... Preamplifier, 13 ... Amplifier, 14 ... Signal selector switch, 15 ... Video board, 16 ... SEM display, 17 ... PC monitor , 18 ... Sample exchange room, 19 ... Vacuum exhaust system, 20 ... Sample, 21 ... Electron beam, 22 ... Wiring pattern, 23 ... Defect occurrence place, 24 ... Feedthrough, 25 ... Secondary electron, 26 ... Wiring TEG production, 27 ... Resistance measurement, 28 ... Probe contact, 29 ... Fault location search, 30 ... Fault location identification, 31 ... SEM image observation, 32 ... Analysis, 33 ... Pad, 34 ... First layer wiring, 35 ... Contact, 36 ... Second layer Wiring, 37 ... resistance measurement result, 38 ... normal part resistance, 39 ... defective part resistance, 40 ... inspection pattern selection, 41 ... search at low magnification, 42 Broken point located at the height ratio, shape observation by 43 ... SEM, 44 ... second probe, 45 ... second pad, 46 ... silicon oxide film, 47 ... silicon substrate, 48 ... Cu layer, 49 ... conductive failure, 50 ... embedding failure, 51 ... wiring test pattern production, 52 ... resistance measurement, 53 ... defect generation pattern selection, 54 ... surface observation, 55 ... abnormality determination, 56 ... analysis.

Claims (8)

A semiconductor device in which a wiring pattern is formed,
Irradiating and scanning the surface of the semiconductor substrate with an electron beam;
Detecting a signal secondarily generated from the semiconductor substrate by an electron beam;
Imaging and displaying the detected signal;
A step of bringing the probe into contact with the wiring;
Measuring the current flowing through the probe;
Converting the measured current into a voltage;
And a step of imaging and displaying the converted voltage value in synchronization with scanning of an electron beam . In the inspection method of the semiconductor device according to claim 1,
The step of imaging and displaying a signal based on the current flowing through the probe includes a step of identifying an abnormal portion of the resistance of the wiring by a change in brightness of the image. An electron source ,
A deflector for scanning an electron beam;
A condenser lens and an objective lens for focusing the electron beam;
A sample stage for placing a sample to be inspected;
A stage for moving the position of the sample to be inspected;
A detector for detecting a secondarily generated signal;
A probe in contact with the surface of the sample to be inspected;
A holding drive unit for holding and adjusting the position of the probe;
An amplifier that amplifies the current of the electron beam absorbed in the sample to be detected, which is detected by the probe;
A monitor for imaging and displaying the detected secondarily generated signal or the current flowing through the probe;
An operation unit and a control unit;
With
An inspection apparatus for a semiconductor device, which has a function of identifying defects present in the inspected sample by the imaged current. The inspection apparatus for a semiconductor device according to claim 3,
An inspection apparatus for a semiconductor device, comprising a function of setting an electron beam current applied to the sample to be inspected in a range of 100 pA to 50 nA . The inspection apparatus for a semiconductor device according to claim 3,
It has a function of simultaneously displaying a signal based on the amount of current flowing through the probe and a signal secondarily generated by electron beam irradiation on the monitor, or a function of switching and displaying either one of the signals. Semiconductor device inspection equipment . A method of manufacturing a semiconductor device by inspecting a circuit pattern formed by forming a wiring pattern on a semiconductor substrate,
Irradiating and scanning the surface of the semiconductor substrate with an electron beam;
Detecting a signal secondarily generated from the semiconductor substrate by an electron beam;
Imaging and displaying the detected signal in synchronization with scanning of an electron beam;
A step of bringing the probe into contact with the wiring;
Measuring the current flowing through the probe;
Converting the measured current into a voltage;
And a step of imaging and displaying the converted voltage value in synchronization with scanning of an electron beam . An electron source,
A deflector for scanning an electron beam;
A condenser lens and an objective lens for focusing the electron beam;
A sample stage for placing a sample to be inspected;
A stage for moving the position of the sample to be inspected;
A detector for detecting a secondarily generated signal;
A probe in contact with the surface of the sample to be inspected;
A holding drive unit for holding and adjusting the position of the probe;
An amplifier for amplifying the current of the electron beam absorbed by the sample to be detected detected by the probe;
A monitor for imaging and displaying the detected secondarily generated signal or the current flowing through the probe;
An operation unit and a control unit;
With
An inspection apparatus for a semiconductor device, wherein a first stage portion of the amplifier is installed in a vacuum chamber . Creating a test element pattern for wiring;
Measuring the resistance value of the test element pattern using a prober;
Selecting a defective pattern among the test element patterns according to the resistance value ;
Bringing a probe into contact with the pad portion of the defective pattern in a vacuum chamber;
Irradiating an electron beam to the defective pattern from the probe to detect the absorbed current to form a two-dimensional image;
Identifying a defect position in the defective pattern from the two-dimensional image;
Exposing or cutting out the region containing the defect location with a focused ion beam or mechanical polishing or cutting means;
Observing the exposed or cut-out portion with a scanning electron microscope or a transmission electron microscope;
A method for manufacturing a semiconductor device, comprising: