JP2002203882A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve testing efficiency using a TEG, resulting in increasing a yield. SOLUTION: In order to achieve the above mentioned objective, the method of this invention comprises testing a first interconnection arranged on an insulation film formed on a substrate and a second interconnection electrically connected to the substrate and arranged on said insulation film and controllably manufacturing the electronic device utilizing the test result, and further comprises the steps of testing whether the first interconnection is opened by measuring an electrical resistively between both ends of said interconnection and testing a short circuit between the first and second interconnections by measuring the resistively between the first interconnection and the substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a semiconductor device,
The present invention relates to a technique for inspecting and manufacturing electronic devices such as electric circuit boards and CCD elements.

[0002]

2. Description of the Related Art In recent years, shortening the product development period has become an essential requirement in order to enhance the market competitiveness of products. However, it takes several tens of days from the line introduction to the electrical characteristic inspection at the time of product completion to judge a good product or a defective product, and it is too late to take measures after waiting for the result of the electrical characteristic inspection.

In order to solve this problem, in product development, a common process is divided into blocks, an electrical inspection is performed in the blocks, and the result is fed back to the process, so that the process of the block can be performed early. There is a way to establish. A sample for monitoring this block is a TEG (Test Element Group).
p), short loop monitor or test structure. Hereinafter, these are collectively called TEG. An example of a TEG is “Integrat
ed Circuit Manufacturable
, IEEE PRESS, P26-P29 ".

As a technique for specifying a short-circuit position generated in a TEG, a difference in the surface potential state of a wiring pattern is detected by irradiation with a charged particle beam such as an electron beam or a focused ion beam, that is, a potential contrast is obtained. There is a technology for detecting the location of a defect. TEG using this technology
One example is the "Microelectronic Test."
Structures for Rapid Out
omated Contactless Inline
Defect Inspection, IEEE T
transactions on Semiconduc
to Manufacturing, Vol. 10,
No. 3, August, 1997 ".

[0005]

However, in the above-mentioned prior art, it is necessary to irradiate all the TEG patterns in the wafer with the charged particle beam, so that much inspection time is required. In particular, when the number of defects per wafer is small, the ratio of the normal TEG pattern occupies that much, and the time to inspect this normal TEG pattern despite the inspection to detect the abnormal part is increased. It was an inefficient work that occupied a large part.

That is, in the prior art, the TEG for efficiently specifying the short-circuited position has not been sufficiently studied, so that a great deal of time is required for inspection and analysis, and the results are not fed back to the production line. The time was delayed, and the yield could not be improved effectively. In particular, TEG for effectively using the potential contrast method has not been sufficiently studied.

Further, in the prior art, it is not possible to efficiently distinguish between a short circuit and a disconnection. As described above, much time is required for inspection and analysis, and the time required for feeding back the result to the production line is delayed. However, the yield could not be effectively improved.

[0008] It is an object of the present invention to improve the inspection efficiency using the TEG, and thereby to improve the yield.

[0009]

Means for Solving the Problems The present invention has been made in accordance with the scope of the present invention in order to achieve the above object. For example, a first invention provided on an insulating layer formed on a substrate is provided. An electronic device manufacturing method for inspecting using a wiring and a second wiring electrically connected to the substrate and provided on the insulating layer, and managing and manufacturing the electronic device using the inspection result. Measuring the electrical resistance at both ends of the first wiring to determine whether the first wiring is disconnected; and determining the electrical resistance between the first wiring and the substrate. And inspecting whether the first wiring and the second wiring are short-circuited.

In addition, the first wiring provided on the insulating layer formed on the p-type silicon substrate is electrically connected to the first wiring via the n-channel formed on the p-type silicon substrate and provided on the insulating layer. A method for manufacturing an electronic device by inspecting using the second wiring and managing the electronic device using the inspection result, wherein the method comprises: The electrical resistance is measured to check whether the first wiring and the second wiring are short-circuited.

[0011]

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a TEG structure capable of detecting not only a short-circuit failure but also a disconnection failure. Although not shown, a plurality of TEG structures are arranged together with the entire surface of the wafer or a chip as a final product, and are generally arranged together with different TEG structures for the purpose of another inspection such as contact failure.

First, the disconnection detecting wiring 1 having a desired wiring width and wiring length is arranged in a meandering manner in the first wiring layer. The stylus electrodes 3 and 3 'are arranged at both ends of the disconnection detection wiring 1, and the wiring resistance is electrically measured by these to check for disconnection.

A plurality of short-circuit detection wires 2 are arranged in parallel with the gaps between the wires in the longitudinal direction (vertical direction in FIG. 1) of the disconnection detection wires 1 so that the distance between adjacent wires becomes a desired size. To The disconnection detection wiring 1 and the short-circuit detection wiring 2 maintain electrical insulation via the interlayer insulating film 4. The plurality of short-circuit detection wirings 2 arranged are connected to n-channels 7 which are n-doped (ion-implanted) on the upper surface of the P-type silicon substrate 6 via the contact plugs 5 respectively. This plurality n
Each of the channels 7 is configured to be electrically insulated via the element isolation region 8 (may be omitted if the insulation is maintained), and the insulation of the short-circuit detection wiring 2 is maintained. The wiring interval and wiring width are typical dimensions of the wiring process to be monitored, and are set to 0.1 to 1 micrometer. In order to monitor the frequency of occurrence for each defect size, a plurality of TEGs may be provided with wirings having different wiring intervals. Hereinafter, this one TEG unit is referred to as a module.

Next, a method for detecting a short-circuit failure of a wiring will be described with reference to FIG.

First, as shown in FIG.
0 is brought into contact with the stylus electrode 3 connected to the disconnection detection wiring 1. The other is connected to a substrate electrode (not shown) in contact with the P-type silicon substrate 6, and the resistance between these is measured by the measuring instrument 11. At this time, the substrate potential is
To be higher than the potential. That is, if the substrate electrode is at the ground potential, a negative potential is applied to the probe 10, and if the probe 10 is at the ground potential, a positive potential is applied to the substrate electrode. This is because a diode function is formed by the n-channel 7 provided on the p-type silicon substrate 6. If a short-circuit exists, the n-channel of the short-circuited portion 13 is supplied from a substrate electrode (not shown) via the p-type silicon substrate 6. This is to make it easier for a current (a forward current of the diode) to flow.
When an electric current flows, the electric current leaks to the disconnection detecting wiring 1 via the contact plug 5, the short-circuit detecting wiring 2, and the short-circuit 13, and this leakage current is detected by the probe 10 which stylizes the stylus electrode 3. By doing so, a short-circuit failure is detected.

Next, a description will be given of a method of specifying a position where a TEG failure has been determined to be a short-circuit failure by the electrical inspection, that is, a method of specifying a potential contrast method.

Referring to FIG. 3, a method of detecting a short-circuited portion by the potential contrast method will be described.

A charged particle beam 20 is applied to the surface of the disconnection detecting wire 1.
Is irradiated, secondary electrons 21 are emitted from the disconnection detection wiring 1. Although the disconnection detection wiring 1 and the P-type silicon substrate 6 are electrically insulated, when the disconnection detection wiring 1 is grounded via the conductive probe 22, the ground can supply electrons. Thus, a large amount of secondary electrons 21 are emitted. The emitted secondary electrons 21 are detected by the detector 2
3, the signal processing unit 24 performs desired processing, and the display unit 25 can display the charged particle beam 20 as a scanned image having a bright contrast. On the other hand, although the short-circuit detecting wiring 2 in which no short-circuit has occurred is electrically connected to the P-type silicon substrate 6 through the contact plug 5 and the n-channel 7, the n-channel 7 is connected to the P-type silicon substrate 6. By forming this, it has diode characteristics, and electrons are less likely to be supplied to the short-circuit detection wiring 2. Therefore, the secondary electrons 2
1 is temporarily emitted, but the consumed secondary electrons 21
Since the short-circuit detecting wiring 2 is not supplied from the mold silicon substrate 6, the short-circuit detecting wiring 2 is charged, resulting in a dark contrast. Conversely, if there is a defective short-circuit 13, the wiring in which the short-circuit 13 has occurred is electrically connected to the disconnection detection wiring 1 to be approximately at the same potential, so that a large amount of secondary electrons are emitted and the disconnection detection wiring As in the case of 1, a large amount of secondary electrons are emitted, resulting in a bright contrast. Thereby, the short-circuit detection wiring 2 in which the short-circuit 13 has occurred can be made obvious.
In FIG. 3, grounding is performed via a probe in order to obtain a potential contrast image. In addition, the charging voltage may be connected to the substrate in the internal circuit of the TEG or by utilizing the volume difference (capacity difference) of the conductor 10. (The amount of secondary electrons emitted thereby) can be varied, and the disconnection position or short-circuit position can be detected as the difference in potential contrast.

Inspection methods using a basic contrast image include a line scan method and a two-dimensional scan image comparison method. The line scan method is a recognition method based on one-dimensional line scan signal processing, as shown in FIG. By detecting a change in the irregularity of the signal cycle of the potential contrast of the short-circuit detection wiring 2, the short-circuit portion is specified. A signal caused by a short circuit can be obtained by extracting a part with a disorder of this cycle as a defect from the cycle of the main component in the normal part by Fourier transform or the like, or by obtaining the cycle and amplitude of the signal waveform of the normal part in advance. The coordinates are calculated and stored, or the number of occurrences of short circuits is counted, by recognizing the amplitude abnormality of the cycle. The state of occurrence of defects can be monitored by the number, and short-circuited portions can be reviewed with an electron microscope or the like based on the coordinates of the defects.

As shown in FIG. 4B, the two-dimensional scanning image comparison method sequentially takes in two-dimensional images and compares the two-dimensional images using an image in another area to reveal a defective portion. It is to let. Specifically, a two-dimensional image obtained by observing three TEG modules is used. TE
A difference image 28 between the original image 26 of G (a) and the comparison image 27 of TEG (b) is acquired, and then the original image 26 of TEG (a) is obtained.
A difference image 28 ′ between the reference image 29 and the comparison image 29 of TEG (c) is acquired, and it is checked whether or not there is a difference image exceeding the threshold value, and which image has an abnormality, that is, which TEG has a defect (In this case, TEG (b) has a defect), and the coordinates are calculated. In order to improve the inspection sensitivity, a method in which one side of the disconnection detection wiring 1 is stuck to the stylus electrode 3 or 3 'with a probe and grounded,
Although the method of grounding in advance in the internal circuit is effective in enhancing the contrast, if the volume difference (capacity difference) between the disconnection detection wiring 1 and the short-circuit detection wiring 2 is sufficient, the stylus electrode 3 Alternatively, there is no need to probe with 3 'to ground.

In the case of detecting a disconnection defect using the present TEG structure, as shown in FIG. 5, the probe 10 is brought into contact with the stylus electrodes 3 and 3 'connected to both ends of the disconnection detection wiring 1 for measurement. The wiring resistance is measured by the measuring device 11. Disconnection 12
Is present, the resistance of the wiring becomes higher than the wiring resistance of the target specification. In addition, as shown in FIG. 6, when the disconnection portion is specified by using the potential contrast method, as described above, the charged particle beam 20 is irradiated to the module to be inspected.
A part of the disconnection detection wiring 1, that is, a portion where the disconnection 12 has occurred has dark contrast. By catching the end of the portion having the dark contrast (the broken line 12 exists at the rightmost and uppermost coordinates in FIG. 6), the position can be easily specified.

Next, a detailed failure detection method when a disconnection and a short circuit occur in one module will be described with reference to FIG.

First, although not shown, as described above,
The probe 10 is brought into contact with the stylus electrodes 3 connected to both ends of the disconnection detection wiring 1, and the resistance is measured by the measuring instrument 11 to confirm the presence of the disconnection 12. Next, as shown in FIG. 7, the resistance between the substrate electrode (not shown) and the probe 10 brought into contact with the stylus electrode 3 connected to one end of the disconnection detection wiring 1 was measured, and the short circuit 13 was detected. Check for presence. FIG.
In the example shown in (a), since the disconnection 12 has occurred, the short circuit 13 cannot be confirmed. Therefore, as shown in FIG. 7 (b), by measuring the connection between the disconnection detecting wiring 1 and the other stylus electrode 3 ', the short-circuit 1
3 can be confirmed. Thus, even when the disconnection 12 and the short circuit 13 occur simultaneously in one module, an accurate inspection can be performed.

The above procedure is summarized in FIG.

First, the resistance between the stylus electrodes 3 and 3 'connected to both ends of the disconnection detecting wiring 1 is measured to check for any disconnection (step 1). The resistance between one of the electrodes and the substrate-side electrode is measured to check for a short circuit (step 2). If a disconnection is detected in step 1, the resistance between the other of the stylus electrodes and the substrate-side electrode is measured to check for a short circuit (step 3). According to this series of procedures, it is possible to efficiently inspect each of the disconnection and the short-circuit, and the case where they are mixed.

Next, a method for specifying a short-circuited portion when a disconnection defect and a short-circuit defect occur in the same module is shown in FIG.
This will be described with reference to FIG. In addition, according to the present TEG structure, not only a short circuit but also a contrast at the time of disconnection can be obtained at the same time by using the above-described potential contrast method, so that the disconnection position and the short-circuit position can be detected simultaneously.

First, in the same manner as described above, when the charged particle beam 20 is irradiated to the module to be inspected, a part of the disconnection detecting wiring 1, that is, a portion where the disconnection 12 occurs has a dark contrast. The position can be specified. In addition, since the short-circuit 13 has been electrically connected to the disconnection detecting wire 1 at the place where the short-circuit 13 has occurred, a sufficient capacitance is obtained to provide bright contrast, and the short-circuit position can be specified.

By the way, the disconnection detecting wiring 1 which is divided by the disconnection has a contrast determined in accordance with the length of the divided wiring. If the wiring length is short, the charging voltage increases and the contrast becomes dark. If there is a short-circuited portion in this portion, the short-circuited portion is naturally assimilated with the dark contrast of the disconnection detection wiring 1, and it may be difficult to realize the short-circuited portion. In such a case, for example, FIG.
As shown in (1), by applying a reference potential to the stylus electrode 3 connected to the disconnection detection wiring 1 on the side where the dark contrast is made by touching, the disconnection detection wiring 1 has a bright contrast. The short-circuit point 13 as described above can be specified.

FIG. 10 shows another TEG structure for detecting a short-circuit failure.

The TEG structure shown in the figure is obtained by laminating the above-described TEG structure. Since the upper-layer short-circuit detection wiring 2 is connected to the lower-layer short-circuit detection wiring 2 through the through hole 40, the upper-layer short-circuit detection wiring 2 is electrically connected to the p-type silicon substrate through the n-channel. The position can be specified. The disconnection detection wiring 1 can monitor the state of occurrence of each defect by maintaining insulation between upper and lower layers. Also,
The upper and lower stylus electrodes 3 and 3 ′ may be connected via the through holes 40 so that the state of occurrence of defects in the lower layer can be measured even when the upper layer is stacked. The TEG structure is effective for monitoring a change in a defect occurrence state due to lamination. In this TEG structure, after inspecting the lower layer,
The upper layer is formed and inspected. At this time, by measuring the wiring resistance of the lower layer, it is possible to inspect the influence of forming the upper layer. Considering that the short-circuit inspection wiring 2 is conducted vertically through the through hole 40,
Although not shown, it is preferable that the wiring width of the short-circuit inspection wiring 2 is widened so as to absorb the positional deviation at the time of forming the through hole. This is the same for the contact plug 5. Therefore, it is preferable that the wiring 2 for short-circuit inspection is formed wider than the wiring 1 for disconnection inspection. This is preferable because the short-circuit inspection wiring does not break. In this case, needless to say, the dimensions are determined in consideration of the capacitance difference between the disconnection inspection wiring 1 and the short-circuit inspection wiring 2 in the potential contrast method.

FIG. 11 shows another TEG structure for detecting a short circuit failure.

The TEG structure shown in the figure is limited to a function of detecting only a short-circuit defect, and a short-circuit detecting wiring 2 is arranged in a gap between comb-shaped wirings 41. If only a short circuit is to be detected in this way, it is sufficient if there is a comb-tooth wire having a common potential and a short-circuit detecting wire which is in a non-conductive state with the comb-tooth wire.

FIG. 12 shows another TEG structure for detecting a short circuit failure.

In the TEG structure shown in the drawing, a plurality of short-circuit detection wirings which have been arranged so far are each formed by one wiring like a short-circuit detection wiring 42. This makes it possible to reduce the number of scanning lines when specifying a defective position by line scanning, thereby shortening the specifying time.
Although not shown, if a plurality of contact plugs 5 are formed with respect to this one short-circuit detecting wiring 42,
It is possible to cope with a case where the short-circuit detection wiring 42 is disconnected.

FIG. 13 shows another TEG structure for detecting a short-circuit failure.

The TEG structure shown in the figure has a plurality of contact plugs 5 connected to each short-circuit detecting wiring 2. If the contact plug 5 is non-conductive, even if the short-circuit detection wiring 2 is short-circuited, this short-circuit defect is overlooked by an electrical inspection. In order to avoid this, a spare contact plug can be provided to accurately measure the presence or absence of a defect. Further, as described above, it is possible to cope with a case where the short-circuit detection wiring 2 is disconnected.

FIG. 14 shows another TEG structure for detecting a short circuit failure.

The TEG structure shown in the figure is provided with a stylus electrode 3 ″ in order to apply a substrate potential, and a p + channel 51 is provided.
And a P-type silicon substrate 6 via a contact plug 5. This is effective when current cannot be taken from the substrate.

FIG. 15 shows another TEG structure for detecting a short circuit failure.

The TEG structure shown in FIG.
Is connected to a P-type silicon substrate 6 via a p + channel 52 and a contact plug 5. In the appearance inspection by the SEM, inspection defects due to image drift due to charging of the disconnection detection wiring 1 can be reduced. Here, the p + channel 52 is formed by implanting impurities at a concentration higher than the impurity concentration of the P-type silicon substrate 6. (The p + channel 52 may be omitted and conduction may be performed only with the contact plug 5.) In the TEG structures described so far, a P-type silicon substrate is used, but an N-type semiconductor substrate may be used. . However, in this case, it is necessary to provide a P-type well region and appropriately arrange the channel region in the P-type well region. Further, in any of the above embodiments, either TEG may be mounted on the entire surface of the wafer, or TEG and product chips may be mixed and mounted on the wafer. At this time, the TEGs may be arranged in the wafer at a uniform pitch, may be arranged on concentric circles having different radii, or may be arranged on scribe lines. Further, it goes without saying that a system in which any of the above embodiments is appropriately combined is effective.

It is not necessary to form an n-channel if a diode effect can be obtained without forming an n-channel and the flow of electrons can be controlled.

Also, various types of disconnection detection wiring patterns and short-circuit detection wiring patterns have been disclosed. However, the wiring patterns are not limited to these patterns. Any structure may be used as long as a current flows in a fixed direction from the wiring to the substrate or from the substrate to the wiring via the wiring 5.

If the short-circuit position is detected using an appearance inspection or a current absorption method instead of the potential contrast method, it is not necessary to create a diode function, and it is sufficient to simply conduct. This also makes it possible to easily determine short-circuit and disconnection with one module, thereby improving inspection efficiency and manufacturing yield.

FIG. 16 shows a method for specifying a short-circuited portion or a disconnected portion by an appearance inspection device. In this method, the surface of the TEG is irradiated with a charged particle beam such as light or electrons by a visual inspection device (not shown), and the reflected light (bright-field light or dark-field light) or secondary electrons is obtained. Alternatively, an observation image (original image 14) of the surface structure of the TEG is acquired by detecting backscattered electrons, and one or two observation results (comparative image 15) of another region are acquired, and these difference images 16 are obtained. Is determined, and the presence or absence of a defect is confirmed. The figure shows an example of detecting a disconnection.

FIG. 17 is a diagram showing a method for specifying a defective portion using the absorption current method.

First, the probe 10 is brought into contact with one side of the stylus electrode 3 connected to the disconnection detection wiring 1. TEG
Is irradiated with a charged particle beam 20 such as an electron beam, the difference in the amount of emitted secondary electrons 21, that is, the current balance can be detected by a probe. The current change detected by the detector 30 is subjected to desired processing by the signal processing unit 32 and output to the display unit 33 as a scanned image. The absorption current method uses the above principle. When the position of the short-circuit defect is specified, no current flows to the probe in the normal short-circuit detection wiring, but the current flows in the short-circuited portion, so that the short-circuit defect can be detected. Similar to the above-described potential contrast method, by performing a line scan of the charged particle beam irradiation to detect a discontinuous point, or performing a comparative inspection with a normal part as an absorption current image as a two-dimensional image synchronized with the scan. , It is possible to specify the defective part. It is also effective to use the charged particle beam 20 to obtain an enlarged image of a short-circuited portion. In the case of disconnection position identification,
A change in the amount of absorption current can be confirmed, and the coordinates are stored in the same manner as in the case of the potential contrast method, or an enlarged image of the broken portion is directly obtained using the charged particle beam 20 used for irradiation. be able to.

FIG. 20 is a diagram showing a method of specifying a short-circuited portion using an emission microscope.

First, the probe 10 is brought into contact with the stylus electrodes 3 and 3 ″, and the power supply 103 is connected. As described in the previous embodiments, the short circuit 1
If 3 is present, current flows through this power supply 103. At this time, since this current flows via a PN junction formed by the P-type silicon substrate 6 and the n-channel 7, a light emission phenomenon occurs at the PN junction (light emission 101 due to short circuit). Although the wiring is formed in the upper layer, the light emission intensity due to the forward current is generally high, and the light emission leaks from the gap between the wirings. By capturing this light emission using an emission microscope, it is possible to detect the presence or absence of the short circuit 13 and the position where the short circuit 13 occurs. Thereafter, by performing physical analysis such as SEM or TEM based on the coordinates obtained here, the failure analysis time can be reduced. At this time, there is a possibility that a light-emitting phenomenon occurs (light-emitting from under the electrode 102) also by a PN junction formed by the p + channel 51 and the P-type silicon substrate 6. When the light emission is not blocked by the pad, the light emission from this portion is not due to the short circuit 13, and therefore, it is not necessary to recognize the defect as a defect or to store the coordinates.

In the method using the light-emitting microscope described here, not only the location of the short-circuit portion is specified but also the presence or absence of the short-circuit can be confirmed by measuring the current flowing through the power supply 103.

Also, the P-type silicon substrate 6 described here
Even in a case other than the TEG configuration in which light emission due to a PN junction formed by the N channel 7 is formed, a light emission phenomenon can be captured. For example, if the n-channel is a p-channel and the p-type silicon substrate is an n-type silicon substrate, if a voltage higher than the breakdown voltage of the diode is applied to the stylus at the time of short-circuit inspection, the light emission phenomenon due to the breakdown of the junction is detected. It is possible to do. The manufacturing process of the TEG shown in FIG. 1 will be described with reference to FIG. First, a groove for an element isolation region 8 is formed by etching a Si wafer (b),
An oxide film such as SiO2 is formed on the upper surface of the wafer by CVD or the like (c). An excess portion of the oxide film is removed by CMP (chemical mechanical polishing) and flattened to form a desired element isolation region 8 (d). Next, ion implantation is performed to form an n-channel 7 in a desired region (e). On this, an interlayer insulating film 4 such as SiO2 is deposited (f), a hole for embedding the contact plug 5 is formed by etching (g), and after a metal such as W is buried inside the hole (h), Excess metal material on the upper surface is removed by CMP to form a contact plug (i). In addition, S
An interlayer insulating film 4 such as iO2 is formed (j), and a wiring groove for a wiring pattern is formed (k). A barrier film (for example, TiN: titanium nitride, Ta)
(N: tantalum nitride, Ta: tantalum, etc.) (not shown), plating or sputtering of metal such as Cu (l), removing and flattening excess metal by CMP, and detecting disconnection Wiring 1, short-circuit detection wiring 2, and stylus electrodes 3, 3 '. Note that the pattern generation for any of the above-mentioned etching steps involves forming a resist mask in advance by a photolithography step and removing portions other than the mask. It is also possible to form the wiring by using Al or W by partially changing the process. It goes without saying that the same problem as the product can be extracted by the TEG by making the process as similar as possible to the product.

The feedback method to the production line of the present invention will be described with reference to FIG. The manufacturing process of the TEG is set, a Si wafer is input to the manufacturing line, and manufacturing is performed (STEP 1). After performing a wafer appearance inspection (for example, foreign matter inspection after film formation, appearance inspection after etching or CMP, SEM review after these inspections, etc.) between desired steps and after the steps in this manufacturing process (STEP 2), the tester An electrical test is performed by a prober or the like, and the TEG is determined to be good or bad (STEP 3). Based on the result of the electric test, a TEG to be analyzed is selected (with reference to the result of the visual inspection as necessary), and a defective position is specified for the TEG (STEP 4). Based on the position coordinates of the specified defect, the surface and cross-section are observed by SEM or TEM and material analysis is performed (STEP 5), the defect mechanism is estimated, and a countermeasure is formulated (STEP 6). If necessary, determine whether the frequency of occurrence of defects is higher than the target, determine whether measures should be taken, and take the necessary measures (process improvement, equipment improvement, cleaning inside equipment, etc.) and reflect the results in subsequent lots And confirm the effect (STEP
7). As a result, the reduction of defects can be promoted and the yield can be improved.

As described above, even if a short circuit occurs between the disconnection detection wiring 1 and the short detection wiring 2 by electrically connecting the short detection wiring 2 to the silicon substrate 6 side, the disconnection occurs. Electrode to be connected to detection wiring 1 and silicon substrate 6
By measuring the wiring resistance between the electrode and the electrode to be connected, it is possible to detect whether or not a short circuit has occurred.

Also, by forming an n-channel in the P-type silicon substrate 6, a diode function can be created so that secondary electrons are not emitted even by irradiation of charged particles in the potential contrast method. The position of “no” can also be detected as a difference in contrast.

As a result, the entire surface of the wafer composed of a plurality of TEGs is electrically measured, and T
After narrowing down the EG, the defect occurrence position can be specified by performing a detailed inspection only on the defective TEG, so that the defect occurrence state can be efficiently grasped. By estimating the generation model of the defect and taking measures against the generation source, it is possible to realize the cleaning of the production line and the improvement of the production yield.

[0056]

According to the present invention, the inspection efficiency using the TEG can be improved, and thereby the yield can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a TEG structure of the present invention.

FIG. 2 is a diagram illustrating a method for detecting a short-circuit failure.

FIG. 3 is a diagram illustrating a method for detecting a short-circuit failure.

FIG. 4 is a diagram showing a scanning method and an inspection algorithm.

FIG. 5 is a diagram illustrating a method for detecting a disconnection failure.

FIG. 6 is a diagram showing a scanning method and an inspection algorithm.

FIG. 7 is a diagram illustrating a method for detecting a disconnection failure and a short-circuit failure.

FIG. 8 is a diagram showing an inspection flow for disconnection failure and short-circuit failure.

FIG. 9 is a diagram illustrating a method for detecting a disconnection failure and a short-circuit failure.

FIG. 10 is a diagram showing a TEG structure according to the present invention.

FIG. 11 shows a TEG structure of the present invention.

FIG. 12 is a diagram showing a TEG structure according to the present invention.

FIG. 13 is a diagram showing a TEG structure according to the present invention.

FIG. 14 is a diagram showing a TEG structure according to the present invention.

FIG. 15 is a diagram showing a TEG structure of the present invention.

FIG. 16 is a diagram showing a method of detecting a broken portion by a visual inspection device.

FIG. 17 is a diagram showing a method of detecting a short-circuit point by a current absorption method.

FIG. 18 is a diagram showing a manufacturing process of the TEG of the present invention.

FIG. 19 is a feedback method to the production line of the present invention.

FIG. 20 is a diagram showing a method of detecting a short-circuited portion by an emission microscope.

[Explanation of Symbols] 1 ... wire for detecting disconnection, 2 ... wire for detecting short circuit, 3 ... electrode for stylus, 4 ... interlayer insulating film 5 ... contact plug, 6 ... P-type silicon substrate, 7 ... n
Channel, 8 ... element isolation region

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/822 H01L 27/04 T 27/04 (72) Inventor Hisao Asakura 6-16 Shinmachi, Shinmachi, Ome City, Tokyo No. 3 Inside Hitachi, Ltd. Device Development Center Co., Ltd. (72) Inventor Kazuyuki Tsukuni 5-2-1, Kamimizuhonmachi, Kodaira-shi, Tokyo In-house Hitachi, Ltd. Semiconductor Group (72) Inventor Yutoshi Sugimoto Tokyo 6-16 Shinmachi, Ome-shi, Tokyo F-term in the Device Development Center, Hitachi, Ltd.

Claims (15)

[Claims] An inspection is performed by using a first wiring provided on an insulating layer formed on a substrate and a second wiring electrically connected to the substrate and provided on the insulating layer. What is claimed is: 1. A method for manufacturing an electronic device, comprising: managing an electronic device by using an inspection result; and determining whether or not the first wiring is disconnected by measuring electric resistance at both ends of the first wiring. Inspecting, and measuring the electric resistance between the first wiring and the substrate to inspect whether the first wiring and the second wiring are short-circuited. A method for manufacturing an electronic device, comprising: 2. A first wiring provided on an insulating layer formed on a p-type silicon substrate and an n-type wiring formed on the p-type silicon substrate.
An electronic device manufacturing method for performing an inspection using a second wiring electrically connected via a channel and provided on the insulating layer, and managing and manufacturing the electronic device using the inspection result. Measuring whether or not the first wiring and the second wiring are short-circuited by measuring an electric resistance between the first wiring and the p-type silicon substrate. Manufacturing method of electronic device. 3. The method for manufacturing an electronic device according to claim 1, wherein said second wiring is disposed between wirings formed by said first wiring. 4. The method for manufacturing an electronic device according to claim 3, wherein said first wiring has a comb shape or a meandering shape. 5. The method according to claim 2, wherein a short-circuit point between the first wiring and the second wiring is detected by irradiating a charged particle beam using contrast. Method of manufacturing electronic device. 6. A wafer, wherein the first wiring and the second wiring according to any one of claims 1 to 5 are formed in a region other than a region to be a semiconductor device. 7. A semiconductor device on which the first wiring and the second wiring according to claim 1 are formed. 8. The method according to claim 1, wherein a short circuit is detected by detecting a light emission generated at a short-circuit point between the first wiring and the second wiring by flowing a current. 3. The method for manufacturing an electronic device according to claim 1. 9. A wafer wherein the first wiring and the second wiring according to claim 8 are formed in a region other than a region to be a semiconductor device. 10. A semiconductor device on which the first wiring and the second wiring according to claim 8 are formed. 11. A wafer provided with an electronic device and a wiring for inspecting the electronic device on a substrate, wherein the wiring for inspection is a first wiring for detecting a disconnection and a second wiring for detecting a short circuit. A wafer formed by forming an insulating layer on the substrate with the second wiring and the substrate being electrically connected to each other. 12. A wafer having an electronic device and a wiring for inspection of the electronic device on a substrate, wherein the wiring for inspection is a first wiring for detecting disconnection and a second wiring for detecting short circuit. A wafer formed on the substrate via an insulating layer, and wherein the second wiring and the substrate are connected by a channel via a contact plug. 13. The wafer according to claim 12, wherein each of said second wirings is electrically connected to said substrate via a plurality of contact plugs. 14. The wafer according to claim 12, wherein an element isolation portion is provided between the channels. 15. The wafer according to claim 1, wherein an electrode plate for a stylus is formed on the substrate via an insulating layer, and the substrate and the electrode plate for a stylus are electrically connected to each other. A wafer connected to the wafer.