CN113517260A - Wafer test structure, manufacturing method thereof and wafer - Google Patents
Wafer test structure, manufacturing method thereof and wafer Download PDFInfo
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- CN113517260A CN113517260A CN202110779761.1A CN202110779761A CN113517260A CN 113517260 A CN113517260 A CN 113517260A CN 202110779761 A CN202110779761 A CN 202110779761A CN 113517260 A CN113517260 A CN 113517260A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
Abstract
The application provides a wafer test structure and a manufacturing method thereof, and a wafer, which relate to the technical field of semiconductors and are used for solving the technical problem that the occupied space of the wafer test structure is large, and the wafer test structure comprises: the device comprises a plurality of resistors to be tested, a first test pad and a plurality of second test pads; the resistance testing device comprises a plurality of resistors to be tested, a plurality of resistors to be tested and a plurality of resistors to be tested, wherein the plurality of resistors to be tested are stacked, and an insulating layer is arranged between every two adjacent resistors to be tested; the first ends of the resistors to be tested are respectively electrically connected with the first test pads, the resistors to be tested are in one-to-one correspondence with the second test pads, and the second end of each resistor to be tested is electrically connected with one corresponding second test pad. One end of each resistor to be tested is connected in common, and the other end of each resistor to be tested is led out and connected with the second test pad, so that each resistor to be tested shares one first test pad, the total number of the first test pads and the total number of the second test pads are reduced on the basis of ensuring that each resistor to be tested can be measured normally, and the space occupied by the test structure is reduced.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a wafer test structure, a method for manufacturing the same, and a wafer.
Background
The wafer (wafer) comprises a plurality of crystal grains and cutting lines (scriber lines) for isolating the crystal grains, after an integrated circuit is formed on the crystal grains and before cutting and packaging, the crystal grains need to be selected and tested, the crystal grains are classified through the selection and testing, the crystal grains with defects or without normal working capacity are marked, and the crystal grains are filtered and discarded when the wafer is cut, so that the bad crystal grains are prevented from entering the packaging and subsequent manufacturing processes.
The selection Test includes Wafer Acceptance Test (WAT), which usually includes a plurality of destructive tests, and Test key (Test key) is usually fabricated on the scribe line to determine the performance of the integrated circuit device in the die. Important test parameters for acceptable testing of a wafer include the resistance of the resistor under test in the test structure.
However, with the complexity of the integrated circuit in the die, the number of resistors to be tested increases, resulting in a larger space occupied by the test structure.
Disclosure of Invention
In view of the foregoing problems, embodiments of the present application provide a wafer test structure, a method for manufacturing the same, and a wafer, so as to reduce a space occupied by the test structure.
In order to achieve the above object, the embodiments of the present application provide the following technical solutions:
in a first aspect, an embodiment of the present application provides a wafer test structure, which includes: the device comprises a plurality of resistors to be tested, a first test pad and a plurality of second test pads; the resistors to be tested are stacked, and an insulating layer is arranged between every two adjacent resistors to be tested; it is a plurality of the first end of resistance to be measured respectively with first test pad electricity is connected, and is a plurality of the resistance to be measured and a plurality of the second test pad one-to-one, and every the second end electricity of resistance to be measured connects corresponding one the second test pad.
The wafer test structure provided by the embodiment of the application has the following advantages:
in the wafer test structure provided by the embodiment of the application, a plurality of resistors to be tested are stacked, and an insulating layer is arranged between two adjacent resistors to be tested, so that the electrons to be tested are electrically isolated; the first ends of the resistors to be tested are electrically connected to the first test pad, and the second ends of the resistors to be tested are electrically connected to the second test pad respectively. One end of each resistor to be tested is connected in common, the other end of each resistor to be tested is led out and connected with the second test pad respectively, so that each resistor to be tested shares one first test pad, the total number of the first test pads and the total number of the second test pads are reduced on the basis of ensuring that the resistance value of each resistor to be tested can be measured normally, the space occupied by the wafer test structure is reduced, and the space utilization rate of a cutting channel is improved. Simultaneously, in this application embodiment with a plurality of resistances to be tested range upon range of setting in a test structure, avoided being connected independent resistance to be tested and test pad, realized testing a plurality of resistances to be tested through a range of test structure, and then reduced the area that resistance to be tested occupy.
In the wafer test structure, the first test pad and the plurality of second test pads are on the same layer as the to-be-tested resistor on the top layer among the plurality of to-be-tested resistors.
In the wafer testing structure, the first testing pad and the second testing pad are both copper pads.
In the wafer test structure, the insulating layer is a silicon oxide layer.
As described above, the resistor to be tested includes one or more of an active region, a gate, a capacitor and a metal layer.
According to the wafer test structure, the active region is arranged in the well, the well is arranged in the substrate, and the active region is circumferentially provided with the shallow trench isolation.
In the wafer test structure, the first test pad is connected to the voltage output end of the test machine, and the plurality of second test pads are connected to the ground end of the test machine; and the test machine platform measures the current value on the second test pad, and calculates the resistance value of the resistor to be tested corresponding to the second test pad according to the voltage value of the voltage output end and the current value.
The wafer test structure further comprises a first wire, wherein one first wire is arranged in each insulating layer, penetrates through the corresponding insulating layer, and is electrically connected with the first ends of the two resistors to be tested, which are adjacent to the first wires.
In the wafer test structure, the first conductive line is a through silicon via or a contact hole.
In the wafer test structure, the first conducting wire is located in the overlapping area of the two adjacent layers of the resistors to be tested.
In the wafer test structure, the first test pad is connected to the current output end of the machine to be tested, and any one of the second test pads on the side of the first wire to be tested away from the first test pad is connected to the ground end of the machine to be tested; and the test machine measures the voltage values of the second test pads corresponding to the two resistors to be tested which are adjacent to the first lead wire to be tested, and calculates the resistance value of the first lead wire to be tested according to the difference between the current value of the current output end and the measured voltage value.
The wafer test structure as described above, further comprising a second conductive line and a third conductive line; the second conducting wires are electrically connected with the resistors to be tested and the first testing pads on the top layer, the third conducting wires are arranged in a plurality of numbers, and each third conducting wire is electrically connected with the second end of each resistor to be tested and the corresponding second testing pad.
In a second aspect, an embodiment of the present application provides a method for manufacturing a wafer test structure, including:
step a: providing a substrate, wherein an active area is arranged in the substrate, and the active area is a resistor to be tested;
step b: forming an insulating layer on the resistor to be tested by using a chemical vapor deposition process;
step c: forming a metal layer on the insulating layer by using a physical vapor deposition process, wherein the metal layer is one resistor to be tested;
repeating the step b and the step c until the required number of the resistors to be tested is formed;
and forming a first test pad electrically connected with the first end of each resistor to be tested, and forming a second test pad which corresponds to and is electrically connected with the second end of each resistor to be tested.
The wafer test structure provided by the embodiment of the application has the following advantages:
in the manufacturing method of the wafer test structure in the embodiment of the application, the plurality of resistors to be tested are arranged in the test structure in a stacking mode, so that the plurality of resistors to be tested are tested through the stacked test structure, and the area occupied by the resistors to be tested is further reduced. Meanwhile, each resistor to be tested shares one first test pad, so that the space occupied by the wafer test structure is reduced and the space utilization rate of the cutting channel is improved on the basis of ensuring that the resistance value of each resistor to be tested can be measured normally.
The method for manufacturing the wafer test structure further includes: after an insulating layer is formed on the resistor to be tested by using a chemical vapor deposition process, carrying out planarization treatment on the insulating layer by using chemical mechanical polishing; and/or after a metal layer is formed on the insulating layer by utilizing a physical vapor deposition process, carrying out planarization treatment on the metal layer by utilizing chemical mechanical polishing.
The method for manufacturing the wafer test structure, after forming the insulating layer on the resistor to be tested by using a chemical vapor deposition process, further includes: etching the insulating layer to form a hole-shaped structure, wherein the hole-shaped structure exposes the first end of the resistor to be tested; and depositing a conductive material in the hole-shaped structure, wherein the conductive material fills the hole-shaped structure to form a first conducting wire.
In a third aspect, an embodiment of the present application provides a wafer, which includes a die and a scribe line located outside the die, where an integrated circuit is disposed in the die, and a wafer test structure is disposed in the scribe line; the integrated circuit comprises a plurality of devices to be tested, the wafer test structure comprises a plurality of resistors to be tested, a first test pad and a plurality of second test pads, and the plurality of resistors to be tested and the plurality of devices to be tested correspond to each other one by one and have the same key size; it is a plurality of treat that the resistance to be tested stacks up the setting, and adjacent two be provided with the insulating layer between the resistance to be tested, it is a plurality of the first end electricity of resistance to be tested is connected first test pad, and is a plurality of the resistance to be tested is with a plurality of second test pad one-to-one, and every corresponding one is connected to the second end electricity of resistance to be tested the second test pad.
The wafer provided by the embodiment of the application has the following advantages:
in the wafer that this application embodiment provided, obtain the electrical parameter of each device to be tested in the integrated circuit through each resistance to be tested in the wafer test structure, the one end of each resistance to be tested in the wafer test structure connects altogether, draw the other end of each resistance to be tested respectively and connect the second test pad, make each resistance to be tested share a first test pad, on the basis that the resistance value that guarantees each resistance to be tested can normal measurement, the total number of first test pad and second test pad has been reduced, thereby the shared space of wafer test structure has been reduced, the space utilization who cuts the way has been improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic diagram of a wafer test structure in the related art;
FIG. 2 is a schematic structural diagram of a wafer according to an embodiment of the present disclosure;
FIG. 3 is a schematic structural diagram of a wafer test structure according to an embodiment of the present application;
FIG. 4 is a schematic current diagram of a wafer test structure according to an embodiment of the present application;
fig. 5 is a schematic distribution diagram of the first test pad and the second test pad in the embodiment of the present application.
Description of reference numerals:
100-a wafer; 110-crystal grains;
120-cutting a street; 200-wafer test structure;
210-resistance to be measured; 220-an insulating layer;
230-a first test pad; 240-a second test pad;
250-a substrate; 251-shallow trench isolation;
252-a well; 260-a first conductive line;
270-a second conductive line; 280-a third wire;
300-a test pad; 400-Probe.
Detailed Description
Referring to fig. 1, in the related art, two ends of each resistor 210 to be tested in the wafer test structure 200 are respectively provided with one test pad 300, and the resistance value of the resistor 210 to be tested is calculated by testing the voltage value difference between the two test pads 300 at the two ends of the resistor 210 to be tested and the current value of any one test pad 300 of the two test pads 300 at the two ends of the resistor 210 to be tested. The wafer test structure 200 requires more test pads 300, so that the wafer test structure 200 occupies a larger space and the scribe lines 120 have a lower space utilization.
In view of the above technical problems, an embodiment of the present application provides a wafer test structure and a wafer, in the wafer test structure, one end of each resistor to be tested is electrically connected to a first test pad, the other end of each resistor to be tested is electrically connected to a second test pad, and one end of each resistor to be tested shares the first test pad, so that the total number of the first test pads and the second test pads is reduced, the space occupied by the wafer test structure is further reduced, and the space utilization rate of a cutting channel is improved.
In order to make the aforementioned objects, features and advantages of the embodiments of the present application more comprehensible, embodiments of the present application are described in detail below with reference to the accompanying drawings. It is to be understood that the described embodiments are merely a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 2, a wafer 100 includes a die 110 and scribe lines 120, the scribe lines 120 are located outside the die 110. Illustratively, the wafer 100 includes a plurality of dies 110, scribe lines 120 are located between the dies 110, and the scribe lines 120 are adjacent to the dies 110.
An Integrated Circuit (IC) is disposed in the die 110, and the IC is formed by deposition, development, etching, doping, and thermal treatment. The integrated circuit includes a plurality of components (resistors, capacitors, transistors, diodes, etc.), stacked layers, interconnections, etc., a part of the integrated circuit is configured as a device under test, and a plurality of devices under test are usually configured to monitor a process condition of the integrated circuit by detecting an electrical parameter (e.g., a resistance value) of the device under test.
A wafer test structure 200 is disposed in the scribe line 120, the wafer test structure 200 includes a plurality of resistors to be tested 210, the plurality of resistors to be tested 210 in the wafer test structure 200 correspond to the plurality of devices to be tested in the integrated circuit one by one, and each resistor to be tested 210 has the same Critical Dimension (CD) as the corresponding device to be tested, so that the corresponding device to be tested can be represented by the resistor to be tested 210, and the electrical parameters of the device to be tested can be obtained by testing the electrical parameters of the resistor to be tested 210. The wafer test structures 200 in the streets 120 may be formed simultaneously with the integrated circuits in the dice 110.
Referring to fig. 3, the wafer test structure 200 includes a plurality of resistors to be tested 210, the plurality of resistors to be tested 210 are sequentially stacked, and an insulating layer 220 is disposed between two adjacent resistors to be tested 210, so as to electrically isolate the two adjacent layers of resistors to be tested 210 and avoid electrical connection between the resistors to be tested 210. Illustratively, the insulating layer 220 may be a silicon oxide layer (e.g., SiO)2Layer) or silicon nitride layer (e.g. SI)3N4Layers).
The resistance to be measured 210 may include one or more of an active region, a gate, a capacitor, or a metal layer (e.g., a copper interconnect metal layer). Illustratively, one of the resistors 210 to be tested in the wafer test structure 200 is an active area, i.e., a resistance value of the active area is measured. As shown in fig. 3, the active region is disposed in a Well (Well)252, and the Well 252 is disposed in a substrate 250.
The substrate 250 may be a P-type substrate, that is, the concentration of holes in the substrate 250 is greater than the concentration of free electrons, and the substrate 250 mainly conducts electricity by using holes as carriers. The trap 252 is formed by ion implantation in the substrate 250, and the trap 252 has a certain ion concentration. As shown in fig. 3, the active region is located in the well 252, and a Shallow Trench Isolation (STI) 251 is disposed in the active region in the circumferential direction. During the fabrication of the shallow trench isolation 251, the substrate 250 is patterned by using silicon nitride as a mask to form a recess on the substrate 250, and an oxide is deposited in the recess to isolate the active region.
Referring to fig. 4 and 5, first ends of the plurality of resistors to be tested 210 are electrically connected to the first test pad 230, respectively, and a second end of each of the plurality of resistors to be tested 210 is electrically connected to one of the second test pads 240. It is understood that the number of the first test pads 230 is one, and the number of the second test pads 240 is the same as the number of the resistors 210 to be tested.
With such an arrangement, as shown in fig. 4 and 5, the first ends of the resistors 210 to be tested are connected in common and share one first test pad 230, so that the number of the first test pads 230 is reduced, the total number of the first test pads 230 and the second test pads 240 is reduced, and the space occupied by the wafer test structure 200 is further reduced.
The first test pads 230 and the second test pads 240 are made of conductive material, so that the wafer test structure 200 has conductivity. For example, the first test pad 230 and each second test pad 240 are made of metal, for example, the first test pad 230 and each second test pad 240 are copper (Cu) pads or aluminum (Al) pads.
In a possible example, as shown in fig. 4, a first conducting wire 260 is disposed in each insulating layer, the first conducting wire 260 penetrates through the insulating layer where the first conducting wire 260 is disposed, and two ends of the first conducting wire 260 are electrically connected to first ends of two resistors to be tested 210 adjacent to the insulating layer where the first conducting wire 260 is disposed, that is, the first ends of the resistors to be tested 210 are electrically connected by the first conducting wire 260.
The first wires 260 are located in the overlapping area of the two adjacent layers of resistors 210 to be tested, so as to prevent the first wires 260 from extending to the outside of the projection area of the resistors 210 to be tested, and reduce the space occupied by the wafer test structure 200. The first conductive lines 260 may be aligned with each other, and each of the first conductive lines 260 may be a Through Silicon Via (TSV) or a Contact (CT), which is made of copper or tungsten (W).
For example, as shown in fig. 3 and 4, a first conducting line 260 is disposed in the insulating layer 220 between the resistor 210 to be measured on the uppermost layer and the resistor 210 to be measured on the next upper layer. The upper end of the first wire 260 contacts with the first end of the uppermost layer of the resistor 210 to be tested, the lower end of the first wire 260 contacts with the first end of the next upper layer of the resistor 210 to be tested, and the first wire 260 is electrically connected with both the uppermost layer of the resistor 210 to be tested and the next upper layer of the resistor 210 to be tested. The first wire 260 is located in an overlapping region of the uppermost resistor 210 to be tested and the next upper resistor 210 to be tested, that is, an orthogonal projection of the first wire 260 in the vertical direction (Y direction shown in fig. 4) is located in an orthogonal projection range of the uppermost resistor 210 to be tested and the next upper resistor 210 to be tested.
With continued reference to fig. 4 and 5, when the wafer test structure 200 is connected to a test machine, a probe 400 passing through the test machine provides a current or voltage through the first test pad 230 (not shown in fig. 4). The direction of the current in the wafer test structure 200 is shown in fig. 4, and the current flows into each resistor under test 210 below the top layer through the first conductive line 260.
It should be noted that, as shown in fig. 5, the wafer test structure 200 further includes a second wire 270 and a third wire 280, wherein the second wire 270 electrically connects the top layer of the resistor to be tested 210 and the first test pad 230, so as to electrically connect the first end of each resistor to be tested 210 with the first test pad 230. The third wires 280 are provided in a plurality, the plurality of third wires 280 correspond to the plurality of resistors to be tested 210 one by one, and each third wire 280 is connected to one resistor to be tested 210 and the second test pad 240 corresponding to the resistor to be tested 210. It is understood that there is a one-to-one correspondence between the third conductive line 280, the resistor 210 to be tested and the second test pad 240.
Referring to fig. 5, the first test pad 230 and the plurality of second test pads 240 are located on the same layer, and are located on the same layer as the to-be-tested resistors 210 located on the top layer among the plurality of to-be-tested resistors 210. As shown in fig. 5, the first test pad 230, the second test pad 240 and the top layer of the resistor 210 to be tested are located on the same layer, that is, the first test pad 230 and the second test pad 240 are located on the same layer of the top layer of the resistor 210 to be tested, so that the first test pad 230 and the second test pad 240 are exposed, the measurement is facilitated, and the measurement accuracy is improved.
In one possible example, the wafer test structure 200 includes five resistors 210 to be tested and four insulating layers 220. For convenience of description, as shown in fig. 4, the five resistors 210 to be measured are respectively defined as a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4 and a fifth resistor R5 from top to bottom, and the embodiments of the present application and the following embodiments are all explained by taking the above five resistors as examples. The specific structure and test principle of the wafer test structure 200 when the number of the resistors 210 to be tested is not five are referred to the specific structure and test principle of the wafer test structure 200 when the number of the resistors 210 to be tested is five.
The wafer test structure 200 includes a first test pad 230 and five second test pads 240. As shown in fig. 4 and 5, the second test PAD 240 electrically connected to the first resistor R1 is PAD1, the second test PAD 240 electrically connected to the second resistor R2 is PAD2, the second test PAD 240 electrically connected to the third resistor R3 is PAD3, the second test PAD 240 electrically connected to the fourth resistor R4 is PAD4, the second test PAD 240 electrically connected to the fifth resistor R5 is PAD5, and the first test PAD 230 is PAD 6.
A second wire 270 is connected between PAD6 and first resistor R1. As shown in fig. 4 and 5, a first wire 260 is connected between the first resistor R1 and the second resistor R2, between the second resistor R2 and the third resistor R3, between the third resistor R3 and the fourth resistor R4, and between the fourth resistor R4 and the fifth resistor R5. Specifically, a first wire 260 between the first resistor R1 and the second resistor R2 is N1, a first wire 260 between the second resistor R2 and the third resistor R3 is N2, a first wire 260 between the third resistor R3 and the fourth resistor R4 is N3, and a first wire 260 between the fourth resistor R4 and the fifth resistor R5 is N4.
As shown in fig. 4 and 5, a third wire 280 is connected between the first resistor R1 and the PAD1, between the second resistor R2 and the PAD2, between the third resistor R3 and the PAD3, between the fourth resistor R4 and the PAD4, and between the fifth resistor R5 and the PAD 5.
During measurement, the first test pad 230 is connected to the voltage output terminal of the tester, and each of the second test pads 240 is connected to the ground terminal of the tester. The testing machine measures the current value on the second testing pad 240, and calculates the measured resistance value of the resistor 210 to be tested corresponding to the second testing pad 240 according to the voltage value and the current value of the voltage output end.
The testing machine includes a plurality of probes 400, the probes 400 are respectively inserted into the first testing pad 230 and the second testing pad 240 corresponding to any resistor 210 to be tested, and the testing machine provides a voltage to the first testing pad 230 and the second testing pad 240 through the probes 400 and measures a current.
For example, the plurality of probes 400 of the testing machine are respectively tied to the first testing pad 230 and all the second testing pads 240, a voltage value (a voltage value at the voltage output end) of the first testing pad 230 is Vm, and the second testing pads 240 are grounded, that is, a voltage value of the second testing pads 240 is 0. The currents measured on PAD1, PAD2, PAD3, PAD4, PAD5 are I1, I2, I3, I4, I5, respectively. Correspondingly, the resistance values of the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4 and the fifth resistor R5 are respectively: r1 ═ Vm/I1, R2 ═ Vm/I2; r3 ═ Vm/I3; r4 ═ Vm/I4; r5 ═ Vm/I5.
The wafer test structure 200 in the embodiment of the present application can also obtain the resistance value of the first conductive line 260. Specifically, the first test pad 230 is connected to a current output end of the test machine, and any one of the second test pads 240 on a side of the first wire 260 to be tested away from the first test pad 230 is connected to a ground terminal of the test machine, for example, the second test pad 240 corresponding to the bottom resistor 210 to be tested in the plurality of resistors 210 to be tested is connected to the ground terminal of the test machine, so that a current at the current output end flows through the first wire 260 to be tested.
The tester measures the voltage values of the second test pads 240 corresponding to the two resistors to be tested 210 adjacent to the first wire 260 to be tested, and calculates the resistance value of the first wire 260 to be tested according to the difference between the current value of the current output terminal and the measured voltage value.
Illustratively, the resistance value of N1 may be obtained by the following process: the first test PAD 230 is connected to a current output terminal of the test platform, the current value of the current output terminal is Ih, and the PAD3 is grounded. The testing machine measures the voltage values of the PAD1 and the PAD2 respectively corresponding to the first resistor R1 and the second resistor R2 adjacent to the N1, for example, the voltage value of the PAD1 is Vh, the voltage value of the PAD2 is V1, and then the resistance value of the N1 is: RN1 ═ V-V1)/Ih.
In the wafer test structure 200 provided in the embodiment of the present application, a plurality of resistors to be tested 210 are stacked, and an insulating layer 220 is disposed between two adjacent resistors to be tested 210, so as to electrically isolate each of the electrons to be tested; the first ends of the to-be-tested resistors 210 are electrically connected to the first test pad 230, and the second ends of the to-be-tested resistors 210 are electrically connected to one second test pad 240, respectively. One end of each resistor 210 to be tested is connected in common, and the other end of each resistor 210 to be tested is led out and connected with each second test pad 240 respectively, so that each resistor 210 to be tested shares one first test pad 230, and on the basis of ensuring that the resistance value of each resistor 210 to be tested can be measured normally, the total number of the first test pads 230 and the second test pads 240 is reduced, so that the space occupied by the wafer test structure 200 is reduced, and the space utilization rate of the cutting channels 120 is improved. Meanwhile, the plurality of resistors to be tested 210 are stacked in the test structure 200, so that the independent resistors to be tested 210 are prevented from being connected with the test pad, the plurality of resistors to be tested 210 are tested through the stacked test structure 200, and the occupied area of the resistors to be tested 210 is further reduced.
An embodiment of the present invention further provides a method for manufacturing a wafer test structure, and referring to fig. 1 to 5, the method for manufacturing a wafer test structure includes:
step a: providing a substrate, wherein an active area is arranged in the substrate, and the active area is a resistor to be tested.
The wafer test structure 200 in the embodiment of the present application may measure the resistance of the active region, which may be disposed in the well 252, and the well 252 is disposed on the substrate 250. The substrate 250 may be a P-type substrate 250, and the well 252 is formed by performing ion implantation in the substrate 250. The active region is located in the well 252, and the active region is circumferentially provided with a shallow trench isolation 251.
Step b: and forming an insulating layer on the resistor to be tested by utilizing a chemical vapor deposition process.
The insulating layer 220 is formed on the substrate 250 through a Chemical Vapor Deposition (CVD) process. The insulating layer 220 covers the active region to electrically isolate the active region. The material of the insulating layer 220 may include silicon oxide or silicon nitride.
After the insulating layer 220 is formed, a planarization process may be performed on a surface of the insulating layer 220 away from the substrate 250, so that each film layer formed on the insulating layer 220 is relatively flat. Illustratively, the upper surface of the insulating layer 220 is planarized by Chemical Mechanical Polishing (CMP).
In some possible examples, a first wire 260 is disposed in the insulating layer 220, and the first wire 260 penetrates through the insulating layer 220 to electrically connect the resistors 210 to be tested on two sides of the insulating layer 220. The first conductive line 260 may be a through silicon via or a contact hole, and may be made of copper or tungsten.
Specifically, after the insulating layer 220 is formed, the insulating layer 220 is etched to form a hole structure, and the hole structure exposes the first end of the resistor 210 to be tested, i.e., the hole structure penetrates through the insulating layer 220. The orthographic projection of the resistor 210 to be measured on the substrate 250 covers the orthographic projection of the hole-shaped structure on the substrate 250. After the hole structure is formed, a conductive material is deposited in the hole structure, and the conductive material fills the hole structure to form the first conductive line 260.
Step c: and forming a metal layer on the insulating layer by using a physical vapor deposition process, wherein the metal layer is a resistor to be tested.
The metal layer may be a copper interconnection layer, the metal layer is formed on the insulating layer 220 by a Physical Vapor Deposition (PVD) process, and a first end of the metal layer contacts the first conductive line 260 in the insulating layer 220, so as to be electrically connected to the first conductive line 260.
After the metal layer is formed, a planarization process may be performed on the surface of the metal layer facing away from the substrate 250 to planarize the surface of the metal layer. The upper surface of the metal layer is planarized, for example, by chemical mechanical polishing.
It is understood that the metal layers and the insulating layers 220 in the wafer test structure 200 may be planarized to make the surfaces of the metal layers and the insulating layers 220 away from the substrate 250 smoother, or a certain layer or layers of the metal layers and the insulating layers 220 may be planarized to ensure the flatness of the more critical layers.
And repeating the steps b and c until the required number of the resistors 210 to be tested are formed. That is, the steps of forming the metal layer and the insulating layer 220 are repeated until the required number of resistors to be tested 210 are formed, and the resistors to be tested 210 and the insulating layer 220 are alternately stacked.
A first test pad 230 electrically connected to the first end of each resistor 210 to be tested is formed, and a second test pad 240 electrically connected to the second end of each resistor 210 to be tested is formed in a one-to-one correspondence. The first test pad 230 and each second test pad 240 are made of a conductive material, for example, the first test pad 230 and each second test pad 240 are copper (Cu) pads or aluminum (Al) pads. The first test pad 230 and the plurality of second test pads 240 are located on the same layer, and are located on the same layer as the to-be-tested resistors 210 located on the top layer among the plurality of to-be-tested resistors 210. As shown in fig. 5, the first test pad 230, the second test pad 240 and the top layer of the resistor 210 to be tested are located on the same layer.
In the manufacturing method of the wafer test structure 200 provided by the embodiment of the application, the plurality of resistors to be tested 210 are stacked, and the insulating layer 220 is arranged between two adjacent resistors to be tested 210, so that the plurality of resistors to be tested 210 are tested through one stacked test structure 200, and the area occupied by the resistors to be tested 210 is further reduced. Meanwhile, each resistor 210 to be tested shares one first test pad 230, so that the space occupied by the wafer test structure 200 is reduced and the space utilization rate of the scribe line 120 is improved on the basis of ensuring that the resistance value of each resistor 210 to be tested can be measured normally.
The embodiments or implementation modes in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.
In the description of the present specification, references to "one embodiment", "some embodiments", "an illustrative embodiment", "an example", "a specific example", or "some examples" and the like mean that a specific feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.
Claims (16)
1. A wafer test structure, comprising: the device comprises a plurality of resistors to be tested, a first test pad and a plurality of second test pads; the resistors to be tested are stacked, and an insulating layer is arranged between every two adjacent resistors to be tested;
it is a plurality of the first end of resistance to be measured respectively with first test pad electricity is connected, and is a plurality of the resistance to be measured and a plurality of the second test pad one-to-one, and every the second end electricity of resistance to be measured connects corresponding one the second test pad.
2. The wafer test structure as claimed in claim 1, wherein the first test pad and the plurality of second test pads are in the same layer as the to-be-tested resistor located at the top layer among the plurality of to-be-tested resistors.
3. The wafer test structure as claimed in claim 1, wherein the first test pad and the second test pad are both copper pads.
4. The wafer test structure of claim 1, wherein the insulating layer is a silicon oxide layer.
5. The wafer test structure of claim 1, wherein the resistance to be tested comprises one or more of an active region, a gate, a capacitor, and a metal layer.
6. The wafer test structure as claimed in claim 5, wherein the active region is disposed in a well disposed in the substrate, and the active region is circumferentially disposed with shallow trench isolation.
7. The wafer test structure as claimed in any one of claims 1 to 6, wherein the first test pad is connected to a voltage output terminal of a tester, and the plurality of second test pads are connected to a ground terminal of the tester;
and the test machine platform measures the current value on the second test pad, and calculates the resistance value of the resistor to be tested corresponding to the second test pad according to the voltage value of the voltage output end and the current value.
8. The wafer test structure as claimed in any one of claims 1 to 6, wherein the wafer test structure further includes first wires, one first wire is disposed in each insulating layer, and the first wires penetrate through the corresponding insulating layer and electrically connect the first ends of the two resistors to be tested adjacent to the first wires.
9. The wafer test structure as claimed in claim 8, wherein the first conductive line is a through silicon via or a contact hole.
10. The wafer test structure as claimed in claim 9, wherein the first conductive line is located in a region where two adjacent layers of the resistors to be tested overlap.
11. The wafer test structure as claimed in claim 8, wherein the first test pad is connected to a current output terminal of a test machine, and any one of the second test pads on a side of the first conductive line to be tested away from the first test pad is connected to a ground terminal of the test machine;
and the test machine measures the voltage values of the second test pads corresponding to the two resistors to be tested which are adjacent to the first lead wire to be tested, and calculates the resistance value of the first lead wire to be tested according to the difference between the current value of the current output end and the measured voltage value.
12. The wafer test structure of claim 7, wherein the wafer test structure further comprises a second conductive line and a third conductive line;
the second conducting wires are electrically connected with the resistors to be tested and the first testing pads on the top layer, the third conducting wires are arranged in a plurality of numbers, and each third conducting wire is electrically connected with the second end of each resistor to be tested and the corresponding second testing pad.
13. A method for manufacturing a wafer test structure is characterized by comprising the following steps:
step a: providing a substrate, wherein an active area is arranged in the substrate, and the active area is a resistor to be tested;
step b: forming an insulating layer on the resistor to be tested by using a chemical vapor deposition process;
step c: forming a metal layer on the insulating layer by using a physical vapor deposition process, wherein the metal layer is one resistor to be tested;
repeating the step b and the step c until the required number of the resistors to be tested is formed;
and forming a first test pad electrically connected with the first end of each resistor to be tested, and forming a second test pad which corresponds to and is electrically connected with the second end of each resistor to be tested.
14. The method as claimed in claim 13, further comprising:
after an insulating layer is formed on the resistor to be tested by using a chemical vapor deposition process, carrying out planarization treatment on the insulating layer by using chemical mechanical polishing;
and/or after a metal layer is formed on the insulating layer by utilizing a physical vapor deposition process, carrying out planarization treatment on the metal layer by utilizing chemical mechanical polishing.
15. The method as claimed in claim 13, wherein after forming an insulating layer on the resistor to be tested by a chemical vapor deposition process, the method further comprises:
etching the insulating layer to form a hole-shaped structure, wherein the hole-shaped structure exposes the first end of the resistor to be tested;
and depositing a conductive material in the hole-shaped structure, wherein the conductive material fills the hole-shaped structure to form a first conducting wire.
16. A wafer is characterized by comprising a crystal grain and a cutting channel positioned outside the crystal grain, wherein an integrated circuit is arranged in the crystal grain, and a wafer test structure is arranged in the cutting channel;
the integrated circuit comprises a plurality of devices to be tested, the wafer test structure comprises a plurality of resistors to be tested, a first test pad and a plurality of second test pads, and the plurality of resistors to be tested and the plurality of devices to be tested correspond to each other one by one and have the same key size;
it is a plurality of treat that the resistance to be tested stacks up the setting, and adjacent two be provided with the insulating layer between the resistance to be tested, it is a plurality of the first end electricity of resistance to be tested is connected first test pad, and is a plurality of the resistance to be tested is with a plurality of second test pad one-to-one, and every corresponding one is connected to the second end electricity of resistance to be tested the second test pad.
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