CN113517260B - Wafer test structure, manufacturing method thereof and wafer - Google Patents
Wafer test structure, manufacturing method thereof and wafer Download PDFInfo
- Publication number
- CN113517260B CN113517260B CN202110779761.1A CN202110779761A CN113517260B CN 113517260 B CN113517260 B CN 113517260B CN 202110779761 A CN202110779761 A CN 202110779761A CN 113517260 B CN113517260 B CN 113517260B
- Authority
- CN
- China
- Prior art keywords
- tested
- test
- resistor
- resistors
- wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
Abstract
The application provides a wafer test structure, a manufacturing method thereof and a wafer, which relate to the technical field of semiconductors and are used for solving the technical problem that the space occupied by the wafer test structure is large, and the wafer test structure comprises: a plurality of resistors to be tested, a first test pad and a plurality of second test pads; the plurality of resistors to be tested are arranged in a stacked mode, and an insulating layer is arranged between two adjacent resistors to be tested; the first ends of the plurality of resistors to be tested are respectively and electrically connected with the first test pads, the plurality of resistors to be tested are in one-to-one correspondence with the plurality of second test pads, and the second end of each resistor to be tested is electrically connected with a corresponding second test pad. Through connect the one end of each resistance that awaits measuring altogether, draw forth and connect the second test pad respectively with the other end of each resistance that awaits measuring for each resistance that awaits measuring shares a first test pad, on guaranteeing that each resistance that awaits measuring can normally measure, reduced the total number of first test pad and second test pad, thereby reduced the space that test structure took.
Description
Technical Field
The present application relates to the field of semiconductor technologies, and in particular, to a wafer testing structure, a manufacturing method thereof, and a wafer.
Background
A wafer (wafer) includes a plurality of dies and dicing streets (dicing lines) separating the dies, and after the integrated circuits are formed on the dies, the dies need to be subjected to a sort test before dicing the package, the dies are sorted by the sort test, the dies with defects or without normal operation are marked with marks, and the dies are filtered out and discarded when the wafer is diced, thereby avoiding bad dies from entering the package and subsequent processes.
The pick tests include wafer acceptance tests (Wafer Acceptance Test, WAT for short), which typically involve a number of destructive tests, and test structures (test keys) are typically fabricated on the scribe lines, and the test structures are inspected to infer the performance of the devices of the integrated circuits in the die. Important test parameters that a wafer can accept a test include the resistance value of the resistor under test in the test structure.
However, with the complexity of integrated circuits in a die, the number of resistors to be tested increases, resulting in a larger space occupied by the test structure.
Disclosure of Invention
In view of the above, embodiments of the present application provide a wafer testing structure, a manufacturing method thereof, and a wafer for reducing a space occupied by the testing structure.
In order to achieve the above object, the embodiment of the present application provides the following technical solutions:
in a first aspect, an embodiment of the present application provides a wafer test structure, including: a plurality of resistors to be tested, a first test pad and a plurality of second test pads; the resistors to be tested are arranged in a stacked mode, and an insulating layer is arranged between two adjacent resistors to be tested; the first ends of the plurality of resistors to be tested are respectively and electrically connected with the first test pads, the plurality of resistors to be tested are in one-to-one correspondence with the plurality of second test pads, and the second end of each resistor to be tested is electrically connected with a corresponding second test pad.
The wafer test structure provided by the embodiment of the application has the following advantages:
in the wafer test structure provided by the embodiment of the application, a plurality of resistors to be tested are arranged in a stacked manner, and an insulating layer is arranged between two adjacent resistors to be tested, so that each electron to be tested is electrically isolated; the first ends of the plurality of resistors to be tested are electrically connected to the first test pad, and the second ends of the plurality of resistors to be tested are respectively electrically connected to the second test pad. Through the one end of each resistance that awaits measuring is commonly connected, draws forth respectively and each second test pad with the other end of each resistance that awaits measuring for each resistance that awaits measuring shares a first test pad, on guaranteeing that the resistance value of each resistance that awaits measuring can normally measure, has reduced the total number of first test pad and second test pad, thereby has reduced the space that the wafer test structure took, has improved the space utilization of cutting path. Meanwhile, in the embodiment of the application, the plurality of resistors to be tested are arranged in the test structure in a stacked manner, so that the connection of the independent resistors to be tested and the test pad is avoided, the plurality of resistors to be tested are tested through the stacked test structure, and the occupied area of the resistors to be tested is further reduced.
In the wafer test structure, the first test pad and the plurality of second test pads are on the same layer as the resistor to be tested on the top layer of the plurality of resistors to be tested.
In the wafer test structure, the first test pad and the second test pad are copper pads.
In the wafer test structure, the insulating layer is a silicon oxide layer.
The wafer test structure as described above, the resistor to be tested includes one or more of an active region, a gate, a capacitor and a metal layer.
In the wafer test structure, the active region is arranged in the well, the well is arranged in the substrate, and shallow trench isolation is arranged in the circumferential direction of the active region.
In the wafer test structure, the first test pad is connected with the voltage output end of the test machine, and the plurality of second test pads are connected with the grounding end of the test machine; the test machine measures the current value on the second test pad, and calculates the resistance value of the resistor to be tested corresponding to the second test pad according to the voltage value of the voltage output end and the current value.
The wafer test structure further comprises a first wire, one first wire is arranged in each insulating layer, the first wire penetrates through the corresponding insulating layer, and the first ends of the two resistors to be tested, which are adjacent to the first wire, are electrically connected.
In the wafer test structure, the first wire is a through silicon via or a contact hole.
In the wafer test structure, the first conducting wire is positioned in the overlapping area of the two adjacent layers of the resistors to be tested.
In the wafer test structure, the first test pad is connected with the current output end of the to-be-tested machine, and any one of the second test pads on one side of the first lead far away from the first test pad is connected with the grounding end of the test machine; the test machine measures voltage values on the second test pads corresponding to the two to-be-tested resistors adjacent to the to-be-tested first wire, and calculates the resistance value of the to-be-tested first wire according to the difference between the current value of the current output end and the measured voltage value.
The wafer test structure further comprises a second wire and a third wire; the second wires are electrically connected with the resistor to be tested and the first test pad on the top layer, the third wires are arranged in a plurality, and each third wire is electrically connected with the second end of each resistor to be tested and the corresponding second test pad.
In a second aspect, an embodiment of the present application provides a method for manufacturing a wafer test structure, including:
step a: providing a substrate, wherein an active area is arranged in the substrate, and the active area is a resistor to be tested;
step b: forming an insulating layer on the resistor to be tested by using a chemical vapor deposition process;
step c: forming a metal layer on the insulating layer by using a physical vapor deposition process, wherein the metal layer is one resistor to be tested;
repeating the step b and the step c until the required number of the resistors to be tested are formed;
and forming a first test pad electrically connected with the first end of each resistor to be tested, and forming a second test pad in one-to-one correspondence with and electrically connected with the second end of each resistor to be tested.
The wafer test structure provided by the embodiment of the application has the following advantages:
in the manufacturing method of the wafer test structure, a plurality of resistors to be tested are stacked in one test structure, so that the plurality of resistors to be tested are tested through the stacked test structure, and the occupied area of the resistors to be tested is reduced. Meanwhile, each resistor to be tested shares a first test pad, so that the space occupied by the wafer test structure is reduced and the space utilization rate of the cutting channel is improved on the basis of ensuring that the resistance value of each resistor to be tested can be measured normally.
The manufacturing method of the wafer test structure further comprises the following steps: after forming an insulating layer on the resistor to be tested by using a chemical vapor deposition process, flattening the insulating layer by using chemical mechanical polishing; and/or after forming a metal layer on the insulating layer by using a physical vapor deposition process, flattening the metal layer by using chemical mechanical polishing.
The method for manufacturing the wafer test structure, after forming the insulating layer on the resistor to be tested by using the chemical vapor deposition process, further comprises: etching the insulating layer to form a hole-shaped structure, wherein the hole-shaped structure exposes the first end of the resistor to be tested; depositing a conductive material within the hole structure, the conductive material filling the hole structure to form a first wire.
In a third aspect, an embodiment of the present application provides a wafer, including a die and a scribe line located outside the die, where an integrated circuit is disposed in the die, and a wafer test structure is disposed in the scribe line; the integrated circuit comprises a plurality of devices to be tested, the wafer test structure comprises a plurality of resistors to be tested, a first test pad and a plurality of second test pads, and the plurality of resistors to be tested and the plurality of devices to be tested are in one-to-one correspondence and have the same critical dimension; the plurality of resistors to be tested are arranged in a stacked mode, an insulating layer is arranged between two adjacent resistors to be tested, the first ends of the plurality of resistors to be tested are electrically connected with the first test pads, the plurality of resistors to be tested are in one-to-one correspondence with the plurality of second test pads, and the second end of each resistor to be tested is electrically connected with a corresponding second test pad.
The wafer provided by the embodiment of the application has the following advantages:
in the wafer provided by the embodiment of the application, the electrical parameters of each device to be tested in the integrated circuit are obtained through each resistor to be tested in the wafer test structure, one end of each resistor to be tested in the wafer test structure is commonly connected, and the other end of each resistor to be tested is respectively led out and connected with the second test pad, so that each resistor to be tested shares one first test pad, the total number of the first test pads and the second test pads is reduced on the basis of ensuring that the resistance value of each resistor to be tested can be measured normally, the space occupied by the wafer test structure is reduced, and the space utilization rate of the cutting path is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a related art wafer test structure;
FIG. 2 is a schematic diagram of a wafer in an embodiment of the application;
FIG. 3 is a schematic diagram of a wafer test structure according to an embodiment of the present application;
FIG. 4 is a schematic diagram of the current flow of a wafer test structure according to an embodiment of the present application;
FIG. 5 is a schematic diagram showing the distribution of the first test pad and the second test pad according to an embodiment of the application.
Reference numerals illustrate:
100-wafer; 110-grains;
120-cutting the tracks; 200-wafer test structure;
210-a resistor to be measured; 220-an insulating layer;
230-a first test pad; 240-a second test pad;
250-substrate; 251-shallow trench isolation;
252-well; 260-a first wire;
270-a second wire; 280-a third wire;
300-test pads; 400-probe.
Detailed Description
Referring to fig. 1, in the related art, two ends of each resistor under test 210 in the wafer test structure 200 are respectively provided with a test pad 300, and the resistance value of the resistor under test 210 is calculated by testing the difference between the voltage values of the two test pads 300 at the two ends of the resistor under test 210 and the current value of any one test pad 300 of the two test pads 300 at the two ends of the resistor under test 210. The wafer test structure 200 requires more test pads 300, so that the wafer test structure 200 occupies larger space and the dicing street 120 has lower space utilization.
In view of the above technical problems, embodiments of the present application provide a wafer test structure and a wafer, in which one end of each resistor to be tested in the wafer test structure is electrically connected to a first test pad, the other end of each resistor to be tested is electrically connected to a second test pad, and one end of each resistor to be tested shares one first test pad, so that the total number of the first test pads and the second test pads is reduced, the space occupied by the wafer test structure is further reduced, and the space utilization rate of a dicing channel is improved.
In order to make the above objects, features and advantages of the embodiments of the present application more comprehensible, the technical solutions of the embodiments of the present application will be described clearly and completely with reference to the accompanying drawings. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Referring to fig. 2, the wafer 100 includes a die 110 and scribe lines 120, the scribe lines 120 being located outside the die 110. Illustratively, the wafer 100 includes a plurality of dies 110 with streets 120 located between each die 110, the streets 120 being contiguous with each die 110.
An integrated circuit (Integrated Circuit, abbreviated as IC) is disposed within die 110, and the integrated circuit is formed by deposition, development, etching, doping, thermal processing, and the like. The integrated circuit includes a plurality of elements (resistors, capacitors, transistors, diodes, etc.), stacks, interconnect lines, etc., and some of the structures in the integrated circuit are devices under test, and the devices under test are usually a plurality of devices under test, so as to monitor the process conditions of the integrated circuit by detecting electrical parameters (e.g., resistance values) of the devices under test.
The dicing street 120 is provided with a wafer test structure 200, the wafer test structure 200 includes a plurality of resistors to be tested 210, the plurality of resistors to be tested 210 in the wafer test structure 200 are in one-to-one correspondence with a plurality of devices to be tested in the integrated circuit, and the critical dimensions (Critical Dimension, abbreviated as CD) of each resistor to be tested 210 and the corresponding device to be tested are the same, so that the resistor to be tested 210 can represent the corresponding device to be tested, and the electrical parameters of the device to be tested can be obtained by testing the electrical parameters of the resistor to be tested 210. Wafer test structures 200 within scribe line 120 may be formed simultaneously with integrated circuits within die 110.
Referring to fig. 3, the wafer test structure 200 includes a plurality of resistors to be tested 210, the plurality of resistors to be tested 210 are sequentially stacked, and an insulating layer 220 is disposed between two adjacent resistors to be tested 210 to electrically isolate the adjacent two resistors to be tested 210, so as to avoid electrical connection between the resistors to be tested 210. Illustratively, the insulating layer 220 may be a silicon oxide layer (e.g., siO 2 Layer) or a silicon nitride layer (e.g. SI 3 N 4 A layer).
The resistor under test 210 may include one or more of an active region, a gate, a capacitor, or a metal layer (e.g., copper interconnect metal layer). Illustratively, one of the resistors 210 under test in the wafer test structure 200 is an active region, i.e., the resistance value of the active region is measured. As shown in fig. 3, the active region is disposed in a Well (Well) 252, and the Well 252 is disposed in a substrate 250.
The substrate 250 may be a P-type substrate, that is, the concentration of holes in the substrate 250 is greater than the concentration of free electrons, and the substrate 250 is mainly conductive with holes as carriers. The well 252 is formed by ion implantation within the substrate 250, the well 252 having a certain ion concentration. As shown in fig. 3, the active region is located in the well 252, and shallow trench isolation (Shallow Trench Isolation, STI for short) 251 is disposed in the active region in the circumferential direction. In the fabrication of the shallow trench isolation 251, the substrate 250 is patterned to form a recess in the substrate 250, typically using silicon nitride as a mask, and then oxide is deposited in the recess to isolate the active region.
Referring to fig. 4 and 5, first ends of the plurality of resistors under test 210 are electrically connected to the first test pad 230, respectively, and a second end of each of the plurality of resistors under test 210 is electrically connected to a second test pad 240. It is understood that the number of the first test pads 230 is one, and the number of the second test pads 240 is the same as the number of the resistors 210 to be tested.
Thus, as shown in fig. 4 and 5, by connecting the first ends of the resistors to be tested 210 together and making them share one first test pad 230, the number of first test pads 230 is reduced, so that the total number of first test pads 230 and second test pads 240 is reduced, and the space occupied by the wafer test structure 200 is reduced.
The first test pad 230 and each second test pad 240 are made of conductive materials, so that the wafer test structure 200 has conductivity. Illustratively, the first test pad 230 and each second test pad 240 are made of metal, for example, the first test pad 230 and each second test pad 240 are copper (Cu) pads or aluminum (Al) pads.
In one possible example, as shown in fig. 4, a first wire 260 is disposed in each insulating layer, the first wire 260 penetrates through the insulating layer where the first wire 260 is disposed, and two ends of the first wire 260 are respectively electrically connected to the first ends of two resistors under test 210 adjacent to the insulating layer where the first wire 260 is disposed, that is, the first ends of the resistors under test 210 are electrically connected by the first wire 260.
The first conductive line 260 is located in the overlapping area of the two adjacent layers of the resistors to be tested 210, so as to avoid the first conductive line 260 extending out of the projection area of the resistors to be tested 210, and reduce the space occupied by the wafer test structure 200. The first wires 260 may be aligned, and each first wire 260 may be a through silicon via (Through Silicon Via, abbreviated as TSV) or a Contact (CT), which is made of copper or tungsten (W).
For example, as shown in fig. 3 and 4, one first wire 260 is provided in the insulating layer 220 between the resistor to be measured 210 located at the uppermost layer and the resistor to be measured 210 located at the next upper layer. The upper end of the first wire 260 contacts with the first end of the uppermost layer of the resistor to be tested 210, the lower end of the first wire 260 contacts with the first end of the next upper layer of the resistor to be tested 210, and the first wire 260 is electrically connected with both the uppermost layer of the resistor to be tested 210 and the next upper layer of the resistor to be tested 210. The first conductive line 260 is located in the overlapping area of the uppermost layer of the resistor to be tested 210 and the next upper layer of the resistor to be tested 210, i.e. the orthographic projection of the first conductive line 260 in the vertical direction (Y direction shown in fig. 4) is located in the range of the orthographic projection of the uppermost layer of the resistor to be tested 210 and the next upper layer of the resistor to be tested 210.
With continued reference to fig. 4 and 5, when the wafer test structure 200 is attached to a test station, a current or voltage is provided through the first test pad 230 (not shown in fig. 4) by the probe 400 of the test station. The direction of the current in the wafer test structure 200 is shown in fig. 4, and the current flows into each resistor under test 210 under the top layer through the first conductive line 260.
It should be noted that, as shown in fig. 5, the wafer test structure 200 further includes a second wire 270 and a third wire 280, where the second wire 270 electrically connects the resistor under test 210 and the first test pad 230 on the top layer, so as to electrically connect the first end of each resistor under test 210 with the first test pad 230. The third wires 280 are arranged in a plurality, the plurality of third wires 280 are in one-to-one correspondence with the plurality of resistors to be tested 210, and each third wire 280 is connected with one resistor to be tested 210 and the second test pad 240 corresponding to the resistor to be tested 210. It is understood that the third conductive line 280, the resistor to be tested 210 and the second test pad 240 are in one-to-one correspondence.
Referring to fig. 5, the first test pad 230 and the plurality of second test pads 240 are located at the same layer as the resistor under test 210 located at the top layer of the plurality of resistors under test 210. As shown in fig. 5, the first test pad 230 and the second test pad 240 are located at the same layer as the uppermost layer of the resistor to be tested 210, i.e. the first test pad 230 and the second test pad 240 are located at the same layer as the uppermost layer of the resistor to be tested 210, so that the first test pad 230 and the second test pad 240 are exposed, thereby facilitating measurement and improving measurement accuracy.
In one possible example, the wafer test structure 200 includes five resistors under test 210 and four insulating layers 220. For convenience of description, as shown in fig. 4, the five resistors to be tested 210 are respectively defined as a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4 and a fifth resistor R5 from top to bottom, and the above five resistors are taken as examples for the embodiment of the present application and the following embodiments. The specific structure and the test principle of the wafer test structure 200 when the number of the resistors to be tested 210 is not five refer to the specific structure and the test principle of the wafer test structure 200 when the number of the resistors to be tested 210 is five.
The wafer test structure 200 includes a first test pad 230 and five second test pads 240. As shown in fig. 4 and 5, the second test PAD 240 electrically connected to the first resistor R1 is PAD1, the second test PAD 240 electrically connected to the second resistor R2 is PAD2, the second test PAD 240 electrically connected to the third resistor R3 is PAD3, the second test PAD 240 electrically connected to the fourth resistor R4 is PAD4, the second test PAD 240 electrically connected to the fifth resistor R5 is PAD5, and the first test PAD 230 is PAD6.
A second wire 270 is connected between PAD6 and first resistor R1. As shown in fig. 4 and 5, a first wire 260 is connected between the first resistor R1 and the second resistor R2, between the second resistor R2 and the third resistor R3, between the third resistor R3 and the fourth resistor R4, and between the fourth resistor R4 and the fifth resistor R5, respectively. Specifically, the first wire 260 between the first resistor R1 and the second resistor R2 is N1, the first wire 260 between the second resistor R2 and the third resistor R3 is N2, the first wire 260 between the third resistor R3 and the fourth resistor R4 is N3, and the first wire 260 between the fourth resistor R4 and the fifth resistor R5 is N4.
As shown in fig. 4 and 5, a third wire 280 is connected between the first resistor R1 and the PAD1, between the second resistor R2 and the PAD2, between the third resistor R3 and the PAD3, between the fourth resistor R4 and the PAD4, and between the fifth resistor R5 and the PAD5, respectively.
During measurement, the first test pad 230 is connected to the voltage output terminal of the test machine, and each second test pad 240 is connected to the ground terminal of the test machine. The test machine measures the current value on the second test pad 240, and calculates the measured resistance value of the resistor 210 to be tested corresponding to the second test pad 240 according to the voltage value and the current value of the voltage output terminal.
The test machine includes a plurality of probes 400, the probes 400 are respectively tied on the first test pad 230 and the second test pad 240 corresponding to any resistor to be tested 210, and the test machine provides voltage to the first test pad 230 and the second test pad 240 through the probes 400 and measures current.
For example, the plurality of probes 400 of the test machine are respectively tied to the first test pad 230 and all the second test pads 240, the voltage value (voltage value of the voltage output terminal) on the first test pad 230 is Vm, and the second test pad 240 is grounded, i.e. the voltage value on the second test pad 240 is 0. Currents on the PAD1, PAD2, PAD3, PAD4 and PAD5 are measured as I1, I2, I3, I4 and I5 respectively. Correspondingly, the resistance values of the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4 and the fifth resistor R5 are respectively: r1=vm/I1, r2=vm/I2; r3=vm/I3; r4=vm/I4; r5=vm/I5.
The wafer test structure 200 in the embodiment of the application can also obtain the resistance value of the first wire 260. Specifically, the first test pad 230 is connected to the current output end of the test machine, any second test pad 240 on a side of the first lead 260 to be tested away from the first test pad 230 is connected to the ground end of the test machine, for example, the second test pad 240 corresponding to the resistor 210 to be tested on the bottom layer among the plurality of resistors 210 to be tested is connected to the ground end of the test machine, so that the current at the current output end flows through the first lead 260 to be tested.
The test machine measures the voltage values on the second test pads 240 corresponding to the two resistors to be tested 210 adjacent to the first wire to be tested 260, and calculates the resistance value of the first wire to be tested 260 according to the difference between the current value of the current output end and the measured voltage value.
Illustratively, the resistance value of N1 may be obtained by: the first test PAD 230 is connected to the current output end of the test machine, the current value of the current output end is Ih, and the PAD3 is grounded. The test bench measures voltage values on PAD1 and PAD2 corresponding to the first resistor R1 and the second resistor R2 adjacent to each other by N1, for example, the voltage value of PAD1 is Vh, the voltage value of PAD2 is V1, and then the resistance value of N1 is: rn1= (Vh-V1)/Ih.
In the wafer test structure 200 provided by the embodiment of the application, a plurality of resistors to be tested 210 are stacked, and an insulating layer 220 is arranged between two adjacent resistors to be tested 210, so that each electron to be tested is electrically isolated; the first ends of the plurality of resistors to be tested 210 are electrically connected to the first test pad 230, and the second ends of the plurality of resistors to be tested 210 are electrically connected to a second test pad 240, respectively. By commonly connecting one end of each resistor to be tested 210, the other end of each resistor to be tested 210 is respectively led out and connected with the second test pad 240, so that each resistor to be tested 210 shares one first test pad 230, the total number of the first test pads 230 and the second test pads 240 is reduced on the basis of ensuring that the resistance value of each resistor to be tested 210 can be measured normally, thereby reducing the space occupied by the wafer test structure 200 and improving the space utilization rate of the dicing channel 120. Meanwhile, the plurality of resistors to be tested 210 are stacked in one test structure 200, so that the connection of the independent resistors to be tested 210 and the test pad is avoided, the plurality of resistors to be tested 210 are tested through one stacked test structure 200, and the occupied area of the resistors to be tested 210 is reduced.
The embodiment of the application also provides a manufacturing method of the wafer test structure, referring to fig. 1 to 5, the manufacturing method of the wafer test structure comprises the following steps:
step a: providing a substrate, wherein an active area is arranged in the substrate, and the active area is a resistor to be tested.
The wafer test structure 200 in the embodiment of the present application may measure the resistance value of an active region, and the active region may be disposed in a well 252, and the well 252 is disposed on a substrate 250. The substrate 250 may be a P-type substrate 250, and the well 252 is formed by ion implantation in the substrate 250. The active region is located within the well 252 and is circumferentially provided with shallow trench isolation 251.
Step b: and forming an insulating layer on the resistor to be tested by using a chemical vapor deposition process.
The insulating layer 220 is formed on the substrate 250 through a chemical vapor deposition (Chemical Vapor Deposition, simply referred to as CVD) process. An insulating layer 220 covers the active region to electrically isolate the active region. The material of the insulating layer 220 may include silicon oxide or silicon nitride.
After forming the insulating layer 220, a planarization process may be performed on a surface of the insulating layer 220 facing away from the substrate 250, so that each film layer formed on the insulating layer 220 is relatively flat. The upper surface of the insulating layer 220 is planarized by chemical mechanical polishing (Chemical Mechanical Polishing, simply referred to as CMP), for example.
In some possible examples, a first wire 260 is disposed in the insulating layer 220, and the first wire 260 penetrates through the insulating layer 220 and is used for electrically connecting the resistor to be tested 210 on both sides of the insulating layer 220. The first conductive line 260 may be a through silicon via or a contact hole, and is made of copper or tungsten.
Specifically, after the insulating layer 220 is formed, the insulating layer 220 is etched to form a hole structure, and the hole structure exposes the first end of the resistor 210 to be tested, i.e. the hole structure penetrates through the insulating layer 220. The orthographic projection of the resistor 210 under test onto the substrate 250 covers the orthographic projection of the hole-like structure onto the substrate 250. After the hole structure is formed, a conductive material is deposited within the hole structure, filling the hole structure with the conductive material to form the first conductive line 260.
Step c: and forming a metal layer on the insulating layer by using a physical vapor deposition process, wherein the metal layer is a resistor to be tested.
The metal layer may be a copper interconnection layer, and the metal layer is formed on the insulating layer 220 using a physical vapor deposition (Physical Vapor Deposition, abbreviated as PVD) process, and a first end of the metal layer is in contact with the first conductive line 260 within the insulating layer 220, thereby being electrically connected to the first conductive line 260.
After the metal layer is formed, a planarization process may be performed on a surface of the metal layer facing away from the substrate 250 to planarize the surface of the metal layer. For example, the upper surface of the metal layer is planarized by chemical mechanical polishing.
It can be appreciated that the metal layers and the insulating layers 220 in the wafer test structure 200 may be planarized, so that the surfaces of the metal layers and the insulating layers 220 facing away from the substrate 250 are relatively flat, and that one or more layers of the metal layers and the insulating layers 220 may be planarized to ensure the flatness of the critical film layers.
Repeating steps b and c until the desired number of resistors 210 to be tested are formed. That is, the steps of forming the metal layer and the insulating layer 220 are repeated until the desired number of resistors to be measured 210 are formed, and the resistors to be measured 210 and the insulating layer 220 are alternately stacked.
Then, a first test pad 230 electrically connected to the first end of each resistor to be tested 210 is formed, and a second test pad 240 in one-to-one correspondence with and electrically connected to the second end of each resistor to be tested 210 is formed. The first test pad 230 and each second test pad 240 are made of conductive materials, for example, the first test pad 230 and each second test pad 240 are copper (Cu) pads or aluminum (Al) pads. The first test pad 230 and the plurality of second test pads 240 are located on the same layer as the top layer of the plurality of resistors under test 210. As shown in fig. 5, the first test pad 230 and the second test pad 240 are located at the same layer as the uppermost layer of the resistor under test 210.
In the method for manufacturing the wafer test structure 200 provided by the embodiment of the application, the plurality of resistors to be tested 210 are stacked, and the insulating layer 220 is arranged between two adjacent resistors to be tested 210, so that the plurality of resistors to be tested 210 are tested through one stacked test structure 200, and the occupied area of the resistors to be tested 210 is reduced. Meanwhile, each resistor to be tested 210 shares one first test pad 230, so that the space occupied by the wafer test structure 200 is reduced and the space utilization rate of the dicing channels 120 is improved on the basis of ensuring that the resistance value of each resistor to be tested 210 can be measured normally.
In this specification, each embodiment or implementation is described in a progressive manner, and each embodiment focuses on a difference from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.
In the description of the present specification, reference is made to "one embodiment," "some embodiments," "an exemplary embodiment," "an example," "a particular instance," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.
Claims (16)
1. A wafer test structure, comprising: a plurality of resistors to be tested, a first test pad and a plurality of second test pads; the resistors to be tested are arranged in a stacked mode, and an insulating layer is arranged between two adjacent resistors to be tested;
the first ends of the plurality of resistors to be tested are respectively and electrically connected with the first test pads, the plurality of resistors to be tested are in one-to-one correspondence with the plurality of second test pads, and the second end of each resistor to be tested is electrically connected with a corresponding second test pad.
2. The wafer test structure of claim 1, wherein the first test pad and the plurality of second test pads are co-located with the top layer of the plurality of resistors under test.
3. The wafer test structure of claim 1, wherein the first test pad and the second test pad are copper pads.
4. The wafer test structure of claim 1, wherein the insulating layer is a silicon oxide layer.
5. The wafer test structure of claim 1, wherein the resistor under test comprises one or more of an active region, a gate, a capacitor, and a metal layer.
6. The wafer test structure of claim 5, wherein the active region is disposed within a well disposed within a substrate, the active region being circumferentially provided with shallow trench isolation.
7. The wafer test structure of any one of claims 1-6, wherein the first test pad is connected to a voltage output terminal of a test station and the plurality of second test pads are connected to a ground terminal of the test station;
the test machine measures the current value on the second test pad, and calculates the resistance value of the resistor to be tested corresponding to the second test pad according to the voltage value of the voltage output end and the current value.
8. The wafer test structure of any one of claims 1-6, further comprising a first wire disposed within each insulating layer, the first wire extending through the corresponding insulating layer and electrically connecting first ends of two of the resistors under test adjacent to the first wire.
9. The wafer test structure of claim 8, wherein the first conductive line is a through silicon via or a contact hole.
10. The wafer test structure of claim 9, wherein the first conductive line is located in a region of coincidence of two adjacent layers of the resistor under test.
11. The wafer test structure of claim 8, wherein the first test pad is connected to a current output end of a test machine, and any one of the second test pads on a side of the first wire to be tested away from the first test pad is connected to a ground end of the test machine;
the test machine measures voltage values on the second test pads corresponding to the two to-be-tested resistors adjacent to the to-be-tested first wire, and calculates the resistance value of the to-be-tested first wire according to the difference between the current value of the current output end and the measured voltage value.
12. The wafer test structure of claim 7, further comprising a second wire and a third wire;
the second wires are electrically connected with the resistor to be tested and the first test pad on the top layer, the third wires are arranged in a plurality, and each third wire is electrically connected with the second end of each resistor to be tested and the corresponding second test pad.
13. The manufacturing method of the wafer test structure is characterized by comprising the following steps:
step a: providing a substrate, wherein an active area is arranged in the substrate, and the active area is a resistor to be tested;
step b: forming an insulating layer on the resistor to be tested by using a chemical vapor deposition process;
step c: forming a metal layer on the insulating layer by using a physical vapor deposition process, wherein the metal layer is one resistor to be tested;
repeating the step b and the step c until the required number of the resistors to be tested are formed;
and forming a first test pad electrically connected with the first end of each resistor to be tested, and forming a second test pad in one-to-one correspondence with and electrically connected with the second end of each resistor to be tested.
14. The method of manufacturing a wafer test structure of claim 13, further comprising:
after forming an insulating layer on the resistor to be tested by using a chemical vapor deposition process, flattening the insulating layer by using chemical mechanical polishing;
and/or after forming a metal layer on the insulating layer by using a physical vapor deposition process, flattening the metal layer by using chemical mechanical polishing.
15. The method of claim 13, further comprising, after forming an insulating layer on the resistor to be tested using a chemical vapor deposition process:
etching the insulating layer to form a hole-shaped structure, wherein the hole-shaped structure exposes the first end of the resistor to be tested;
depositing a conductive material within the hole structure, the conductive material filling the hole structure to form a first wire.
16. The wafer is characterized by comprising a crystal grain and a cutting channel positioned outside the crystal grain, wherein an integrated circuit is arranged in the crystal grain, and a wafer test structure is arranged in the cutting channel;
the integrated circuit comprises a plurality of devices to be tested, the wafer test structure comprises a plurality of resistors to be tested, a first test pad and a plurality of second test pads, and the plurality of resistors to be tested and the plurality of devices to be tested are in one-to-one correspondence and have the same critical dimension;
the plurality of resistors to be tested are arranged in a stacked mode, an insulating layer is arranged between two adjacent resistors to be tested, the first ends of the plurality of resistors to be tested are electrically connected with the first test pads, the plurality of resistors to be tested are in one-to-one correspondence with the plurality of second test pads, and the second end of each resistor to be tested is electrically connected with a corresponding second test pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110779761.1A CN113517260B (en) | 2021-07-09 | 2021-07-09 | Wafer test structure, manufacturing method thereof and wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110779761.1A CN113517260B (en) | 2021-07-09 | 2021-07-09 | Wafer test structure, manufacturing method thereof and wafer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113517260A CN113517260A (en) | 2021-10-19 |
| CN113517260B true CN113517260B (en) | 2023-09-15 |
Family
ID=78067155
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110779761.1A Active CN113517260B (en) | 2021-07-09 | 2021-07-09 | Wafer test structure, manufacturing method thereof and wafer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113517260B (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05196714A (en) * | 1991-12-20 | 1993-08-06 | Sharp Corp | Laminated ceramic superconducting magnetoresistance element |
| US5712571A (en) * | 1995-11-03 | 1998-01-27 | Analog Devices, Inc. | Apparatus and method for detecting defects arising as a result of integrated circuit processing |
| JPH11214628A (en) * | 1998-01-23 | 1999-08-06 | Sony Corp | Method of testing wiring of semiconductor device, wiring testing circuit and wiring tester |
| JP2000021945A (en) * | 1998-06-30 | 2000-01-21 | Nec Corp | Method and circuit for measuring contact resistance of semiconductor integrated circuit |
| JP2002203882A (en) * | 2000-10-30 | 2002-07-19 | Hitachi Ltd | Method for manufacturing semiconductor device |
| KR20040008477A (en) * | 2002-07-18 | 2004-01-31 | 주식회사 하이닉스반도체 | Method for test a gate discontinuity of semiconductor device |
| JP2012113884A (en) * | 2010-11-22 | 2012-06-14 | Denso Corp | Current measurement apparatus |
| CN110392838A (en) * | 2017-03-07 | 2019-10-29 | 斯坦福国际研究院 | Equipment, system and method for integrated circuit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7253436B2 (en) * | 2003-07-25 | 2007-08-07 | Matsushita Electric Industrial Co., Ltd. | Resistance defect assessment device, resistance defect assessment method, and method for manufacturing resistance defect assessment device |
| KR100649015B1 (en) * | 2004-12-30 | 2006-11-27 | 동부일렉트로닉스 주식회사 | The pattern and its forming method for metering chain resist during test pattern layout |
-
2021
- 2021-07-09 CN CN202110779761.1A patent/CN113517260B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05196714A (en) * | 1991-12-20 | 1993-08-06 | Sharp Corp | Laminated ceramic superconducting magnetoresistance element |
| US5712571A (en) * | 1995-11-03 | 1998-01-27 | Analog Devices, Inc. | Apparatus and method for detecting defects arising as a result of integrated circuit processing |
| JPH11214628A (en) * | 1998-01-23 | 1999-08-06 | Sony Corp | Method of testing wiring of semiconductor device, wiring testing circuit and wiring tester |
| JP2000021945A (en) * | 1998-06-30 | 2000-01-21 | Nec Corp | Method and circuit for measuring contact resistance of semiconductor integrated circuit |
| JP2002203882A (en) * | 2000-10-30 | 2002-07-19 | Hitachi Ltd | Method for manufacturing semiconductor device |
| KR20040008477A (en) * | 2002-07-18 | 2004-01-31 | 주식회사 하이닉스반도체 | Method for test a gate discontinuity of semiconductor device |
| JP2012113884A (en) * | 2010-11-22 | 2012-06-14 | Denso Corp | Current measurement apparatus |
| CN110392838A (en) * | 2017-03-07 | 2019-10-29 | 斯坦福国际研究院 | Equipment, system and method for integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113517260A (en) | 2021-10-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8890560B2 (en) | Crack sensors for semiconductor devices | |
| US8237160B2 (en) | Probe pad on a corner stress relief region in a semiconductor chip | |
| TWI601222B (en) | Integrated circuit (ic) test structure with monitor chain and test wires | |
| US11854913B2 (en) | Method for detecting defects in semiconductor device | |
| CN108376653B (en) | System and method for electrical testing of Through Silicon Vias (TSVs) | |
| US6246075B1 (en) | Test structures for monitoring gate oxide defect densities and the plasma antenna effect | |
| US8217394B2 (en) | Probe pad on a corner stress relief region in a semiconductor chip | |
| US8853693B2 (en) | Test structure for determination of TSV depth | |
| US9322870B2 (en) | Wafer-level gate stress testing | |
| US8748295B2 (en) | Pads with different width in a scribe line region and method for manufacturing these pads | |
| CN203312265U (en) | Testing system | |
| US20070210306A1 (en) | Test pattern for measuring contact short at first metal level | |
| US20220359456A1 (en) | Semiconductor structure and methods for bonding tested wafers and testing pre-bonded wafers | |
| US9875964B2 (en) | Semiconductor device components and methods | |
| US20220359395A1 (en) | Method of testing wafer | |
| CN110335861B (en) | Semiconductor device and manufacturing method thereof | |
| US11121056B2 (en) | Semiconductor device and manufacturing method of the same | |
| US6300647B1 (en) | Characteristic-evaluating storage capacitors | |
| CN113517260B (en) | Wafer test structure, manufacturing method thereof and wafer | |
| KR102463139B1 (en) | Kelvin resistance test structure and method of manufacturing structure including the same | |
| JP4299349B2 (en) | Manufacturing method of semiconductor device | |
| US20140332952A1 (en) | Semiconductor structure and method for testing the same | |
| JP2000058614A (en) | Electrical-characteristic evaluation circuit for semiconductor device | |
| CN116741754A (en) | Metal insulating layer semiconductor structure, manufacturing method thereof and image sensor | |
| CN113889421A (en) | Screening method and apparatus for detecting deep trench isolation and SOI defects |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |