JP2002026100A - Semiconductor substrate and inspection method of electric circuit fabricating process and method for fabricating electric circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a TEG structure optimal for evaluating the defect level in the important components of an interconnection process, i.e., interconnect resistance, open circuit and short circuit defect, and through hole process, at a low cost and enhancing the location efficiency of a detected defect. SOLUTION: The semiconductor device comprises a meandering pattern 1 for detecting defective interconnect resistance formed on an electric circuit substrate, and a pattern 3 for detecting defective conduction of through hole formed in the gap of the pattern 1 for detecting defective interconnect resistance while being insulated electrically therefrom.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a semiconductor device,
The present invention relates to a semiconductor substrate for manufacturing a semiconductor product such as an electric circuit device such as a display device such as an electric circuit substrate, a CCD, or a TFT, a method of inspecting a manufacturing process of the electric circuit device, and a method of manufacturing the electric circuit device.

[0002]

2. Description of the Related Art Speaking of a semiconductor manufacturing process comprising several hundred steps, performing a foreign substance inspection for every step requires an enormous inspection time and cost. And SEM appearance inspection. Conventionally, in this inspection process, the number and size of foreign particles and the coordinates of the foreign particles on the wafer surface are measured,
The history is recorded in a database, and based on the history data, it is possible to monitor for sudden abnormalities in manufacturing equipment and to constantly monitor the suppression of foreign matter levels. By comparing the failure mode and failure position data to be performed and analyzing the history of the inspection results, it is possible to evaluate the fatality (probability of a product failure) of a defect in each process. Then, countermeasures have been taken by specifying a dust source and a defect mode in a process that is statistically fatal and suppressing the occurrence thereof.

As a conventional example, "Integra
ted Circuit Manufacturabi
lite, IEEE PRESS, P26-P29 ", which has two opposing comb-tooth patterns for short-circuit detection.
EG, TE having meandering pattern for detecting wiring resistance failure
G, and a mixed structure of a comb pattern and a meandering pattern are disclosed (conventional example 1). These TEGs are mixed with product chips of a product wafer, or TEGs are mounted on the entire surface of the wafer. Since the TEG area is not a product,
Economic losses due to TEG must be minimized. On the other hand, in order to monitor the defect, the defect occurs with a certain finite probability (defect density = defect occurrence frequency / area). The area needs to be large enough.

On the other hand, in order to reflect the TEG probe inspection results in process improvement, short-circuits and disconnection points are specified, and physical failures such as surface observation, cross-section observation, material analysis, and the like are specified to identify the failure generation mechanism. There is a need to. In the case of Conventional Example 1, a defect having a large dimension can be supplemented by an optical surface inspection. However, when the defect size becomes about 0.3 μm or less, a defective portion may be specified due to insufficient inspection sensitivity. It becomes difficult. Therefore, the structure and inspection method of TEG for the purpose of improving the capture rate of this defective part is described in "Microelecronic Test Structures for Rapid Automat
ed Contactless Inline Defect Inspection, IEEE Tran
sactions on Semiconductor Manufacturing, Vol.10,
No. 3, August, 1997 "(conventional example 2). This TEG has a structure in which a plurality of electrically insulated linear patterns are arranged between meandering wiring resistance detecting wiring patterns, and the charged state of the pattern to be inspected is used as potential contrast image information using an SEM type inspection apparatus. It utilizes a method of detecting, and discloses that a disconnection and a short circuit of one wiring layer are monitored in a small area.

Japanese Patent Application Laid-Open No. 11-330181 discloses a TEG structure in which a wiring pattern for detecting a short-circuit defect by a potential contrast method is provided in a gap between comb-shaped wirings (conventional example 3). . In addition, JP-A-5-144
Japanese Patent Application Laid-Open No. 901 discloses a method for detecting a short circuit and a disconnection by utilizing a potential contrast caused by ion beam irradiation (conventional example 4). Using a conventional two comb-teeth facing type TEG for detecting a short-circuit defect and a meandering pattern for detecting a disconnection defect, a focused ion beam (hereinafter referred to as FIB) is used.
) To generate a potential contrast image, and at the same time, cut or connect the TEG by the FIB to shorten the time for identifying a defective portion.

[0006]

However, in all of the conventional examples, all processes such as wiring resistance, disconnection and short-circuit defect, and through-holes (holes connecting upper and lower wiring layers) which are important elements in the wiring process are performed. However, it has not been possible to provide the trapping efficiency of the defects, the improvement of the search efficiency of the defect portion, and the reduction of the TEG occupied area, which does not realize the optimal TEG structure.

[0007] An object of the present invention is to solve the above problems.
Defect capture efficiency and search for defect locations in consideration of all processes such as wiring resistance, disconnection and short defects, and through holes (holes connecting the upper and lower wiring layers), which are important elements in the wiring process in the electric circuit manufacturing process Efficiency,
And a semiconductor substrate provided with a test (including inspection) pattern (TEG structure) of an electric circuit manufacturing process capable of reducing the area occupied by the TEG and controlling the manufacturing yield at a low cost, and an electric circuit manufacturing process An inspection method is provided. Further, another object of the present invention is to quickly detect defects at a low cost and in a short period of time, to quickly identify the cause, and to provide early feedback to the manufacturing process, thereby eliminating losses due to low yield in a short period of time. It is an object of the present invention to provide a method for manufacturing an electric circuit device that can be used.

[0008]

In order to achieve the above object, the present invention provides a pattern for detecting a meandering wiring resistance defect,
A test pattern (test pattern / test pattern) for an electric circuit manufacturing process, which is disposed in the gap between the wiring resistance defect detection patterns and has an electrically insulated through-hole conduction defect detection pattern.
(A monitoring pattern) is provided in a partial region in a semiconductor substrate for manufacturing a semiconductor product. The present invention also provides a test pattern for an electric circuit manufacturing process, comprising: a comb-shaped short-circuit detection pattern; and a through-hole failure detection pattern that is disposed in a gap between the short-circuit detection patterns and is electrically insulated. (Inspection pattern / monitoring pattern) is provided in a partial region in a semiconductor substrate for manufacturing a semiconductor product. Further, the present invention is a semiconductor substrate, characterized in that in the test pattern of the electric circuit manufacturing process, an electrically insulated short-circuit detection pattern is provided as a part of the through-hole conduction defect detection pattern.

Further, the present invention provides a test pattern for an electric circuit manufacturing process having a pattern for detecting a wiring resistance defect and a pattern for detecting a conduction defect in a through-hole connected to the pattern for detecting a wiring resistance defect, for manufacturing a semiconductor product. A semiconductor substrate provided in a partial region within the semiconductor substrate. Further, the present invention is a semiconductor substrate, characterized in that in the test pattern of the electric circuit manufacturing process, an electrically insulated short-circuit detection pattern is provided in a gap between the wiring resistance defect detection patterns. In addition, the present invention manufactures a semiconductor product using a test pattern of an electric circuit manufacturing process including a comb-shaped short-circuit detection pattern facing thereto and a through-hole conduction failure detection pattern connected to the short-circuit detection pattern. A semiconductor substrate provided in a partial region in the semiconductor substrate.

[0010] The present invention also relates to a meandering wiring resistance failure detecting pattern provided on an electric circuit board, which measures the electrical resistance by a stylus or a charged particle beam. A resistance inspection step of obtaining a potential contrast generated by irradiating the wiring and inspecting the resistance of the wiring, and arranging the wiring resistance defect detection pattern on the electric circuit board in a gap between the meandering portions and electrically insulating the wiring. The resistance of the through hole is measured for the through hole conduction failure detection pattern, or the potential contrast generated by irradiating the charged particle beam to the through hole conduction failure detection pattern is detected to detect the defect. And a defect detection step.

Further, in the present invention, in the defect detecting step, a part of the through hole conduction defect detecting pattern may include:
The method includes a step of acquiring a potential contrast image generated by irradiating the charged particle beam and detecting a short-circuit defect. In addition, the present invention measures the electrical resistance by touching a meandering wiring resistance failure detection pattern provided on an electric circuit board, or irradiates the charged resistance particle beam to the wiring resistance failure detection pattern. A resistance inspection step of obtaining the potential contrast generated by the above and inspecting the resistance of the wiring, and a through-hole for the through-hole conduction failure detection pattern connected to the wiring resistance failure detection pattern on the electric circuit board. A defect detection step of measuring a resistance or detecting a defect by acquiring a potential contrast generated by irradiating a charged particle beam to the through hole conduction defect detection pattern. This is a process inspection method.

In the present invention, the defect detection step is preferably performed by irradiating a charged particle beam to an electrically insulated short-circuit detection pattern formed in a gap between the wiring resistance defect detection patterns. The method includes a step of detecting a short-circuit defect by acquiring a potential contrast image. Further, according to the present invention, the electric resistance is measured by touching the opposing comb-shaped short-circuit detection pattern provided on the electric circuit board, or the charged particle beam is irradiated on the short-circuit detection pattern. A short-circuit inspection step of acquiring a potential contrast caused by the inspection and inspecting the short-circuit, and measuring the resistance of the through-hole for the through-hole conduction failure detection pattern connected to the short-circuit detection pattern on the electric circuit board, Or a defect detection step of detecting a defect by irradiating a charged particle beam to the through hole conduction failure detection pattern to detect a defect. is there. Further, the present invention provides an electric circuit device which quantitatively evaluates a defect level of an electric circuit manufacturing line by using the inspection method of the electric circuit manufacturing process and determines whether or not the performance of the electric circuit manufacturing line is satisfied. And a method for manufacturing an electric circuit device.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An electric circuit manufacturing process according to the present invention and a TEG for detecting a defect formed on an electric circuit board for evaluating process characteristics in the manufacturing line.
(Test Element Group) An embodiment of a pattern, a method of inspecting a manufacturing process using the pattern, and a manufacturing process of an electric circuit board will be described with reference to the drawings. By the way, in recent years, semiconductor devices
As miniaturization and multi-layering progress, it is extremely difficult to ensure a high yield of products. Also in the production of a display such as a TFT, an increase in area and an increase in the number of pixels have progressed, and it has become difficult to secure a production yield. On the other hand, product cycles are being shortened, and when mass production of new products is started, it is necessary to rapidly increase the yield, reduce manufacturing costs, and bring new products to market early. Factors that reduce the yield include characteristic defects due to device variations, design defects such as logic circuit defects and mask defects, and the like.
There are defects caused by foreign matter adhering during the manufacturing process and defects caused by improper process conditions.

As described above, with the recent shortening of the semiconductor product cycle, in order to enhance the market competitiveness of products,
Shortening the product development period is an essential requirement. However, as described above, due to the increase in the number of semiconductor manufacturing processes, it takes several tens of days from product input to electrical characteristic inspection at the time of product completion, so countermeasures will be delayed. In product development, a method is adopted in which a common process is divided for each block, an electrical inspection is performed in this block, the result is fed back to the process, and the process of the block is established early. A sample for monitoring this block is provided by TEG (Test E
element Group), short loop monitor,
Or, it is called a test structure.

In the embodiment according to the present invention, short-circuiting and disconnection (including high resistance, the same applies hereinafter), which are defects in the wiring process.
The above TEG for the wiring process monitor for detecting
And its use. In particular, in the development of the TEG according to the present invention, reducing the occupied area without lowering the detection sensitivity has become an important issue. In the embodiment of the present invention, the wiring layers as a sample formed as an electric circuit substrate such as a wafer are referred to as M1 layer and M2 layer, for example, counting in order from the diffusion layer side.
The through hole connection layer between the layers is referred to as a TH1 layer. Also, an example in which the TEG (TEG pattern) in the embodiment of the present invention is configured by the M1, the TH1, and the M2 layers will be described, but the application range is not limited to this.

(Embodiment 1) Embodiment 1 according to the present invention will be described with reference to FIGS. First, FIG. 1 is a diagram showing a TEG structure for detecting a wiring resistance defect, a short-circuit defect, and a through-hole conduction defect according to the first embodiment of the present invention. First, a wiring resistance defect detecting pattern 1 having a desired wiring width and wiring length is meandered in the M1 layer, and the wiring gap in the longitudinal direction of the wiring resistance defective detecting wiring pattern 1 (denoted as Y direction in FIG. 1). And a plurality of short-circuit detection patterns 2
Are arranged in the M1 layer so that the distance between adjacent wirings becomes a desired size. The short-circuit detection pattern 2 needs to set the wiring length in the Y-direction in consideration of forming a continuous through hole by being connected to the TH1 layer and the M2 layer in the subsequent process. These wiring patterns 1,
2 is an Al pattern formed by dry-etching Al formed on the interlayer insulating film 4 (strictly, a multilayer wiring structure in which the upper and lower layers of Al are formed of a thin film of TiN or Ti), or a wiring groove in the interlayer insulating film 4. After forming, a wiring (damascene wiring) formed by embedding Cu or the like by sputtering or plating,
Use the desired wiring formation process to be monitored. The damascene wiring is a technique in which a hole is buried in a via (contact) hole or a groove of a wiring by forming a film, and an excess deposited portion is removed by polishing to form a buried hole. In the case of a semiconductor process, a wiring interval and a wiring width are generally set to typical dimensions of a wiring process to be monitored, and are set to about 0.1 to 1 μm. In order to monitor the frequency of occurrence for each defect size, a plurality of TEG patterns are provided with wirings having different wiring intervals.

Next, an interlayer insulating film 4 is formed on the M1 layer.
A through hole conduction failure detection pattern 3 for connecting the short circuit detection patterns 2 in a chain is formed. TH1
As a method of forming the layer and the M2 layer, a hole for a through hole is formed in the interlayer insulating film 4 formed on the M1 layer, and the hole is buried with a metal material such as W, Al, or Cu. Back or CMP (Chemical
A TH1 layer is formed by performing Mechanical Polishing (chemical mechanical polishing).
A process for forming two layers in the same manner as the M1 layer is used. As another method, holes and wiring grooves are formed by dry etching in the interlayer insulating film 4 formed on the M1 layer, and processing such as formation of a barrier metal on the side walls of the holes and wiring grooves is performed.
After that, a process (dual damascene) of embedding the both at the same time with a metal material by sputtering, electrolytic plating, or CVD and removing the surplus portion by CMP is used. In this dual damascene, a groove is formed in a via (contact) hole and a portion to be a wiring in advance, filling is performed by forming a film, and then an unnecessary portion is removed by polishing to fill the hole. And wiring at the same time.

As described above, the TE of the first embodiment
As the G pattern, a wiring resistance defect detecting pattern 1 having a desired wiring width and a desired wiring length is meandered as an M1 layer, and a plurality of wiring patterns are formed in parallel with the longitudinal gaps of the wiring resistance defective detecting wiring pattern 1. Of the short-circuit detection pattern 2 of
The wiring is formed so that the space between adjacent wirings has a desired size. Further, as the TH1 layer and the M2 layer, through-hole conduction failure detecting patterns 3 are formed by connecting the short-circuit detecting patterns 2 in a chain between the ends in the longitudinal direction. In other words, the through-hole conduction failure detecting pattern 3 is formed in the TH1 layer and the M2 layer, which are the upper layers of the M1 layer, by being connected in a chain between the ends of the short-circuit detecting patterns 2 in the longitudinal direction. Therefore, both short-circuit failure and through-hole conduction failure can be detected together, and the area occupied by the TEG pattern can be significantly reduced, so that the time required for the TEG pattern inspection can be shortened. Many products such as semiconductor chips can be produced from a single substrate.

Next, an evaluation method, an evaluation device, and a detection principle of each wiring will be described with reference to FIGS. FIG.
FIG. 3 is a diagram showing a wiring resistance measuring method and a short-circuit defect inspection method according to the first embodiment of the present invention. First, a method for measuring the wiring resistance will be described. As shown in FIG. 2, when the M1 layer is formed, for example, electric field etching or FIB
The resistance is measured by connecting the resistance measuring device 15 to the wiring resistance failure detection pattern 1 via the probe 14 whose tip is thinned by using (Focused Ion Beam) processing or the like. When the contact resistance between the wiring resistance defect detection pattern 1 and the probe 14 affects the resistance measurement, the resistance is measured by the 4-short probe method, and otherwise, the ordinary 2-short probe method may be used. The probe 14 may be a direct contact needle as shown in FIG.
Normally, a stylus pad (not shown) electrically connected to the end of the wiring resistance failure detecting pattern 1 with a low resistance is provided in the M1 layer in advance, and the resistance is measured through this. This stylus pad may be formed of the M2 layer connected to the end of the wiring resistance failure detection pattern 1 in the M1 layer. In this case, the resistance can be evaluated by using the probe 14 as a stylus with a stylus pad formed of the M2 layer. When the resistance value measured by the resistance measuring device 15 is higher than a desired value, a disconnection or a high resistance defect is present, or the bulk resistance value is increased due to impurities contained in the wiring material. There is a possibility that further analysis is needed.

Next, a method for inspecting a short-circuit defect will be described. When the M1 layer is completed, the charged particle beam 1
By detecting an abnormality in the potential contrast image signal obtained by scanning the line 7, the presence or absence of a defect can be discriminated, and the short-circuit defect 8 can be specified. An inspection apparatus for acquiring the potential contrast image signal will be described in detail. FIG.
1 is a diagram showing an inspection device using a charged particle beam according to a first embodiment of the present invention. This inspection device is an inspection device body 10
0, charged particle optical system 11 in the inspection apparatus main body 100
5, a sample stage 112, a control system 101 such as an electric signal measuring device, and a host computer 102 that controls a user interface. Further, the host computer 102 is connected to the network 103 and can communicate with the electrical inspection device 104 and the visual inspection device 105 or a database 106 for storing these inspection data.
Analysis system 10 that analyzes the history of foreign matter and defects
7 can transmit and receive data.

The electrical inspection device 104 automatically obtains an electrical inspection result (an electrical inspection result of the TEG) by applying a voltage to a contact pad of the TEG to be inspected, and stores the result in the database 106. It is also called a tester or auto prober. The appearance inspection device 105 is configured by a foreign matter inspection device, a wiring pattern inspection device (for example, configured by an optical wiring pattern inspection device, an SEM appearance inspection device, or the like), and the like. Inspection of the shape of wiring, such as foreign matter deposited on the semiconductor substrate) or pattern failure, and data on the generation process, position coordinates of the defect, the feature amount of the defect, and the category of the defect (type of foreign substance or defect) And stored in the database 106.

Then, in the defect analysis system 107 composed of a CPU or the like, in order to determine whether the cause of the electrical failure of the TEG is a foreign substance or a defective pattern, the coordinates of the TEG pattern, the foreign substance and Since it is necessary to collate with the coordinates at which the wiring failure has occurred, communication with the database 106 storing the inspection results of the wiring shape inspected by the visual inspection device 105 is made in advance. That is, the defect analysis system 107 generates a database 106 based on, for example, CAD information that forms a TEG pattern obtained from a CAD system (not shown) via a network.
Of the TEG pattern stored in the camera and the visual inspection device 10
5 and collated with the coordinates at which the foreign matter or wiring failure has occurred and stored in the database 106, it is possible to determine whether the electrical failure of the TEG is due to a foreign matter or pattern failure. Become.

Further, in the defect analysis system 107 for analyzing the history of foreign matter and defects, the appearance inspection apparatus 105 analyzes the history of the appearance inspection results stored in the database 106 for each process, and generates the results in each process. It is possible to discriminate a defect from a defect generated in an earlier process. Further, the defect analysis system 107 is based on the database stored in the database 106 and tracks the process of generating a foreign substance or the like inspected by the visual inspection device 105, and is provided by the visual inspection device (including the defect classification device) 105. The type (category) of the foreign matter or defect, the electrical inspection result of the TEG inspected by the electrical inspection device 104, and the coordinates of the foreign material or the pattern defect inspected by the visual inspection device 105 are compared with each other to check the electrical characteristics of the TEG. In addition to analyzing the cause of the failure, the appearance inspection device 105 examines, for example, a specific foreign matter or a pattern failure detected based on the feature amount to determine how much the fatal defect occurs. It is also possible to measure the degree of fatal influence of foreign matter or pattern failure.

As described above, the defect analysis system 1
According to 07, it is effective to narrow down the targets to be inspected by the inspection device using the charged particle beam according to the first embodiment of the present invention in advance. That is, the defect analysis system 107 determines that the electrically defective T
Of the EGs, only patterns of unknown origin that have not been found as foreign substances or pattern defects by the visual inspection device 105 are narrowed down (extracted), and information (eg, coordinate data) on the narrowed down TEGs is stored in the database 10.
6, the host computer 102
Can be provided. Therefore, the host computer 102, which is an inspection device using a charged particle beam, only needs to inspect the narrowed range of the TEG, so that the inspection time based on the charged particle image corresponding to the potential contrast can be reduced. become.

First, the inspection apparatus main body 100 will be described. A sample (for example, a semiconductor substrate such as a wafer) 1 is placed in a sample chamber 110 maintained in a vacuum by a vacuum exhaust device (not shown).
A sample stage 112 for mounting the sample 11 is provided. As the sample stage 112, an XY stage, an XYZ stage, or a combination of these stages with a rotary stage or a tilt stage is used. A charged particle housing 113 is connected to the sample chamber 110, and the charged particle housing 113 is also evacuated by a vacuum exhaust device (not shown). The charged beam housing 113 is composed of a charged particle source 114 for emitting the charged particle beam 17 and a charged particle optical system 115 for focusing the generated charged particle beam 17. The charged particle source 114 uses a thermionic emission type (tungsten hairpin filament or lanthanum hexaboride point cathode) or a field emission type when the charged particle beam 17 is an electron beam, and a liquid metal such as Ga when it is an ion. An ion source, a plasma ion source such as Ar, a field emission type rare gas ion source such as He, or the like is used. The charged particle optical system 115 includes an extraction electrode, an acceleration electrode, a stigma deflection coil, an electrostatic lens, a magnetic field lens, and the like, and controls scanning, irradiation, and non-irradiation of the focused charged particle beam 17.
The acceleration voltage of the charged particle beam 17 is usually several hundred V to several hundred k.
About V, the current of the charged particle beam 17 is several pA to several tens μm.
A varies. The diameter of the charged particle beam 17 is usually 1 n
Focusing is performed at about m to 100 nm, but is not limited to this. Secondary electrons 116 or reflected electrons 116 ′ generated when the surface of the sample 111 is irradiated with the charged particle beam 17.
To the charged particle detector 117 to perform current amplification,
After the image processing is performed by the host computer 102, the image is displayed on the monitor 102a. With this image, the potential contrast can be obtained. In order to avoid dielectric breakdown due to charging of the sample 111, the acceleration voltage is usually reduced to about several hundred V to 1 kV for observation, or a neutralizing charged particle beam (shown in FIG. Is installed in the sample chamber 110. Note that the current value of the charged particle beam 17, the acceleration voltage of the charged particle beam 17, and the sample 11 based on the optical axis of the charged particle optical system 115 are displayed on the monitor screen 102a of the host computer 102.
1, the coordinate value (address value) of the TEG and the coordinate value (address value) of the chip can be monitored.

Further, it is possible to mount a stylus means on this inspection apparatus.
A probe 14 to be brought into contact with an EG detection pattern or a stylus pad, and a driving means 118 for driving the probe
And These probe 14 and driving means 118
A part of the electrical inspection apparatus 104 including the resistance measuring device (including the applied voltage source) 15 is also configured. The driving means 118 can control any XYZ within the field of view of the scanned electronic image.
A stage that can drive the probe 14 is provided at a position in the direction, and the drive source can be controlled with a resolution of micrometer or submicrometer using an electric motor, a piezo element, or the like. It is also possible to mount a means (not shown) for detecting contact based on a change in screen contrast caused by the contact and a change in current flowing through the probe 14. The drive means 118 and the host computer 102 are linked, and the operator can use a mouse or a drive button displayed on the monitor screen via an interface device such as a joystick 102d while watching the monitor screen 102a of the host computer 102. The probe 14 can be moved by clicking at 102b.

Next, the principle of defect detection based on the potential contrast will be described with reference to FIG. FIG. 4 is a diagram illustrating the principle of the potential contrast. First, a test object (sample) 111 is a semiconductor wafer in which a TEG pattern including an interlayer insulating film 4 and a conductor 10 according to the present invention is formed on a grounded Si substrate 9. When the charged particle beam 17 is irradiated from the charged particle optical system 115 to the conductor 10 of the TEG pattern, secondary electrons 21 are emitted from the conductor 10 and charging occurs. When the conductor 10 and the Si substrate 9 are electrically insulated completely, as shown in FIG. 4A, the conductor 10 is (1) grounded via the probe 14, or (2)
Only a small amount of secondary electrons 21 are emitted as compared with the case where the substrate is electrically connected to the grounded Si substrate 9 (connected to the substrate 9 by an internal circuit). This is due to the charging phenomenon of the conductor 10, which is because when the secondary electrons 21 are emitted and no electrons are supplied from the ground, the conductor 10 is positively charged and the secondary electron emission efficiency is reduced. . The difference in the emission amount of the secondary electrons 21 is detected by the charged particle detector 117, input to the host computer 102, and displayed on the monitor screen 102 a as a scanned image of the charged particle beam 17. Bright-dark contrast, that is, potential contrast can be obtained. this is,
Even when there is a difference in the volume of the conductor 10 as in (3), the potential contrast can be detected because the charge levels are different.

Next, a description will be given of defect recognition by a charged particle beam inspection apparatus utilizing the principle of generating potential contrast. FIG. 4B shows a method of recognizing a defect by a (1) one-dimensional line scan signal processing method. When the volume of the short-circuit detection wiring 2 is sufficiently small as compared with the wiring resistance failure detection pattern 1, the former is clear in the normal part, the latter has a dark contrast, and the part where the short-circuit defect 8 exists has a difference in brightness. Decrease. (A) is a charged particle detector 11
7 shows the signal of the normal part detected by 7
(B) is a signal waveform when there is an abnormal part detected by the charged particle detector 117. Therefore, in an image processing unit (not shown) of the host computer 102,
By taking the difference between the signal intensities of (a) and (b) or detecting the irregularity of the signal period of (b), the frequency of occurrence of short-circuit defects 8 can be quantified, and the short-circuit location can be specified. It is also possible to store an enlarged image of the specified portion as a charged beam image in an image memory (not shown) by specifying the image on a monitor screen, for example.
Further, it is also possible to display and output it on the monitor screen 102a, for example. Of course, the position data and the occurrence frequency data of the specified short-circuit point of the TEG are stored in the database 1.
06 can be stored in association with the chip and the TEG.

As another method, as shown in FIG. 4C, (2) two-dimensional images detected by the charged particle detector 117 are sequentially taken in, and the host computer 10
In the second image processing unit (not shown), it is also possible to make the defect portion obvious by comparing the image with the normal part, and the host computer 102 outputs the made defect portion to, for example, a monitor screen 102a. Is also possible. In order to improve the inspection sensitivity, it is effective to ground the wiring resistance failure detection pattern 1 via the probe 14 or to ground in advance in an internal circuit to enhance the contrast. Further, when it is desired to actually measure the resistance value of the short-circuit defect 8, as shown in FIG. 2, it is also possible to directly touch the probe 14 with the probe 14 in the electrical inspection device 104 and measure the resistance with the resistance measuring device 15, This measurement can be stored in the database 106.

Next, a method of measuring the resistance of a through hole and detecting a defect will be described with reference to FIGS. FIG.
FIG. 4 is a diagram illustrating a through-hole resistance measuring method according to the first embodiment of the present invention. A circuit is formed in a chain by the short-circuit detection pattern 2 of the M1 layer and the through-hole conduction failure detection pattern 3 formed of the TH1 and M2 layers. Electrical inspection device 104
In, the end of this chain is touched by a probe and measured by a resistance measuring device. This probe 14
May be electrode pads (not shown) formed in advance on both ends of the pattern. Further, in the electrical inspection apparatus 104, similarly to the above, it is also possible to detect a short circuit between the resistance measurement wiring pattern of the M1 layer and the through hole conduction failure detection pattern 3 by measuring the resistance. . FIG. 6 is a diagram illustrating a through hole defect detection method according to the potential contrast method according to the first embodiment of the present invention. If one side of the through hole conduction failure detection pattern 3 is grounded, or if there is a sufficient difference in the capacitance of the pattern on both sides of the disconnection defect 12, a potential contrast image can be obtained at this location,
By performing physical analysis such as SEM observation and cross-sectional analysis of this location, it is possible to quantify the frequency of occurrence of through-hole failures, estimate the defect occurrence mechanism, and reflect it in process measures.

(Embodiment 2) Embodiment 2 according to the present invention will be described with reference to FIGS. FIG. 7 is a diagram showing a TEG structure for detecting a wiring resistance failure, a short circuit, and a through-hole conduction failure according to the second embodiment of the present invention. First, a wiring resistance defect detection pattern 1 having a desired wiring width and wiring length is arranged in a meandering manner by the M1 layer, and a plurality of short-circuit detection patterns 2 ′ are arranged in parallel with the gaps of the wiring resistance defect detection pattern 1. Are arranged in the M1 layer so that the distance between adjacent wirings becomes a desired size. This short-circuit detection pattern 2 ′ has no restriction on the wiring length for forming a chain-like through hole as in the first embodiment. As in the first embodiment, when the M1 layer is completed, the wiring resistance of the resistance failure detection pattern 1 is measured by the probe 14 and the resistance measuring device 15.
, And the short-circuit defect 8 is detected by the same potential contrast method as in the first embodiment (not shown). next,
A columnar through-hole defect detection pattern 3 ′ is formed of a TH1 layer so as to be connected to the wiring resistance defect detection pattern 1. The defect inspection of the through hole is performed by scanning the charged particle beam 17 emitted from the charged particle optical system 115 as in the first embodiment. Resistance failure detection pattern 1
Is that the capacity is sufficiently large as compared with one through-hole, so that the normal part has a bright contrast, and the non-opening of the through-hole or the high resistance defective part has a dark contrast, so that the defective part can be specified in the host computer 102. Become. Further, similarly to the first embodiment, it is also possible to directly probe the defective portion and measure the resistance.

On the other hand, in the case of a dual damascene process,
Since there is a case where the formation of the TH1 layer and the formation of the M1 layer are integrated processes (for example, a process of forming a wiring groove first and then forming a through hole), it is impossible to form only the TH1 layer. Becomes FIG. 8 is a diagram showing a dual damascene-compatible TEG structure according to the second embodiment of the present invention. The M1 layer is the same as that of FIG. 7, and here, shows a structure in which a wiring pattern 3 ″ for detecting through-hole defects with wiring is formed by the TH1 layer and the M2 layer in order to support the dual damascene process. In the wiring pattern 3 ″ for detecting through-hole defects with wiring, the wiring portion may have a longitudinal direction in the X direction or a direction in the Y direction. The defect detection of the through hole is performed by the potential contrast method as described above.

FIGS. 9 and 10 show a TEG structure in which the function of the M1 layer is limited to wiring resistance measurement or short-circuit detection.
Shown in FIG. 9 is a diagram showing a TEG structure for detecting a wiring resistance failure and a through-hole conduction failure according to the second embodiment of the present invention. In this figure, short-circuit defect detection of the M1 layer is omitted.
FIG. 10 is a view showing a TEG structure for detecting a short-circuit defect and a through-hole conduction failure. In order to detect a short-circuit defect, a short-circuit defect detection wiring pattern 2 ″ in which comb teeth are opposed by the M1 layer is formed.

(Embodiment 3) Embodiment 3 according to the present invention will be described with reference to FIGS. FIGS. 11 and 12 show a TEG for detecting a wiring resistance defect, a short-circuit defect, and a through-hole conduction defect according to the third embodiment of the present invention.
It is a figure showing a structure. In the third embodiment, the M2 layer also has a structure in which the wiring resistance failure detection pattern 1 is formed, and the sensitivity for capturing the disconnection or the high resistance failure is substantially the same in the area where the short-circuit defect is captured. Is doubled.
Also, by measuring the resistance between the wiring pattern for resistance measurement of the M2 layer and the pattern for detecting through-hole conduction failure 3 in the same manner as in the first and second embodiments, it is also possible to detect a short circuit between the two. With almost the same area, the efficiency of capturing short-circuit defects is doubled. Further, as shown in FIG.
The wiring resistance failure detection pattern 1 of the layer may be a comb-shaped short-circuit detection pattern 2 ″.

The effects of the above-described embodiment of the present invention will be described with reference to FIG. That is, in the case of the present invention, when the area of the TEG in which the number of detected defects becomes equal to that of the conventional example is compared, it is possible to reduce the area by 1/3 to 1/2 of the conventional example. In addition, it can be seen that the area occupied by half is sufficient as compared with the conventional example (3) in which the defective portion can be easily specified in consideration of the specification of the short-circuited portion.

Next, a semiconductor wafer (semiconductor substrate) on which the TEG disclosed in all embodiments of the present invention is mounted will be described. FIG. 13 shows a TEG according to the embodiment of the present invention.
FIG. 2 is a schematic view of a wafer on which is mounted. In FIG. 13A,
Reference numeral 203 indicates the case where one or a plurality of TEG chips 202 having substantially the same size as the product are arranged between the product chips 201. By arranging the (4n + 1) TEG chips 202 on the approximate center and the approximate concentric circle of the wafer, it is possible to take a measure for reducing the defect distribution in the wafer surface, that is, for reducing the defect. Here, n is an arbitrary integer. Also, (8n + 1) TEG chips 20
It is also effective to arrange 2 and monitor more detailed in-plane distribution. In FIG. 13A, a method of regularly arranging is adopted, but the present invention is not limited to this.

FIG. 13B shows the product chip 201 and the TEG in order to obtain a more detailed defect in-plane distribution.
FIG. 3 is a schematic view showing a wafer 203 on which chips 202 are mounted in pairs. In this case, the area of the TEG chip 202 may be different from the product chip 201 as illustrated. Figure 1
FIG. 3C shows an example in which a TEG chip 202 is arranged in a scribe area 204 that is removed when cutting a product chip. In this case, the TEG chip 202 is
Can be avoided to reduce the number of product chips 201 to be obtained, which is effective in reducing the product manufacturing cost. Although not shown, the entire surface of the wafer may be made of the TEG of the present invention.

[0038]

According to the present invention, all processes such as wiring resistance, disconnection and short-circuit defect, and through-holes (holes connecting upper and lower wiring layers), which are important elements in the wiring process in the electric circuit manufacturing process, are performed. It is possible to improve the efficiency of searching for a defect, the efficiency of searching for a defective portion, and reduce the area occupied by the TEG, and manage the production yield at low cost. Further, according to the present invention, in a manufacturing process of an electric circuit device, detection of a defect at a low cost and in a short time,
By accelerating the identification of the cause and providing early feedback to the manufacturing process, it is possible to eliminate the loss due to low yield in a short time.

[Brief description of the drawings]

FIG. 1 shows a T for detecting a wiring resistance defect, a short-circuit defect, and a through-hole conduction defect according to a first embodiment of the present invention.
It is a figure showing an EG structure.

FIG. 2 is a wiring resistance measuring method according to an embodiment of the present invention;
FIG. 6 is a diagram illustrating a method for inspecting short-circuit defects.

FIG. 3 is a diagram illustrating an inspection apparatus using a charged particle beam according to an embodiment of the present invention.

FIG. 4 is a diagram illustrating a principle of a potential contrast and a defect recognition method.

FIG. 5 is a diagram illustrating a through-hole resistance measuring method according to an embodiment of the present invention.

FIG. 6 is a diagram illustrating a through-hole defect detection method by a potential contrast method according to the embodiment of the present invention.

FIG. 7 is a TEG for detecting a wiring resistance defect, a short circuit, and a through-hole conduction defect according to the second embodiment of the present invention;
It is a figure showing a structure.

FIG. 8 is a diagram showing a dual damascene-compatible TEG structure according to a second embodiment of the present invention.

FIG. 9 is a diagram showing a TEG structure for detecting a wiring resistance defect and a through-hole conduction defect according to the second embodiment of the present invention.

FIG. 10 is a diagram showing a TEG structure for detecting a short-circuit defect and a defective through-hole conduction according to the second embodiment of the present invention.

FIG. 11 shows a wiring resistance failure according to the third embodiment of the present invention;
It is a figure which shows the TEG structure for detecting a short-circuit failure and a through-hole conduction failure.

FIG. 12 shows a wiring resistance failure according to the third embodiment of the present invention;
It is a figure which shows the TEG structure for detecting a short-circuit failure and a through-hole conduction failure.

FIG. 13 is a schematic view of a wafer on which the TEG according to the embodiment of the present invention is mounted.

FIG. 14 is a diagram showing an effect in the embodiment of the present invention.

[Explanation of symbols]

1, 1 '... pattern for detecting wiring resistance failure, 2, 2', 2 "
... pattern for detecting short circuit, 3, 3 ', 3 "... pattern for detecting poor conduction of through hole, 4 ... interlayer insulating film, 8 ... short defect,
12: disconnection defect, 14: probe, 15: resistance measuring instrument,
17: charged particle beam, 21: secondary electron, 100: inspection device main body, 102: host computer, 102a: monitor screen, 103: network, 104: electric inspection device,
105 ... appearance inspection device, 106 ... database, 107
... Defect analysis system, 110 ... Sample chamber, 112 ... Sample stage, 111 ... Sample (semiconductor device such as semiconductor substrate),
113: charged beam housing, 114: charged particle source, 115
... charged particle optical system, 116 ... secondary electrons, 116 '... reflected electrons, 117 ... charged particle detector.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G01R 31/28 G01R 31/28 V 31/302 L H01L 21/3205 H01L 21/88 S (72) Inventor Hidemi Koike 882 Ma, Hitachinaka-shi, Ibaraki Pref., Hitachi, Ltd.Measurement Instruments Group (72) Inventor Akira Shimase 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa, Japan Hitachi, Ltd.Production Technology Research Laboratories (72) Invention Person Junzo Higashi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside Hitachi, Ltd.Production Technology Research Laboratories (72) Inventor Kaoru Umemura 1-280 Higashi-Koigabo, Higashi-Koigabo, Kokubunji-shi, Tokyo Inside Hitachi Central Research Laboratory (72) Inventor Satoshi Tomimatsu 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (72) Inventor Sugimoto Shun 3-16-16, Shinmachi, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor: Yu Sekihara 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Hitachi, Ltd. F-term in the system (reference) 2G011 AA01 AA02 AD02 2G014 AA02 AA03 AB59 AC11 2G032 AD08 AF02 AF08 AK04 4M106 AA01 AA08 AC01 AC04 BA02 BA14 CA10 CA16 CA39 DB05 DJ38 5F033 HH08 HH11 HH19 JJ11 KK19 KK01 KK08 QQ37 QQ48 VV12 XX37

Claims (12)

[Claims] 1. A test of an electric circuit manufacturing process having a meandering wiring resistance detection pattern and an electrically insulating through-hole conduction failure detection pattern disposed in the gap between the wiring resistance detection patterns. A semiconductor substrate, wherein a pattern is provided in a partial region in a semiconductor substrate for manufacturing a semiconductor product. 2. A test pattern for an electric circuit manufacturing process comprising a comb-shaped short-circuit detection pattern and a through-hole conduction failure detection pattern disposed in a gap between the short-circuit detection patterns and electrically insulated. A semiconductor substrate provided in a partial region in a semiconductor substrate for manufacturing a semiconductor product. 3. The test pattern of the electric circuit manufacturing process, wherein a part of the through hole conduction failure detection pattern includes:
3. The semiconductor substrate according to claim 1, further comprising an electrically insulated short-circuit detection pattern. 4. A test pattern for an electric circuit manufacturing process having a wiring resistance failure detection pattern and a through-hole conduction failure detection pattern connected to the wiring resistance failure detection pattern is formed in a semiconductor substrate for manufacturing a semiconductor product. A semiconductor substrate provided in a partial region of the semiconductor substrate. 5. The semiconductor substrate according to claim 4, wherein in the test pattern of the electric circuit manufacturing process, an electrically insulated short-circuit detection pattern is provided in a gap between the wiring resistance defect detection patterns. 6. A semiconductor for manufacturing a semiconductor product, comprising: a test pattern for an electric circuit manufacturing process having a comb-shaped short-circuit detection pattern facing and a through-hole conduction failure detection pattern connected to the short-circuit detection pattern. A semiconductor substrate provided in a partial region in the substrate. 7. A method of measuring electric resistance by touching a meandering wiring resistance failure detection pattern provided on an electric circuit board, or irradiating the wiring resistance failure detection pattern with a charged particle beam. A resistance inspection step of acquiring the potential contrast generated by the above and inspecting the resistance of the wiring; and arranging the wiring resistance failure detecting pattern in the meandering portion of the pattern on the electric circuit board and electrically insulating the through hole. A defect detection step of measuring a resistance of a through hole for the defect detection pattern, or detecting a defect by acquiring a potential contrast generated by irradiating a charged particle beam to the through hole conduction defect detection pattern. An inspection method for an electric circuit manufacturing process, comprising: 8. The defect detecting step includes a step of detecting a short-circuit defect by irradiating a part of the through-hole conduction defect detecting pattern with a charged particle beam to acquire a potential contrast image generated. The method for inspecting an electric circuit manufacturing process according to claim 7, wherein: 9. A method for measuring electric resistance by touching a meandering wiring resistance failure detection pattern provided on an electric circuit board, or irradiating the wiring resistance failure detection pattern with a charged particle beam. A resistance inspection step of acquiring the potential contrast generated by the above and inspecting the resistance of the wiring, and the resistance of the through hole with respect to the pattern for detecting the conduction defect of the through hole connected to the pattern for detecting the wiring resistance failure on the electric circuit board. Or a defect detecting step of detecting a defect by detecting a potential contrast generated by irradiating a charged particle beam on the pattern for detecting a through-hole conduction failure, and detecting a defect. Inspection method. 10. A potential contrast image generated by irradiating a charged particle beam to an electrically insulated short-circuit detection pattern formed in a gap between the wiring resistance defect detection patterns in the defect detection step. The method for inspecting an electric circuit manufacturing process according to claim 9, further comprising a step of acquiring and detecting a short-circuit defect. 11. An electric resistance is measured by touching an opposing comb-shaped short-circuit detection pattern provided on an electric circuit board, or a charged particle beam is irradiated to the short-circuit detection pattern. A short-circuit inspection step of acquiring a potential contrast generated by and inspecting a short circuit, and measuring a resistance of a through-hole with respect to the through-hole conduction failure detection pattern connected to the short-circuit detection pattern on the electric circuit board, or A defect detection step of detecting a defect by acquiring a potential contrast generated by irradiating the through hole conduction failure detection pattern with a charged particle beam to detect a defect. 12. A method for inspecting an electric circuit manufacturing process according to claim 7, wherein the defect level of the electric circuit manufacturing line is quantitatively evaluated to satisfy the performance of the electric circuit manufacturing line. A method of manufacturing an electric circuit device, comprising: determining whether or not to perform an electric circuit device.