JPH05164798A - Surface potential detection method - Google Patents

Surface potential detection method

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Publication number
JPH05164798A
JPH05164798A JP33330891A JP33330891A JPH05164798A JP H05164798 A JPH05164798 A JP H05164798A JP 33330891 A JP33330891 A JP 33330891A JP 33330891 A JP33330891 A JP 33330891A JP H05164798 A JPH05164798 A JP H05164798A
Authority
JP
Japan
Prior art keywords
sample
scanning
probe electrode
potential
unevenness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33330891A
Other languages
Japanese (ja)
Inventor
Masaaki Niwa
正昭 丹羽
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP33330891A priority Critical patent/JPH05164798A/en
Publication of JPH05164798A publication Critical patent/JPH05164798A/en
Pending legal-status Critical Current

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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To obtain a surface potential detection method which can measure a potential distribution of a sample surface in the order of nm or less with a high resolution and at the same time can detect that of a section part of the sample. CONSTITUTION:A specified bias voltage is applied to a probe electrode 4 and a substrate region 2 of a sample 1 which are placed opposingly on a surface of the sample 1 by a bias circuit 5 and a first scanning is performed so that a tunnel current (It) which flows between them becomes constant, thus enabling a surface roughness of the sample 1 to be measured. Then, a surface roughness of the sample 1 is measured by a second scanning by applying a bias voltage which is equivalent to a band gap to an impurity-implantation region 3 of the sample by a bias circuit 6 and then a difference is obtained by subtracting the surface roughness data which is obtained by the first scanning from that obtained by the second scanning, thus enabling a potential distribution of the sample surface to be detected.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、極微細回路を用いた
電子素子、超LSIや量子化機能素子等の信頼性評価の
ために欠陥検出として行なわれる試料表面の電位検出方
法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for detecting a potential on a surface of a sample, which is performed as a defect detection for reliability evaluation of an electronic device using a very fine circuit, a VLSI, a quantizing function device or the like. ..

【0002】[0002]

【従来の技術】近年、LSIの回路評価については、そ
の表面から観察する方法が採られており、キャリア輸送
に伴う発熱現象を検出する液晶解析技術やキャリアの再
結合やホットエレクトロンによる発光現象を捕らえる発
光解析技術が主流となっている(例えば浦岡、筒、田
中、秋山 SDM90−39 電子情報通信学会 19
90年6月26日)。
2. Description of the Related Art In recent years, a method of observing from the surface of an LSI circuit has been adopted, and a liquid crystal analysis technique for detecting a heat generation phenomenon due to carrier transportation, a recombination of carriers, and a light emission phenomenon due to hot electrons have been adopted. Captured emission analysis technology has become mainstream (for example, Uraoka, Tsutsumi, Tanaka, Akiyama SDM90-39 IEICE 19
June 26, 1990).

【0003】以下図面を参照しながら、上記した従来の
発光解析技術の一例について説明する。図5は、従来の
発光解析技術を用いたホットキャリア評価装置の一例の
構成を示すブロック図である。光学顕微鏡のステ−ジ2
0に置かれたテストパタ−ンやLSI21から放出され
る微弱な発光22は、2次元マイクロチャンネル増幅器
23により増幅され、フォトン数としてカウントされ
る。イメ−ジプロセッサ24は、フォトンカウントの分
布と光学顕微鏡の像を重ね合わせることができるもの
で、発光感度は400 〜800 nm、空間分解能は約1μm
である。ゲート酸化膜中に注入された電子は電界からエ
ネルギーを得てシリコン表面でホールと再結合する時に
発光する。絶縁破壊がおこると、破壊場所に電流が集中
するために発光が生じ、その発光をモニタ画面25上で
観察することができる。
An example of the above-mentioned conventional emission analysis technique will be described below with reference to the drawings. FIG. 5 is a block diagram showing a configuration of an example of a hot carrier evaluation apparatus using a conventional emission analysis technique. Stage 2 of the optical microscope
The weak light emission 22 emitted from the test pattern or LSI 21 placed at 0 is amplified by the two-dimensional microchannel amplifier 23 and counted as the number of photons. The image processor 24 is capable of superimposing the photon count distribution and the image of the optical microscope, and has a light emission sensitivity of 400 to 800 nm and a spatial resolution of about 1 μm.
Is. The electrons injected into the gate oxide film emit energy when they obtain energy from the electric field and recombine with holes on the silicon surface. When the dielectric breakdown occurs, current is concentrated at the breakdown location and light emission occurs, and the light emission can be observed on the monitor screen 25.

【0004】図6は、その発光面(350 ×400 μm2)内
での分布を示す図であり、同図の急峻な突起は電流密度
が100 mA/cm2 流れたことにより生じた発光を示
し、直径は約1μmである。
FIG. 6 is a diagram showing the distribution on the light emitting surface (350 × 400 μm 2 ). The steep projections in FIG. 6 show the light emission caused by the current density of 100 mA / cm 2. The diameter shown is about 1 μm.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、上記の
ような構成では、回路の断線箇所や耐圧不良箇所をおお
まかに同定することはできても、極微細化された回路パ
タ−ンの欠陥箇所を特定できるほどの分解能は発揮でき
ないという問題点があった。また、回路断面部分の観察
ができないため、イオン注入プロファイルの同定は計算
機シミュレ−ションに頼るしか方法がなく、VLSI製
造の決定的阻害要因になるという問題点があった。
However, in the above-mentioned structure, although the disconnection point and the withstand voltage defective section of the circuit can be roughly identified, the defective section of the ultra-miniaturized circuit pattern can be identified. There is a problem that the resolution that can be specified cannot be exhibited. Further, since the section of the circuit cannot be observed, there is a problem that the identification of the ion implantation profile can only be done by computer simulation, which becomes a decisive factor for manufacturing VLSI.

【0006】したがって、この発明の目的は、試料表面
の電位分布をnm以下のオ−ダで高分解能に測定するこ
とができるとともに、試料の断面部分の電位分布も検出
することができる表面電位検出方法を提供することであ
る。
Therefore, the object of the present invention is to detect the surface potential on the surface of the sample with high resolution on the order of nm or less and to detect the potential distribution on the cross section of the sample. It is to provide a method.

【0007】[0007]

【課題を解決するための手段】この発明の表面電位検出
方法は、試料表面に対向配置された探針電極と試料の基
板領域に所定のバイアス電圧を印加し、両者間に流れる
トンネル電流が一定になるようにして1回目の走査を行
なって試料表面の凹凸を測定し、次いで試料の不純物注
入領域にバンドギャップ相当のバイアス電圧を印加して
2回目の走査により試料表面の凹凸を測定し、2回目の
走査で得られた凹凸データから1回目の走査で得られた
凹凸データとの差をとることによって試料表面の電位分
布を検出することを特徴としている。
According to the surface potential detecting method of the present invention, a predetermined bias voltage is applied to the probe electrode and the substrate region of the sample which are arranged to face the sample surface, and the tunnel current flowing between the two is constant. As a result, the first scan is performed to measure the unevenness of the sample surface, and then a bias voltage corresponding to the band gap is applied to the impurity-implanted region of the sample to measure the unevenness of the sample surface by the second scan. The feature is that the potential distribution on the sample surface is detected by taking the difference between the unevenness data obtained by the second scanning and the unevenness data obtained by the first scanning.

【0008】[0008]

【作用】この発明の構成によれば、1回目の走査により
試料表面の物理的な凹凸形状が測定される。2回目の走
査は、さらに不純物注入領域にバンドギャップ相当のバ
イアス電圧を印加して表面の凹凸を測定するので、この
凹凸データには試料表面の物理的な形状を示す情報とと
もに表面の電子状態に基づく電気的な凹凸である表面電
位の空間分布情報も含んでいる。そのため、2回目の走
査で得られた凹凸データから1回目の走査で得られた凹
凸データとの差をとることによって試料表面電位の空間
分布を知ることができる。走査を二次元方向に行なうこ
とにより表面電位の分布を実空間上の分布として測定で
きるので、このデータに基づいて試料表面の電気的欠陥
を検出することができる。
According to the structure of the present invention, the physical uneven shape of the sample surface is measured by the first scanning. In the second scan, a bias voltage corresponding to the band gap is further applied to the impurity-implanted region to measure the surface irregularities. Therefore, the irregularity data includes information indicating the physical shape of the sample surface and the electronic state of the surface. It also includes information on the spatial distribution of the surface potential, which is electrical unevenness based on the above. Therefore, the spatial distribution of the sample surface potential can be known by taking the difference between the unevenness data obtained by the second scan and the unevenness data obtained by the first scan. Since the surface potential distribution can be measured as a distribution in the real space by performing the scanning in the two-dimensional direction, it is possible to detect the electrical defect on the sample surface based on this data.

【0009】[0009]

【実施例】以下この発明の実施例について図面を参照し
ながら説明する。図1は、この発明の表面電位検出方法
を実施する装置の構成を示す概略図で、同図において、
2は試料1となるN型シリコン基板におけるイオン注入
しない領域(以下、基板領域という)、3は基板領域2
に砒素イオンを不純物として注入した領域(以下、不純
物注入領域という)、4は探針電極、5は基板領域2に
印加するバイアス回路、6は不純物注入領域3に印加す
るバイアス回路である。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic diagram showing the configuration of an apparatus for carrying out the surface potential detection method of the present invention.
Reference numeral 2 is a region of the N-type silicon substrate that is the sample 1 where ion implantation is not performed (hereinafter referred to as a substrate region).
A region in which arsenic ions are implanted as impurities (hereinafter referred to as an impurity implantation region), 4 is a probe electrode, 5 is a bias circuit applied to the substrate region 2, and 6 is a bias circuit applied to the impurity implantation region 3.

【0010】試料1表面の電位を検出するために、ま
ず、不純物注入領域3に印加するバイアス回路6を開放
し、バイアス回路5によって基板領域2に2Vだけ印加
する。この状態で探針電極4と試料1表面との間に流れ
るトンネル電流が一定になるように保持しながら、探針
電極4と試料1の表面との距離を制御して探針電極4を
試料1の表面に沿って1回目の走査を行なう(以下、こ
のようにして走査することを定電流モ−ドと略称す
る)。図2(a)のT1 は、1回目の走査により試料1
の表面に沿って一次元的に走査した場合の探針電極4の
軌跡を示す。この軌跡T1 は、基板表面の形状である物
理的な凹凸を表している。
In order to detect the potential on the surface of the sample 1, first, the bias circuit 6 applied to the impurity-implanted region 3 is opened, and the bias circuit 5 applies 2 V to the substrate region 2. In this state, while maintaining the tunnel current flowing between the probe electrode 4 and the surface of the sample 1 constant, the distance between the probe electrode 4 and the surface of the sample 1 is controlled to set the probe electrode 4 to the sample. The first scanning is performed along the surface of No. 1 (hereinafter, such scanning is abbreviated as a constant current mode). T 1 in FIG. 2A is the sample 1 obtained by the first scan.
3 shows a trajectory of the probe electrode 4 when one-dimensionally scanned along the surface of the. This locus T 1 represents physical irregularities that are the shape of the substrate surface.

【0011】次に、不純物注入領域3に更にバイアス回
路6によってバイアスを追加し、定電流モードで探針電
極4による2回目の走査を行なう。不純物注入領域3に
印加するバイアスは、試料のバンドギャップに相当する
電圧を印加する。このようにして一次元方向に走査して
得られた探針電極4の軌跡を図2(a)のT2 に示す。
この軌跡T2 は、不純物注入領域3の表面の電子状態に
基づく電気的な凹凸、すなわち、表面電位の空間分布を
示すが、試料1表面の形状である物理的な凹凸や不純物
を注入したことによる表面の荒れも示している。
Next, a bias circuit 6 further applies a bias to the impurity-implanted region 3, and the probe electrode 4 performs a second scan in the constant current mode. The bias applied to the impurity-implanted region 3 is a voltage corresponding to the band gap of the sample. The locus of the probe electrode 4 obtained by scanning in the one-dimensional direction in this manner is shown by T 2 in FIG.
The locus T 2 shows electrical unevenness based on the electronic state of the surface of the impurity-implanted region 3, that is, the spatial distribution of the surface potential, but the physical unevenness that is the shape of the surface of the sample 1 and that the impurities are injected. The surface roughness due to is also shown.

【0012】次に、このようにして採取された物理的お
よび電気的な凹凸を示すデータの処理が行なわれる。す
なわち、2回目の走査で得られた凹凸データから1回目
の走査で得られた凹凸データとの差をとることによって
表面の物理的な凹凸分を差し引いた正味の電位分布を示
すデータが得られる。その結果、図2(a)のT3 に示
す軌跡が得られる。
Next, the data showing the physical and electrical irregularities thus obtained is processed. That is, the difference between the unevenness data obtained by the second scanning and the unevenness data obtained by the first scanning is taken to obtain data showing the net potential distribution obtained by subtracting the physical unevenness of the surface. .. As a result, the locus shown by T 3 in FIG. 2A is obtained.

【0013】上記した走査およびデータ処理を二次元方
向について行なうことにより、図2(b)に示すような
実空間上の電位分布を知ることができる。この電位分布
を観測することにより表面に存在する欠陥を検出するこ
とができる。図3は電位検出時のバンドダイアグラムを
示すものであって、同図(a)、(b)はそれぞれ基板
領域2、不純物注入領域3の基板側に正のバイアスを印
加した場合のバンド図を示す。同図(a)はN型シリコ
ンの基板領域2におけるバンド図で同時に表面付近の電
子分布のエネルギ−依存性を示す。同図(b)は不純物
として砒素が存在する不純物注入領域3のバンド図でN
+ の領域となっている。
By performing the above-described scanning and data processing in the two-dimensional direction, the potential distribution in the real space as shown in FIG. 2B can be known. By observing this potential distribution, defects existing on the surface can be detected. FIG. 3 is a band diagram at the time of potential detection, and FIGS. 3A and 3B are band diagrams when a positive bias is applied to the substrate side of the substrate region 2 and the impurity implantation region 3, respectively. Show. FIG. 3A is a band diagram in the substrate region 2 of N-type silicon and simultaneously shows the energy dependence of the electron distribution near the surface. FIG. 2B is a band diagram of the impurity-implanted region 3 in which arsenic is present as an impurity.
It is the area of + .

【0014】トンネル電流It9は探針電極4と試料表
面間の空間10をトンネルして試料1表面の準位に流れ
る。図(a)では基板領域2はN型シリコンであるの
で、電子の状態密度は伝導帯端付近11より価電子帯端
付近12のほうが大きい。不純物注入領域3におけるN
+ 型基板の場合は、価電子帯端の状態密度14は伝導帯
端付近の状態密度13より大きい。印加する正のバイア
スを試料のバンドギャップと同等かそれより大きい値に
すると、ギャップ中準位や各バンド端付近の電子状態を
反映したトンネル電流が探針電極4からシリコン基板2
または3の空準位に流れ、基板領域2のN型と不純物注
入領域3のN+ 型との差異が明瞭に検出されることにな
る。そこで、2回目の走査を行なう際に、試料のバンド
ギャップに相当する電圧を印加して走査を行なうのであ
る。
The tunnel current It9 tunnels through the space 10 between the probe electrode 4 and the sample surface and flows to the level of the sample 1 surface. In FIG. 5A, since the substrate region 2 is N-type silicon, the density of states of electrons is larger in the vicinity 12 of the valence band edge than in the vicinity 11 of the conduction band edge. N in the impurity implantation region 3
In the case of the + type substrate, the density of states 14 at the valence band edge is higher than the density of states 13 near the conduction band edge. When the applied positive bias is set to a value equal to or larger than the band gap of the sample, a tunnel current reflecting the level in the gap and the electronic state near each band edge is transmitted from the probe electrode 4 to the silicon substrate 2.
Or, it flows to the vacant level of 3 and the difference between the N type of the substrate region 2 and the N + type of the impurity implantation region 3 is clearly detected. Therefore, when the second scan is performed, a voltage corresponding to the band gap of the sample is applied to perform the scan.

【0015】図4(a)は不純物注入領域3にバイアス
回路6によってバイアスを4Vに増加して印加した場合
についての結果を示すが、図2(b)と比較すると注入
領域印加バイアスを増加させることによって電位の分布
は隣接する不純物注入領域の電位分布に一部重複しはじ
めているのが認められる。このような動的現象は従来の
評価手段では不可能であった。
FIG. 4A shows the result when the bias is increased to 4 V by the bias circuit 6 and is applied to the impurity implantation region 3. Compared with FIG. 2B, the implantation region applied bias is increased. Therefore, it is recognized that the potential distribution starts to partially overlap with the potential distribution of the adjacent impurity implantation region. Such a dynamic phenomenon was impossible with the conventional evaluation means.

【0016】また、探針電極4をへき開した試料1の断
面上で上記と同様の走査を行なった場合の結果を図4
(a)(b)に示す。同図(a)は、不純物注入領域3
の断面部分において砒素の注入条件を80keV 、1×1
15cm-2とし、不純物注入領域3へのバイアス回路6を
開放して定電流モードで二次元方向に走査した場合の探
針電極4の軌跡を示したものである。同図(b)は、同
一測定条件で砒素の注入条件を160keV 、1×1015
cm-2とした場合の電位分布を示す。この場合、注入エネ
ルギを80keV から160keV にすることにより、注入
された砒素の分布がシリコン表面からの深さにして0.15
μmから0.20μmにまで伸び、砒素濃度分布のピークが
0.5 μm付近から1.0 μm付近へとシリコン基板表面か
ら深部へシフトしているのがわかる。
FIG. 4 shows the result when the same scanning as above is performed on the cross section of the sample 1 in which the probe electrode 4 is cleaved.
Shown in (a) and (b). FIG. 3A shows the impurity implantation region 3
Arrangement conditions of 80 keV, 1 × 1
0 15 cm -2, and shows the locus of the probe electrode 4 when the bias circuit 6 to the impurity implantation region 3 is opened and two-dimensional scanning is performed in the constant current mode. In the same figure (b), arsenic implantation conditions are 160 keV, 1 × 10 15 under the same measurement conditions.
The electric potential distribution is shown for cm -2 . In this case, by changing the implantation energy from 80 keV to 160 keV, the distribution of the implanted arsenic becomes 0.15 in terms of the depth from the silicon surface.
The peak of the arsenic concentration distribution extends from μm to 0.20 μm
It can be seen that there is a shift from the surface of the silicon substrate to the deep part from around 0.5 μm to around 1.0 μm.

【0017】シリコン原子と較べてほう素イオンは質量
が小さく、砒素イオンは逆に大きいので、ほう素イオン
注入プロファイルは広角散乱の確率が増し、シリコン基
板表面に偏った分布を示す。逆に砒素イオンの注入分布
は広角散乱が少なくシリコン基板の結晶内部側に偏った
分布を示すと考えられる。この結果は、入射粒子の静止
位置分布を与える確立密度関数を用いて見積られた計算
結果とも良好な一致がみられ、この発明の表面電位検出
方法により、従来困難とされていた物質中における不純
物原子の分布を実空間上に二次元的に表示して直接測定
することが可能になったものである。
Since boron ions have a smaller mass and arsenic ions have a larger mass than silicon atoms, the boron ion implantation profile has an increased probability of wide-angle scattering and exhibits a biased distribution on the surface of the silicon substrate. On the contrary, it is considered that the implantation distribution of arsenic ions has a small wide-angle scattering and is biased toward the inside of the crystal of the silicon substrate. This result is in good agreement with the calculation result estimated by using the probability density function that gives the stationary position distribution of the incident particles, and the surface potential detection method of the present invention makes it possible to obtain the impurities in the substance which were conventionally difficult. It is now possible to directly measure the distribution of atoms displayed in two dimensions in real space.

【0018】上記したようにこの発明の実施例によれ
ば、試料1表面の物理的な凹凸と区別して電位の空間分
布を二次元の実空間上に表現することができるととも
に、試料1の断面部分の電位分布も検出することができ
るので、従来把握できなかったミクロな電気的欠陥を検
出することができる。
As described above, according to the embodiment of the present invention, the spatial distribution of the potential can be expressed in a two-dimensional real space in distinction from the physical unevenness on the surface of the sample 1, and the cross section of the sample 1 can be obtained. Since it is possible to detect the potential distribution of a portion, it is possible to detect a micro electrical defect that could not be grasped conventionally.

【0019】[0019]

【発明の効果】この発明の表面電位検出方法によれば、
試料表面の物理的な凹凸と区別して電位の空間分布を二
次元の実空間上に表現することができるとともに、試料
の断面部分の電位分布も検出することができるので、従
来把握できなかったミクロな電気的欠陥を検出すること
ができ、試料となる極微細回路等の信頼性評価をより正
確に行なうことができるようになった。
According to the surface potential detecting method of the present invention,
The spatial distribution of the potential can be expressed in a two-dimensional real space in distinction from the physical unevenness of the sample surface, and the potential distribution in the cross section of the sample can also be detected. It has become possible to detect various electrical defects, and more accurately evaluate the reliability of a sample ultrafine circuit or the like.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の表面電位検出方法を実施する装置の
構成を示す概略図である。
FIG. 1 is a schematic diagram showing the configuration of an apparatus for carrying out the surface potential detection method of the present invention.

【図2】(a)は基板に対して探針電極を走査した場合
の探針電極の軌跡を示す図、(b)は探針電極を二次元
方向に走査して得られた実空間上の電位分布を示す図で
ある。
FIG. 2A is a diagram showing a trajectory of a probe electrode when the probe electrode is scanned on a substrate, and FIG. 2B is a real space obtained by scanning the probe electrode in a two-dimensional direction. It is a figure which shows the electric potential distribution of.

【図3】(a)は電位検出時の基板領域におけるバンド
ダイアグラム、(b)は同じく不純物注入領域における
バンドダイアグラムである。
3A is a band diagram in a substrate region at the time of potential detection, and FIG. 3B is a band diagram in the same impurity implantation region.

【図4】(a)は試料のへき開した断面上を走査した場
合の探針電極の軌跡を示す図、(b)は同じく不純物の
注入条件を変えた場合の探針電極の軌跡を示す図であ
る。
FIG. 4A is a diagram showing a trajectory of a probe electrode when scanning a cleaved cross section of a sample, and FIG. 4B is a diagram showing a trajectory of a probe electrode when an implantation condition of impurities is changed. Is.

【図5】従来の発光解析によりホットキャリア評価を行
なう装置の構成例を示す図である。
FIG. 5 is a diagram showing a configuration example of a conventional device for performing hot carrier evaluation by light emission analysis.

【図6】図5に示す装置における発光の面内分布を示す
図である。
6 is a diagram showing an in-plane distribution of light emission in the device shown in FIG.

【符号の説明】[Explanation of symbols]

1 試料 2 基板領域 3 不純物注入領域 4 探針電極 5 基板領域2に印加するバイアス回路 6 不純物注入領域3に印加するバイアス回路 1 sample 2 substrate region 3 impurity implantation region 4 probe electrode 5 bias circuit applied to substrate region 2 6 bias circuit applied to impurity implantation region 3

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 試料表面に探針電極を対向配置し、試料
表面と探針電極間にバイアス電圧を印加し、両者間に流
れるトンネル電流が一定になるように探針電極を試料表
面に沿って走査し、試料表面の凹凸を測定して表面電位
を検出する表面電位検出方法であって、試料の基板領域
に所定のバイアス電圧を印加して1回目の走査により試
料表面の凹凸を測定し、さらに試料の不純物注入領域に
バンドギャップ相当のバイアス電圧を印加して2回目の
走査により試料表面の凹凸を測定し、2回目の走査で得
られた凹凸データから1回目の走査で得られた凹凸デー
タとの差をとることによって試料表面の電位分布を検出
することを特徴とする表面電位検出方法。
1. A probe electrode is disposed opposite to a sample surface, a bias voltage is applied between the sample surface and the probe electrode, and the probe electrode is arranged along the sample surface so that a tunnel current flowing between the two becomes constant. It is a surface potential detection method that detects the surface potential by measuring the unevenness of the sample surface by scanning with a predetermined bias voltage to the substrate area of the sample and measuring the unevenness of the sample surface by the first scanning. Further, a bias voltage corresponding to the band gap was applied to the impurity-implanted region of the sample, the unevenness of the sample surface was measured by the second scanning, and the unevenness data obtained by the second scanning was obtained by the first scanning. A surface potential detection method, characterized in that the potential distribution on the sample surface is detected by taking the difference from the unevenness data.
JP33330891A 1991-12-17 1991-12-17 Surface potential detection method Pending JPH05164798A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33330891A JPH05164798A (en) 1991-12-17 1991-12-17 Surface potential detection method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33330891A JPH05164798A (en) 1991-12-17 1991-12-17 Surface potential detection method

Publications (1)

Publication Number Publication Date
JPH05164798A true JPH05164798A (en) 1993-06-29

Family

ID=18264653

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33330891A Pending JPH05164798A (en) 1991-12-17 1991-12-17 Surface potential detection method

Country Status (1)

Country Link
JP (1) JPH05164798A (en)

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