JP2006319022A - Inspection method and inspection device for semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of inspecting a semiconductor device capable of evaluating a micro crystal defects, which may cause electric failures to the semiconductor device, with high spatial resolution while a time is shortened for the formation of a specimen. <P>SOLUTION: The inspection method comprises processes of bringing a current detection probe 11 into contact with the surface of an inspected specimen 21, irradiating the inspected specimen 21 with a low-acceleration energy electron beam 22, scanning the surface of the inspection specimen 21, and detecting EBIC signals produced inside the specimen 21, As the result, a process of forming a metal film usually on the surface of the specimen 21 to detect a current can be dispensed with, and an evaluation can be performed in a short time. The spread of the electron beam 22 inside the specimen 21 can be limited to a few tens of nm, so that a crystal defect can be evaluated up to a spatial resolution of a few tens nm. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an inspection technique for a semiconductor device, and more particularly to an inspection technique for inspecting and analyzing a crystal defect portion that causes an electrical characteristic defect in a semiconductor device.

  In semiconductor devices, stress concentration inside the device tends to increase with the miniaturization and high integration of elements. Along with this, the thermal expansion coefficient differs at the interface of different materials inside the device, so that crystal defects are likely to occur due to stress concentration. In addition, with the introduction of new materials, for example, strained Si / SiGe-based devices use the difference in lattice spacing of the SiGe layer to distort the Si layer to increase carrier mobility and improve performance. However, crystal defects are likely to occur due to strain stress. When a crystal defect, which is a misfit dislocation extending in the plane of the semiconductor device, is in the vicinity of the pn junction, a leakage current between the source and the drain is induced, and it extends from the semiconductor Si substrate to the surface of the semiconductor device. Defects that are threading dislocations are considered to cause a significant increase in leakage current and deteriorate the characteristics of semiconductor devices.

  Conventionally, there are an OBIRCH (Optical Beam Induced Resistance Change) method and an EBIC (Electron Beam Induced Current) method as means for non-destructively detecting a crystal defect that causes a defective electrical characteristic of a semiconductor device. The OBIRCH method is described in “JP-A-8-255818” and “JP-A-9-145795”, and is a method of mainly inspecting and analyzing wiring resistance defects using light.

  The EBIC method measures the current induced in a semiconductor by an electron beam as described in “Electron / Ion Beam Handbook (3rd edition), pp. 87-94 (1998)” This is a method for evaluating defects. When an electron beam is irradiated to the pn junction, an electron / hole pair generated in the depletion layer is divided into opposite conductivity type regions by the internal electric field of the junction, and a current is generated in the defect portion. The current decreases due to absorption at the defect. Defects are evaluated by evaluating the current decrease.

JP-A-8-255818 Japanese Patent Laid-Open No. 9-14595 Electron / Ion Beam Handbook (Third Edition), pages 87-94 (1998)

  Similarly to EBIC, the above OBIC method can also evaluate crystal defects by evaluating the amount of current change. However, since a light source is used, the resolution is about 100 nm, which is insufficient for evaluating fine crystal defects.

  In the conventional EBIC method, it is necessary to deposit a metal film on the surface of the object to be inspected in order to measure the current generated inside the sample. Therefore, it took about 1 hour to evaluate. Further, since it is necessary to allow the electron beam to reach the inside of the semiconductor device through the metal film, the acceleration voltage has to be increased. When the acceleration voltage is set high, for example, when an electron beam with an acceleration voltage of 5 kV is used, the resolution becomes several μm because the electron beam spreads inside the sample. As described above, the conventional EBIC method cannot sufficiently evaluate the microcrystal defects.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device inspection technique capable of evaluating a microcrystal defect that may be an electrical failure inside a semiconductor device with a high spatial resolution by shortening a sample preparation time.

  In order to achieve the above object, the present invention has the following characteristics.

  The present invention irradiates and scans a sample with an electron beam, and uses one or more current detection probes to make a metal film on the sample surface for current detection by contacting the detection probe with the sample surface. The current generated inside the sample is detected without being required.

  For this reason, evaluation in a few minutes to several tens of minutes is possible. Furthermore, since there is no metal film on the sample surface, evaluation with a low-acceleration electron beam is possible, the electron beam spread inside the sample can be suppressed to several tens of nm, and minute defects can be evaluated with high spatial resolution.

  Hereinafter, typical configuration examples of the present invention will be listed.

  (1) A method for inspecting a semiconductor device according to the present invention includes: a step of irradiating and scanning an electron beam to the semiconductor device; a step of detecting a signal secondarily generated from the semiconductor device by the electron beam; A step of imaging a signal and displaying it as a first image; a step of generating carriers by irradiating the inside of the semiconductor device with the electron beam; and a probe in contact with the semiconductor device; A step of detecting a carrier current generated inside the semiconductor device by a probe, an image of the detected carrier current in synchronization with scanning of the electron beam, and displaying as a second image. The defect portion of the semiconductor device is evaluated based on the first image and the second image.

  (2) A method for inspecting a semiconductor device according to the present invention includes: a step of irradiating and scanning an electron beam to the semiconductor device; a step of detecting a signal secondarily generated from the semiconductor device by the electron beam; A step of imaging a signal and displaying it as a first image, a step of generating carriers by irradiating the inside of the semiconductor device with the electron beam, and a first probe probe contacting the surface of the semiconductor device A step of bringing a second probe probe into contact with the back surface of the semiconductor device; and grounding the second probe probe to generate a first carrier current generated inside the semiconductor device by the first probe probe. Detecting or grounding the first probe probe and detecting a second carrier current generated in the semiconductor device by the second probe probe; and Recording the first or second carrier current in synchronization with the scanning of the electron beam and displaying it as a second image, based on the first image and the second image The defect portion of the semiconductor device is evaluated.

  (3) In the inspection method having the above configuration, the method includes a step of controlling the temperature of the semiconductor device to be variable, and based on the second image and the first image obtained according to a temperature change of the semiconductor device. A defect portion of the semiconductor device and a defect level in the defect portion are evaluated.

  (4) In the inspection method having the above structure, the semiconductor device has a structure in which a pn junction or a Schottky junction is formed in a semiconductor substrate, and an electric field is formed in the substrate.

  (5) In the inspection method having the above configuration, the first image and the second image are simultaneously displayed on the display, or the first image and the second image are switched and displayed on the display. It was made to do.

  (6) A semiconductor device inspection apparatus according to the present invention includes an electron gun that generates an electron beam, an electron optical system that irradiates and scans the semiconductor device with the electron beam, a sample stage for mounting the semiconductor device, A detector for detecting a signal that is secondarily generated from the semiconductor device by irradiation of the electron beam, a probe probe that is brought into contact with the front or back surface of the semiconductor device, and the semiconductor device by irradiation of the electron beam Means for detecting and imaging a carrier current generated by being excited inside by the probe probe, and based on the image by the signal generated secondarily and the image by the carrier current amount, It is characterized by evaluating a defective portion of a semiconductor substrate.

  (7) The inspection apparatus having the above-described configuration further includes means for controlling the temperature of the semiconductor device to be variable.

  (8) In the inspection apparatus having the above configuration, the semiconductor device has a structure in which a pn junction or a Schottky junction is formed in a semiconductor substrate, and an electric field is formed in the substrate.

  According to the present invention, it is possible to evaluate a microcrystal defect that may cause an electrical failure inside a semiconductor device with a high spatial resolution by shortening a sample preparation time.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted.

Example 1
In this example, an inspection method and an inspection apparatus for identifying a defective portion of electrical characteristics and evaluating a contamination level of the defective portion in a semiconductor device in which a pn junction transistor is formed on a semiconductor substrate will be described.

  FIG. 2 shows the configuration of the main part of the semiconductor device inspection apparatus according to this embodiment. The semiconductor inspection apparatus includes an electron gun 1, a condenser lens 2, a blanking control electrode 3, a movable diaphragm 4, a deflector 5, an objective lens 6, a secondary electron detector 7, a sample stage 8, a temperature control sample holder 9, and an XY. Stage 10, current measurement probe 11, probe probe holding unit 12, preamplifier 13, amplifier 14, signal input changeover switch 15, AD converter 16, SEM display 17, personal computer 18, sample exchange chamber (not shown) The vacuum exhaust system 20 is used.

  FIG. 1 shows an enlarged view of the sample 21 to be inspected, the probe 11 and the probe probe current detection system in FIG.

  The timing of irradiating the sample 21 (in this case, the semiconductor device) with the electron beam 22 is controlled by the blanking control electrode 3, and the electron beam 22 is inspected 21 at a time other than when the inspection is performed. Is not irradiated. When the specimen 21 is irradiated with the electron beam 22, the scanning speed and the scanning area are controlled by the deflector 5. The irradiation energy of the electron beam was 1.5 kV. As a result, the electron beam 22 reaches the depletion layer inside the sample 21 to be inspected, and at the same time, the electron beam range inside the sample 21 to be inspected can be suppressed to about several tens of nm. Further, the current of the electron beam 22 to be irradiated is in the order of pA to nA, and is set to a current of about 300 pA here.

  The probe 11 (for example, coaxial shield probe) is brought into contact with the surface of the sample 21 to be inspected, and the sample 21 is irradiated with the electron beam 22. The electron beam irradiation forms a pair of electrons 23 and holes 24 inside the sample 21 to be inspected. The electrons 23 flow to the n region 26 by the electric field of the depletion layer 25, and the holes 24 pass through the p layer 27 and the sample 21 to be inspected. Flows to the back side of the substrate. When the back surface of the sample 21 to be inspected is grounded to the ground, a closed loop is formed, and thus the generated drift of the pair of electrons 23 and holes 24 can be detected as a current. The electrons 23 drifting to the n layer 26 are detected by the probe probe 11, passed through the shield probe 39 connecting the probe probe 11 and the preamplifier 13, and simultaneously converted into a voltage by the preamplifier 13 immediately after the probe probe 11. Amplified, taken out of the vacuum chamber through the feedthrough 28, further amplified by the amplifier 14, and then input to the AD converter 16. Then, it is displayed on the display 17 or the personal computer monitor 18.

  Here, although the sample 21 to be inspected is described as an n-type semiconductor sample, even a p-type semiconductor sample is an inspection target.

  When displaying an electron beam image, the secondary electron 29 generated by irradiating the specimen 21 with the electron beam 22 is detected by the secondary electron detector 7, the detected signal is amplified, and an AD converter is obtained. 16 is converted into a digital signal and displayed on the display 17 or the personal computer monitor 18. In this apparatus, a switch 15 for switching a secondary electron signal and a signal flowing through the electric measurement probe 11 is installed in front of the AD converter 16, and either the secondary electron signal or the signal flowing through the probe 11 is used. The display can be arbitrarily selected by switching the switch. Therefore, it is possible to alternately observe the SEM image 35 which is the signal of the secondary electrons 29 and the signal flowing through the probe probe 11, that is, the probe current image 36 while scanning the electron beam 22 at the same location. is there. Here, the preamplifier 13 and the amplifier 14 that amplify the signal flowing through the probe 11 can amplify the signal at a speed equivalent to the scanning speed of a normal SEM by using a high-speed amplifier with a response speed of 400 kHz or higher. Therefore, the probe current image 36 can be displayed.

  As shown in FIG. 1, when the non-inspection sample 21 is irradiated with the electron beam 22, carriers (electrons 23 and holes 24) are generated in the non-inspection sample 21, and a current flows. When there is a defect, the generated carriers (electrons 23 and holes 24) are recombined at the defect portion 30. Therefore, the current detected by the probe probe 11 decreases. Due to this difference in the amount of current signal, the normal portion 31 is bright and the defective portion 30 is dark. By switching the switch 15 of the input signal, the SEM image 35 and the probe current image 36 are displayed, and the dark portion of the probe current image 36 is compared with the location of the SEM image 35, so that the location of the defective portion 30. Can be specified.

  In this method, the acceleration voltage of the electron beam 22 is set to a condition of 1.5 kV, and the spread of the electron beam inside the sample 21 is controlled to about several tens of nm. For this reason, the defect location in the probe current image 36 can be evaluated on the order of several tens of nm. In addition, since the process of metal deposition on the surface of the sample 21 to be inspected, which has been necessary in the past, can be omitted and the current signal can be measured by contact with the probe probe 11, evaluation on the order of several minutes has become possible.

(Example 2)
In the second embodiment of the present invention, two probe probes for current measurement are provided in the first embodiment described above. FIG. 3 shows a schematic diagram when there are two probe probes for current measurement.

  In this case, the first probe probe 11 is brought into contact with the surface of the sample 21 to be inspected, and the second probe 32 is brought into contact with the back surface of the sample 21 to be inspected. When the first probe probe current is measured, the second probe probe 32 is grounded, and when the current is measured by the second probe probe 32, the first probe probe 11 is grounded. Further, the probe probe 11 and other configurations are the same as those in the first embodiment.

  In this state, when the current is measured by the second probe probe 32, a current with low noise is detected by the second probe probe 32 from the back surface of the sample 21 to be inspected and amplified by the preamplifier 13 immediately after the probe. Can be obtained. As a result, a probe current image 36 having a high SN can be obtained. Conventionally, when the measurement is performed through the sample stage 8 on the back surface of the sample 21 to be inspected, noise is likely to travel due to the long path to be amplified by the amplifier, and the SN of the probe current image 36 is low. . Further, when the sample stage 8 has noise, the probe current image 36 with a low SN ratio was obtained due to the noise. However, by reducing noise according to this embodiment, a probe current image 36 having a high SN can be obtained, which is very effective in improving the sensitivity of defect detection.

  In this embodiment, in the sample stage for mounting the semiconductor substrate which is the sample to be inspected, the sample stage has a concave shape, or the sample stage and the back side of the semiconductor substrate are not in contact so that the probe is brought into contact with the back side of the semiconductor substrate. It has a contact area. Each of the plurality of probes has a holding drive control unit that can be driven independently.

(Example 3)
In the third embodiment of the present invention, the temperature of the sample 21 to be inspected is variably controlled (heated or cooled) by the temperature control sample holder 9 in the first and second embodiments. A schematic diagram thereof is shown in FIG.

  As described in the first embodiment, in the probe current image 36, the normal portion 31 is bright and the defective portion 30 is dark. Under the condition of cooling to a low temperature, the generated carrier electrons 23 or holes 24 have a low probability of being trapped in the deep level defects 34 due to low excitation energy by heat, and are trapped in the shallow level defects 33. Establishing is high. For this reason, at low temperatures, the absorption of carriers by the shallow level defect portion 33 increases, and in the probe current image 37 at low temperature, the contrast of the shallow level defect portion 33 is high, while the deep level defect. The contrast of the part 34 is lowered. At high temperatures, the heat energy of the electrons 23 and holes 24 of the carriers is high, so the probability of being absorbed by the deep level defects 34 is high, and the probability of being absorbed by the shallow level defects 33 is low. As a result, in the probe current image 38 at a high temperature, the contrast of the shallow level defect 33 is small, and the contrast of the deep level defect 34 is large.

By using the evaluation of the probe current images 37 and 38 based on the temperature characteristics and the secondary electron image 35, it becomes possible to grasp the defect location and the level of the defect at the defect location. In the third to third embodiments, the semiconductor device in which the pn junction transistor is formed is described as an example of a sample to be inspected. .

  As described above in detail, according to the present invention, it is possible to evaluate a microcrystal defect that may be an electrical failure inside a semiconductor device with a high spatial resolution by shortening the sample preparation time.

Schematic explaining the inspection method according to the first embodiment of the present invention. The figure explaining the structure of the principal part of the semiconductor inspection apparatus of this invention. Schematic explaining the inspection method by the 2nd Example of this invention. Schematic explaining the inspection method by the 3rd Example of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Electron gun, 2 ... Condenser lens, 3 ... Blanking control electrode, 4 ... Movable diaphragm, 5 ... Deflector, 6 ... Objective lens, 7 ... Secondary electron detector, 8 ... Sample stand, 9 ... Temperature control sample Holder 10 XY stage 11 Current probe probe 12 Probe probe holding unit 13 Preamplifier 14 Amplifier 15 Signal switch 16 AD converter 17 SEM display DESCRIPTION OF SYMBOLS 18 ... Personal computer, 20 ... Vacuum exhaust system, 21 ... Sample to be inspected, 22 ... Electron beam, 23 ... Electron, 24 ... Hole, 25 ... Depletion layer, 26 ... n layer, 27 ... p layer, 28 ... Feedthrough, 29 ... secondary electrons, 30 ... defects, 31 ... normal parts, 32 ... second current measuring probe, 33 ... shallow level defects, 34 ... deep level defects, 35 ... secondary electron images, 36 ... Secondary electron image, 37 ... low temperature Probe current image of, 38 ... probe current image at a high temperature.

Claims (8)

  A step of irradiating and scanning the semiconductor device with an electron beam, a step of detecting a signal secondarily generated from the semiconductor device by the electron beam, and imaging the detected signal to display as a first image. A step of generating carriers by irradiating the electron beam inside the semiconductor device; and a probe probe is brought into contact with the semiconductor device, and the carrier current generated inside the semiconductor device is detected by the probe probe And imaging the detected carrier current in synchronization with scanning of the electron beam and displaying it as a second image, based on the first image and the second image A method for inspecting a semiconductor device, comprising: evaluating a defective portion of the semiconductor device.   A step of irradiating and scanning the semiconductor device with an electron beam, a step of detecting a signal secondarily generated from the semiconductor device by the electron beam, and imaging the detected signal to display as a first image. A step of generating carriers by irradiating the inside of the semiconductor device with the electron beam, a first probe probe in contact with the semiconductor device surface, and a second probe probe on the back surface of the semiconductor device Contacting the second probe probe and detecting the first carrier current generated inside the semiconductor device by the first probe probe, or connecting the first probe probe Grounding and detecting a second carrier current generated inside the semiconductor device by a second probe probe; and detecting the detected first or second carrier current And evaluating the defect portion of the semiconductor device on the basis of the first image and the second image, wherein the second image is displayed in synchronization with the scanning of the child beam. A method for inspecting a semiconductor device.   3. The method for inspecting a semiconductor device according to claim 1, further comprising a step of controlling the temperature of the semiconductor device so that the temperature of the semiconductor device is variable. The second image and the first image obtained according to a temperature change of the semiconductor device. And a defect level of the semiconductor device and a defect level in the defect portion are evaluated.   3. The semiconductor device inspection method according to claim 1, wherein the semiconductor device has a structure in which a pn junction or a Schottky junction is formed in a semiconductor substrate, and an electric field is formed inside the substrate. Inspection method for semiconductor device.   3. The semiconductor device inspection method according to claim 1, wherein the first image and the second image are simultaneously displayed on a display, or the first image and the second image are displayed. A method for inspecting a semiconductor device, wherein the display is switched and displayed above.   An electron gun that generates an electron beam; an electron optical system that irradiates and scans the semiconductor device with the electron beam; a sample stage on which the semiconductor device is mounted; and secondary irradiation from the semiconductor device by irradiation with the electron beam. A detector for detecting a signal generated in the semiconductor device, a probe probe brought into contact with the front or back surface of the semiconductor device, and a carrier current generated by being excited inside the semiconductor device by irradiation of the electron beam. Means for detecting and imaging with a probe, and evaluating a defective portion of the semiconductor substrate based on an image based on the signal generated secondarily and an image based on the carrier current amount Inspection equipment for semiconductor devices.   7. The semiconductor device inspection apparatus according to claim 6, further comprising means for controlling the temperature of the semiconductor device to be variable. 8. The semiconductor device inspection apparatus according to claim 6, wherein the semiconductor device has a structure in which a pn junction or a Schottky junction is formed in a semiconductor substrate, and an electric field is formed inside the substrate. Inspection equipment for semiconductor devices.

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