JP2009252995A - Semiconductor inspection method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor inspection method that applies an electric load, such as a voltage and a temperature, to a circuit pattern to carry out evaluation of reliability, as a technique for inspecting a wafer in a semiconductor manufacturing process. <P>SOLUTION: An electric load is applied to a circuit pattern by a step of irradiating an electron beam for a predetermined time period to a wafer including the circuit pattern in a semiconductor manufacturing process to charge the circuit pattern to a predetermined charge voltage (Step 99), and a step of controlling a region surrounding the circuit pattern to a predetermined temperature by laser irradiation or the like (Step 106). By irradiating the electron beam to a region including the circuit pattern before and after the application of electric load to acquire a second electric image (Step 90), and the second electric images before and after the application of electric load are compared and determined to inspect the circuit pattern and the wafer including the same. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  In particular, the present invention relates to an inspection method for a semiconductor device using an electron beam, an inspection technique for detecting a defect on a semiconductor wafer having a circuit pattern, a failure analysis technique for electrical characteristics of a semiconductor element, a reliability evaluation technique, and a defect. The present invention relates to a manufacturing technique of a semiconductor device using inspection.

  As a method for evaluating a semiconductor wafer having a circuit pattern using an electron beam, a technique for performing a high-throughput and high-accuracy inspection corresponding to an increase in wafer diameter and circuit pattern miniaturization has been put into practical use. For example, as disclosed in Patent Document 1 (Japanese Patent Application Laid-Open No. 06-139985), a method for inspecting defects using the contrast of a secondary electron beam caused by a surface potential difference is known. As a method for evaluating electrical defects from potential contrast, for example, in Patent Document 2 (Japanese Patent Laid-Open No. 11-121561), a secondary electron image generated from the wafer surface is acquired by irradiating the wafer with an electron beam. The method is described. In this method, an electrical defect of a circuit pattern can be inspected by a potential contrast of secondary electrons generated when the circuit pattern is charged by irradiating an electron beam. In particular, for a technique for evaluating the characteristics of a semiconductor gate oxide film or the like, for example, as disclosed in Patent Document 3 (Japanese Patent Laid-Open No. 2005-108984), an electron beam is applied once or a plurality of times at a predetermined interval. There is known a technique for identifying a leakage defect from an image of secondary electrons generated by irradiation.

On the other hand, with the recent thinning of gate insulating films and the introduction of new processes, it is important to evaluate the reliability of gate oxide films such as CMOS and tunnel oxide films of memories. Conventionally, after completion of a semiconductor circuit, a probe is brought into contact, and an electrical load is applied to the semiconductor circuit, and then a change in electrical characteristics is evaluated to evaluate reliability. As a method for evaluating reliability, for example, there is a technique called TDDB (Time Dependent Dielectric Breakdown), and dielectric breakdown characteristics when a voltage is applied to an oxide film for a long time are generally evaluated. As another reliability evaluation method, evaluation of deterioration of MOS characteristics due to the hot carrier effect is performed. As another reliability evaluation method, a method called PBTI (Positive Bais Temperature Instability) or NBTI (Negative Bais Temperature Instability) is used when a positive or negative voltage is applied to an oxide film for a long time at a high temperature. Evaluation of changes in MOS characteristics is performed.
Japanese Patent Laid-Open No. 06-139985 Japanese Patent Laid-Open No. 11-121561 JP 2005-108984 A

  When the defect inspection method using the electron beam as described above is used, the electrical characteristics of the circuit pattern formed on the wafer can be inspected at high speed without contact and without destruction during the semiconductor manufacturing process. However, with this method, it has been impossible to perform reliability evaluation such as inspecting a change in electrical characteristics after applying an electrical load to a circuit pattern. For this reason, conventionally, it has been difficult to perform reliability evaluation during the semiconductor manufacturing process (so-called in-line).

  On the other hand, conventionally, for example, reliability evaluation is performed in a probe inspection after a semiconductor manufacturing process. However, in this case, since the probe was brought into contact with the pad and an electrical load was applied to the element, the probe was brought into contact with the pad and the electrical characteristics were evaluated, so the reliability of the entire semiconductor circuit could be evaluated. However, it was impossible to know which part of the circuit pattern actually failed and the element characteristics deteriorated. For this reason, it takes time to identify and analyze the defective part and to find out the cause of the defect, which causes a delay in the semiconductor development period. In other words, for example, if the cause of reliability degradation occurs at an early stage of the semiconductor manufacturing process, even if a failure occurs at this stage, it cannot be detected until the semiconductor circuit is completed and an electrical test is performed, It took time from the occurrence of defects to the implementation of countermeasures. For this reason, enormous time on the order of several months was spent on countermeasures, which caused the semiconductor development period to be delayed.

  The present invention has been made in view of the above, and the above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

  Therefore, the present inventors examined a method of performing reliability evaluation during the semiconductor manufacturing process. As a result, by applying a load corresponding to the electrical load applied to the semiconductor circuit during the reliability evaluation by electron beam irradiation, it is possible to perform a pseudo circuit pattern reliability evaluation during the semiconductor manufacturing process. I found it. For example, a case where a TDDB characteristic is evaluated for a gate pattern will be described.

  The TDDB characteristic is a dielectric breakdown characteristic when a voltage is applied to the oxide film for a long time. For example, the TDDB characteristic is shown as a characteristic as shown in FIG. Time Tl is the time until the gate insulating film breaks down. It is known that TDDB is accelerated by a stress electric field Eox applied to the gate insulating film and a temperature Ta as shown in the equation (1).

Tl = A · 10 ^−βEox · exp (Ea / kTa) (1)
Here, β is an electric field acceleration coefficient, Ea is a temperature acceleration coefficient, and k is a Boltzmann coefficient. The circuit pattern temperature Ta is an absolute temperature, and A is a constant. Alternatively, the dielectric breakdown characteristics of TDDB may be expressed by equation (2).

Tl = A · exp (−B / Eox) · exp (Ea / kTa) (2)
As described above, in order to evaluate the reliability of the circuit pattern during the semiconductor manufacturing process, means for applying the stress electric field Eox to the wafer stably for a predetermined time, and further adjusting the temperature Ta of the circuit pattern. Means are needed. A means for applying such an electrical load to the wafer during the semiconductor manufacturing process and inspecting the reliability of the circuit pattern will be described below.

  As a first means, there is provided means for irradiating a circuit pattern on the wafer with an electron beam to charge the wafer surface positively or negatively for a predetermined time. For example, as shown in FIG. 4, an electron optical system for irradiating the wafer with an electron beam for a desired time is provided. Further, electrodes 34a and 34b for controlling a charging voltage on the wafer surface by applying a desired voltage to the wafer upper surface are provided. By applying a voltage to the electrodes 34a and 34b to adjust the electric field formed on the upper surface of the wafer, the trajectory of secondary electrons generated when the wafer is irradiated with an electron beam is controlled, and the charging of the wafer surface is controlled. It became possible to do. For example, when the wafer surface is positively charged, the primary electron beam is irradiated with an irradiation energy at which the secondary electron emission efficiency from the wafer is 1 or more. At this time, when a positive voltage is applied to the electrodes 34a and 34b on the upper surface of the wafer, as shown in FIG. 5, for example, secondary electrons 112 generated from the wafer surface are efficiently drawn out to the upper surface of the wafer, and the wafer surface becomes positive. Charge. On the other hand, when negatively charging the wafer surface, when a negative voltage is applied to the electrodes 34a and 34b on the upper surface of the wafer, the secondary electrons 111 generated from the wafer surface are pulled back to the wafer surface and charged negatively. A function of irradiating a predetermined region with an electron beam stably for a predetermined time is provided. As a result, a desired electric field can be applied to a desired pattern on the wafer during the semiconductor manufacturing process for a desired time.

  As a second means, means for applying a load by electron beam irradiation to a desired position of the circuit pattern on the wafer was provided. For example, as in the first means, an electron optical system for irradiating a small area at a predetermined position on the pattern with an electron beam having a desired energy on the wafer is provided. First, a secondary electron image is acquired as an initial state inspection before an electrical load is applied, and a region to which a load is applied is determined from the acquired secondary electron image. Then, by passing an electron beam with adjusted energy and irradiation amount through a predetermined position of the circuit pattern, a load is applied to a predetermined region of the circuit pattern to evaluate the reliability. By irradiating a part of the circuit pattern with an electron beam, a load can be applied locally to the circuit pattern, and the cause of the decrease in reliability can be estimated at an early stage. For example, in the case of the gate pattern shown in FIG. 3, only the edge portion (122) of the gate electrode 123 can be irradiated with an electron beam, and a load can be selectively applied to the edge portion (122). Can be attributed to the edge portion (122) of the gate. A function for recognizing the same part of the repetitive pattern and irradiating the electron beam under the same condition was provided.

  As a third means, a means for controlling the temperature of a desired circuit pattern on the wafer was provided. For example, as shown in FIG. 4, a function for controlling the temperature by irradiating a desired pattern with laser light is provided. In order to control the temperature of the surface, the laser beam can be irradiated in a pulse form. Furthermore, a thermometer for measuring the pattern temperature was provided, and a mechanism for automatically adjusting the output of the laser beam was provided. Further, the electron beam irradiation described in the first means or the second means and the laser light irradiation as the third means can be performed on the same pattern on the wafer, and the temperature control of the circuit pattern is possible. Application of stress voltage by electron beam irradiation can be performed on the same pattern.

  As a fourth means, an electron beam for acquiring a secondary electron image is applied to the wafer before and after applying a load to the circuit pattern of the wafer to be inspected by the electric load applying means described in the first, second and third means. A function was provided for obtaining the potential contrast of the secondary electrons generated by irradiation and evaluating the electrical characteristics of the circuit pattern. First, as shown in FIG. 4, the position on the XY stage 16 when the load is applied by the electrical load applying means described in the first, second, and third means and secondary electrons generated by electron beam irradiation. A mechanism for accurately moving between the position on the XY stage 16 when acquiring the potential contrast is provided. Furthermore, an alignment function for irradiating the electron beam by adjusting the electron beam irradiation region when applying the electrical load and the electron beam irradiation region when acquiring the secondary electron image to be precisely matched is provided. As a result, the potential contrast before and after the load application by electron beam irradiation can be acquired at high speed, and the comparison evaluation can be performed with high accuracy. Further, there is provided means for acquiring a secondary electron image of a pattern to which an electrical load is applied, evaluating an electrical characteristic of the circuit pattern from the acquired secondary electron image, and displaying a temporal change in the circuit characteristic due to stress application. Provided.

  Briefly explaining the effects obtained by typical ones of the inventions disclosed in the present application, it is possible to detect a defect in reliability of the semiconductor device at an early stage, and to realize reduction in manufacturing cost and the like.

  In the following embodiments, when referring to the number of elements, etc. (including the number, numerical value, quantity, range, etc.), unless otherwise specified and in principle limited to a specific number in principle, It is not limited to the specific number, and it may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps) are not necessarily indispensable unless otherwise specified and clearly considered essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  First, an example of a method and apparatus for performing TDDB evaluation of a wafer in the middle of a semiconductor manufacturing process will be described. FIG. 4 shows a configuration example of the semiconductor inspection apparatus (reliability inspection apparatus) in this embodiment. The semiconductor inspection apparatus 1 includes an inspection system 50, a load application system 51, a stage mechanism system 3, a wafer transfer system 4, a vacuum exhaust system 5, an optical microscope 6, and an operation system 8.

  The inspection system 50 includes an electron optical system 2 and a control system 7. The electron optical system 2 includes an electron gun 9a, a condenser lens 10a, an objective lens 11a, an electrode 34a, a detector 12a, an energy filter 13a, a deflector 14a, and a wafer height detector 15a. The control system 7 includes a signal detection system control unit 22, a blanking control unit 23, a beam deflection correction control unit 24, an electron optical system control unit 25, a wafer height sensor detection system 26, a stage control unit 27, and an electrode control unit 33. It is configured.

  The load application system 51 includes an electron optical system 52, a wafer temperature adjustment system 56, and a load application control system 57. The electron optical system 52 includes an electron gun 9b, a condenser lens 10b, an objective lens 11b, an electrode 34b, a detector 12b, an energy filter 13b, a deflector 14b, and a wafer height detector 15b. The load application control system 57 includes a signal detection system control unit 72, a blanking control unit 73, a beam deflection correction control unit 74, an electron optical system control unit 75, a wafer height sensor detection system 76, an electrode control unit 77, and a laser optical system. The controller 78 and the temperature controller 79 are included. The wafer temperature adjustment system 56 includes a laser light source 66, a laser optical system 67, and a thermometer 68. As described above, the load application system 51 is configured such that the temperature adjustment means (the wafer temperature adjustment system 56, the laser optical system control unit 78, and the temperature control unit 79) is added to the inspection system 50. In this semiconductor inspection apparatus 1, the inspection system 50 and the load application system 51 are separated and the inspection and the load application are performed in parallel to improve the throughput. It is also possible to configure so that load application is performed in order.

  The stage mechanism system 3 includes an XY stage 16, a holder 17 for holding the wafer 18, and a retarding power source 19 for applying a negative voltage to the holder 17 and the wafer 18. A position detector by laser length measurement is attached to the XY stage 16. The distance between the electron optical system 2 of the inspection system 50 and the electron optical system 52 of the load application system 51, the wafer temperature adjustment system 56, or the optical microscope 6 is known, and the XY stage 16 is known. It is designed to reciprocate the distance. That is, the wafer 18 can move between the load application system 51 and the inspection system 50 with high positional accuracy. The wafer transfer system 4 is configured such that the wafer 18 can travel between the cassette mounting unit 20, the wafer loader 21, and the XY stage 16. The operation system 8 includes an operation screen and operation unit 28, an image processing unit 29, an image / inspection data storage unit 30, a calculation unit 31, and an external server 32.

  A method of performing TDDB inspection using such a semiconductor inspection apparatus 1 will be described according to an inspection flow. FIG. 1 shows an example of an inspection flow.

  First, the wafer 18 is set, and the shelf number in the cassette of the wafer 18 to be inspected is designated on the operation screen 28 (step 80). Then, pattern information such as a shot matrix, a gate area, and a gate oxide film thickness is input from the operation screen as information on the wafer 18 to be inspected (step 81). Next, various inspection conditions are input from the operation screen. As the electrical property inspection conditions, electron beam current, electron beam irradiation energy, scanning speed and signal detection sampling clock, visual field size per screen, number of image acquisitions per screen, acquired image used for image processing, inspection region, inspection target Conditions such as various information about the wafer 18 are input (step 82). In addition, the electric load application conditions include an electron beam current at the time of applying the electric load, an electron beam irradiation energy, a scanning speed, a visual field size per screen, the number of electron beam scans, an electron beam irradiation time, and the electrode 34b on the upper surface of the wafer. Conditions such as voltage, wafer surface charging voltage, circuit pattern control temperature, and electrical load application time are input (step 83). In addition, when applying an electrical load locally to a pattern to be inspected, a region to be irradiated with an electron beam is designated for a secondary electron image acquired in advance.

  Further, in steps 82 and 83, contents such as whether to automatically inspect a plurality of wafers 18 continuously or whether to inspect the same wafer 18 continuously under different inspection conditions are input. Although it is possible to input individual parameters, usually, if pattern information, inspection area, and electrical load application conditions are specified, the combination of the above various inspection parameters is set as an inspection condition file according to the pattern information to be inspected. The database is stored in the image / inspection data storage unit 30, and it is only necessary to select and input an inspection condition file. When these condition inputs are completed, the inspection is started.

  When the automatic inspection is started, the set wafer 18 is first transferred into the semiconductor inspection apparatus 1. The wafer 18 to be inspected is placed on the holder 17 by a wafer loader 21 including an arm, a preliminary vacuum chamber, and the like from the cassette placement unit 20, held and fixed, and evacuated in the wafer loader 21 together with the holder. 5 is transported to an examination room which is in a vacuum (step 84). When the wafer is loaded, the electron optical system control unit 25 sets the electron beam irradiation condition for each unit based on the input inspection conditions. Thereafter, the semiconductor inspection apparatus 1 moves the XY stage 16 so that the beam calibration pattern placed on the holder 17 is below the electron optical system 2 (step 85), and an electron beam image of the beam calibration pattern. And the focus and astigmatism are adjusted from the image (step 86). Subsequently, an electron beam image of the wafer 18 is acquired for a predetermined location on the wafer 18 to be inspected, and the contrast and the like are adjusted. Here, when it becomes necessary to change the electron beam irradiation conditions or the like, it is possible to change the parameters and perform the beam calibration again. Further, the height of the wafer 18 is obtained from the wafer height detector 15, and the correlation between the height information and the focusing condition of the electron beam is obtained by the wafer height sensor detection system 26. It is also possible to automatically adjust to the in-focus condition from the result of the wafer height detector 15 without executing the above.

  When the electron beam irradiation conditions and the focus and astigmatism adjustment are completed, alignment is performed using two or more points on the wafer 18. In the inspection, it is necessary to view a set area in the wafer 18 or chip with high accuracy. Therefore, the semiconductor inspection apparatus 1 automatically executes alignment using alignment conditions and alignment images registered in advance before executing the visual field observation of the defective portion (step 87). When the alignment is completed, the rotation and coordinate values are corrected based on the alignment result, and then the second calibration pattern placed on the holder 17 is moved. The second calibration pattern is a transistor in which a normal junction is formed in advance or a pattern corresponding to the transistor, and the brightness of the normal part is calibrated using the pattern. Based on this result, the wafer is moved onto the wafer 18, an image of a pattern portion on the wafer is acquired, and brightness adjustment, that is, calibration is performed (step 88).

  When calibration is completed, the semiconductor inspection apparatus 1 starts inspection (step 89). When the inspection is started, the semiconductor inspection apparatus 1 acquires a secondary electron image while scanning an electron beam in a specified area under a specified inspection condition (step 90), and stores the secondary electron image. (Step 91). At the time of acquiring a secondary electron image, image acquisition can be performed by step-and-repeat. Subsequently, defect determination is performed based on the acquired secondary electron image (step 92). At this time, the variation in leakage current can also be evaluated from the variation in brightness of the acquired secondary electron image. It is also possible to perform defect processing by performing image processing in real time when acquiring a secondary electron image. The inspection status is displayed on the operation screen 28, and the inspection data is output to the external server 32 or the like via the data converter (step 93).

  Here, a method for performing defect determination using a secondary electron image will be described. For example, FIG. 5 shows an explanatory diagram showing a charged state when the gate pattern is irradiated with an electron beam. First, an electron beam is irradiated using the inspection electron optical system of the semiconductor inspection apparatus. When the gate electrode 110 is positively charged, the irradiation energy of the electron beam is selected so that the secondary electron emission efficiency of the gate electrode is 1 or more. When the electron beam is irradiated under the above conditions, more secondary electrons are generated than the irradiated electron beam, and the gate electrode is positively charged. When the gate electrode is positively charged, the low energy secondary electrons 111 are drawn back to the wafer surface, while the high energy secondary electrons 112 reach the detector.

  Here, the electric field on the wafer upper surface is determined by the voltage applied to the electrodes 34a and 34b installed on the wafer upper surface, the trajectory of the secondary electrons is controlled, and the secondary electrons that return to the wafer surface and the detected secondary electrons are controlled. Is done. Accordingly, the charging voltage of the gate electrode 110 can be controlled by the electron beam irradiation conditions such as the electron beam irradiation energy and the electric field on the upper surface of the wafer. In this way, the charging voltage of the gate electrode 110 is controlled, and the contrast of the secondary electron image is formed. When the gate insulating film 113 is broken down, even if the gate electrode 110 is irradiated with an electron beam, the current is instantaneously supplied from the Si substrate 114 through the gate insulating film 113, so that the gate electrode 110 is not charged. Therefore, the gate electrode 110 in which the gate insulating film 113 is broken down is observed brighter than the secondary electron image of the normal gate electrode. Therefore, the brightness of the secondary electron image changes depending on the leakage current of the gate insulating film 113.

  FIG. 6 shows the cumulative frequency distribution of the signal intensity of the gate electrode portion of the acquired secondary electron image. Thus, the main distribution of the pattern to be inspected and the dropout detected as a bright secondary electron image could be evaluated from the signal intensity distribution. By setting a threshold value 115 for determining a defect, the defect could be detected.

  When the inspection of the initial state of the pattern to be inspected is completed, an electrical load is applied for reliability evaluation. First, the semiconductor inspection apparatus 1 controls the XY stage 16 to move the wafer 18 to a predetermined position in the load application system 51. Next, based on the input electrical load application condition, the electron optical system controller 75 sets an electron beam irradiation condition for each part. Then, the XY stage 16 is controlled so that the beam calibration pattern placed on the holder 17 is under the electron optical system 52 (step 94), and an electron beam image of the beam calibration pattern is acquired. The focus and astigmatism are adjusted (step 95). Thereafter, the wafer is moved to a predetermined location on the wafer 18 to be inspected, an electron beam image of the wafer 18 is acquired, and contrast and the like are adjusted. Here, when it becomes necessary to change the electron beam irradiation conditions or the like, it is possible to change the parameters and perform the beam calibration again. Further, the height of the wafer 18 is obtained from the wafer height detector 15b, and the correlation between the height information and the focusing condition of the electron beam is obtained by the wafer height sensor detection system 76, and every time the electron beam image is acquired thereafter, the focal point is obtained. It is also possible to automatically adjust to the in-focus condition from the result of the wafer height detector 15b without executing alignment.

  When the electron beam irradiation conditions and the focus and astigmatism adjustments are completed, alignment is performed using two or more points on the wafer 18 (step 96). In the inspection, it is necessary to view a set area in the wafer 18 or chip with high accuracy. Therefore, the semiconductor inspection apparatus 1 automatically executes alignment using alignment conditions and alignment images registered in advance before executing the visual field observation of the defective portion. With this alignment, the correspondence between the electron beam irradiation region at the time of acquiring the secondary electron image for inspection in the inspection system 50 and the electron beam irradiation region in the case of applying an electrical load in the load application system 51 is precisely determined. It is possible to take.

  When the alignment is completed, the rotation and coordinate values are corrected based on the alignment result, and then the second calibration pattern placed on the holder 17 is moved. The second calibration pattern is a transistor in which a normal junction is formed in advance or a pattern corresponding to the transistor, and the brightness of the normal part is calibrated using the pattern. Based on this result, the wafer is moved onto the wafer 18, an image of a pattern portion on the wafer is acquired, and brightness adjustment, that is, calibration is performed (step 97). Note that the calibration only needs to be performed once at the beginning. In the case of the second and subsequent times following the loop processing returning from step 101 to step 90 described later, the processing is omitted, and the calibration was obtained when the first time it was performed. A set value can be used.

  When the calibration is completed, the semiconductor inspection apparatus 1 controls the XY stage 16 and moves the wafer 18 so that the region to which the electrical load is applied is directly below the electron optical system 52 for applying the electrical load (step 98). ). As described above, for example, when the inspection system 50 is configured to share the load application system, the wafer 18 is moved so that the region to which the electrical load is applied is directly below the electron optical system 2. .

  Next, the semiconductor inspection apparatus 1 starts application of an electrical load, and irradiates and scans a specified time electron beam in a specified region under specified inspection conditions (step 99). At this time, if it is necessary to control the temperature, the wafer temperature in the electrical load application region can be controlled by performing laser beam irradiation simultaneously with electron beam irradiation (step 106). The electron beam irradiation conditions in step 99 are set so that the pattern surface has a desired charging voltage. The method of controlling the pattern surface to a desired charging voltage using an electron beam is the same as the method of charging the pattern surface at the time of acquiring the inspection image, and the irradiation condition of the electron beam such as the irradiation energy of the electron beam and the wafer upper surface The charging voltage of the gate electrode 110 can be controlled by adjusting the voltage applied to the electrode 34b. When an electrical load is applied, a spot beam can be scanned over the irradiation region as an electron beam, or a forming beam spread broadly over the irradiation region can be irradiated. Further, it is confirmed at any time whether the pattern surface is charged to a desired charging voltage, and when the charging voltage is out of the allowable value, the electron beam irradiation conditions and the electrode voltage on the upper surface of the wafer can be set again.

  Here, an example of a method for measuring the charging voltage on the wafer surface will be described. Here, an example of a method for measuring the charging voltage using the energy filter 13b installed in the previous stage of the detector 12b will be described. FIG. 7 shows the relationship between the filter voltage dependence of the signal intensity of the secondary electron image and the charging voltage. First, the voltage of the energy filter 13b is set to a value sufficiently higher than the energy of secondary electrons to be detected, and a secondary electron image is acquired. Next, the value of the filter voltage is set by changing the step width ΔVf, and a secondary electron image is acquired. The filter voltage setting and the secondary electron image acquisition are repeated until the secondary electron image becomes sufficiently dark, and the filter voltage dependency 116 of the signal intensity of the secondary electron image as shown in FIG. 7 is acquired. By obtaining in advance the filter voltage dependency 117 of the signal intensity of the secondary electron image of a sample having a charging voltage of 0 V, such as a bare wafer made of a conductive material, and calculating the shift amount between them. The charging voltage Vc can be measured. In addition, the charging voltage can be obtained using a means such as a Kelvin probe.

  Next, the relationship between the electron beam irradiation region for applying an electric load and the electron beam irradiation region for inspection will be described. FIG. 8 shows an example of the relationship between the electrical load application area 119 and the inspection area 118. FIG. 8 shows a case where a large number of patterns are simultaneously applied with an electrical load. By irradiating an electron beam to a wide area at a time, a uniform load can be applied to a large number of patterns in a short time. When the inspection pattern is small, or when inspection is performed on different electrical load application conditions on a single wafer, the inspection region 118 and the electrical load application region 119 can be set substantially equal.

  Although the case where an electrical load is applied by a charging voltage generated by electron beam irradiation has been described so far, an electrical load can be applied to a pattern by passing the electron beam through a desired region. In this method, for example, the evaluation of the hot carrier effect can be performed in a pseudo manner. The hot carrier effect is due to the fact that the electric field near the drain of the MOSFET becomes very large, and electrons accelerated at high speed are generated, and some of the high-energy electrons and holes are injected into the gate oxide film by the electrons. It is a phenomenon that generates hot carriers. By injecting an incident electron beam or secondary electrons generated by the incident electron beam into the gate oxide film, a pseudo carrier effect can be generated. As the energy of the incident electron beam in this case, for example, the energy of the electron beam having a range larger than the thickness of the gate electrode is effective.

  When an electrical load is applied by a method of passing an electron beam through a desired region, it is possible to apply a load locally to the pattern. FIG. 9 shows an example of the relationship between the inspection region 121 and the electrical load application region 122 when a load is applied locally to the gate pattern. As shown in FIG. 9, an electrical load can be applied to an area smaller than the inspection area 121. For example, in the case of a gate pattern, for example, by comparing the case where an electrical load is applied near the edge of the gate electrode 123 with the case where an electrical load is applied to the entire gate electrode 123, reliability in the circuit pattern is reduced. It is possible to specify a place where it is easy to wake up. Alternatively, by comparing the boundary region between the active region 124 and the element isolation region 125 under the gate pattern and the case where an electrical load is applied to the entire gate electrode 123, a place where the reliability is likely to be lowered can be specified. it can. As described above, when an electrical load is applied locally, alignment can be automatically executed using a previously registered alignment condition and alignment image in the vicinity of the pattern to which the load is applied.

  Further, it is possible to control the temperature at the time of applying an electrical load by electron beam irradiation as described above (step 106). That is, as a means for heating the wafer, a structure capable of irradiating the region including the electric load application region with laser light is provided. For example, as shown in FIG. 8, the laser light emitted from the laser light source 66 is applied to a region 120 wider than the region irradiated with the electric load applying electron beam, for example. As the laser light source 66, for example, a semiconductor laser or the like can be used. In order to adjust the temperature of the circuit pattern, the laser output and the laser pulse interval are adjusted. The temperature adjustment is performed by the thermometer 68 measuring the temperature of the laser irradiation unit in real time, and the temperature control unit 79 adjusting the laser output and the laser pulse interval according to the measured temperature. When the inspection pattern is directly irradiated with laser light, there is a possibility that the inspection pattern may be influenced in addition to the temperature rise. In such a case, the temperature of the pattern can be indirectly controlled by laser irradiation from a region slightly away from the electron beam irradiation unit or from the back surface of the wafer.

  As another method for heating the wafer 18, for example, a heater is embedded in the XY stage 16, and the temperature can be adjusted before the electron beam irradiation. If the temperature of the pattern is changed during inspection, there may be a slight displacement in the electron beam irradiation area, and an electric load cannot be applied to the predetermined pattern, or an inspection image of the predetermined pattern may not be acquired. is there. In such a case, alignment may be automatically executed using alignment conditions and alignment images registered in advance in a temperature controlled region such as the laser light irradiation region 120.

  When the first electrical load application is thus completed, the semiconductor inspection apparatus 1 moves the wafer 18 again to a predetermined stage position in the inspection system 50 and performs an inspection after applying the electrical load ( Step 101). The second and subsequent inspections are desirably performed under the same conditions as before applying the electrical load. If there is an influence of residual charging when an electrical load is applied, a charge removal process is performed before inspection (step 100). Examples of the static elimination method include a method of irradiating an electron beam under an electron beam irradiation condition so as to be charged with a polarity opposite to that at the time of inspection, or a method of performing a charge removal process by irradiating ultraviolet light. During the second and subsequent inspection image acquisition, beam adjustment (step 86), wafer alignment (step 87), and calibration (step 88) can be omitted. When the inspection image is acquired, the wafer 18 is moved again to the load application system 51 (step 94), and an electric load is applied by electron beam irradiation and temperature adjustment (step 99). FIG. 10 shows the relationship between the stress application and the inspection image acquisition timing. In this way, inspection data is acquired by repeating inspection and load application.

  The inspection status is displayed on the operation screen 28 as needed, and the inspection data is stored in the image / inspection data storage unit 30. When the inspection is completed (step 102), an inspection result file in which each inspection data is collected is generated in the image / inspection data storage unit 30 (step 103), and the wafer 18 is unloaded (step 104). The inspection result file can be displayed on the operation screen 28 (step 105), and can also be output to the external server 32 or the like. A display example of the inspection result is shown in FIG. FIG. 11 is a display example of the TDDB characteristic obtained by the inspection as described above. As shown in FIG. 11, the change in the defect rate with the electrical load application time can be evaluated by summing up and discriminating the above-described inspection data using the arithmetic unit 31 or the like.

  Further, by summing up and discriminating the above-described inspection data using the arithmetic unit 31 or the like, it is also possible to display information on defective shot distribution and wafer surface distribution on the operation screen 28 or the like. FIG. 12 shows a display example of the in-wafer surface distribution 126 of defective portions. In this way, for example, the drop pattern portion 127 can be classified and displayed according to the electric load application time. Specifically, first, as a first step, an electrical load is applied to each circuit pattern for a plurality of circuit patterns arranged at different locations in the wafer surface by the processing of step 90 and the like described above. The contrast (first potential contrast) of the previous secondary electron image is acquired. Next, as a second stage, an electrical load is applied to each circuit pattern by the process of step 99 and the like, and then the process returns to step 90 and the contrast of the secondary electron image after the electrical load is applied ( (Second potential contrast) is acquired. Thereafter, the second stage process is repeatedly performed, and accordingly, the electrical load application time is accumulated. Each time the second stage process is performed, the calculation unit 31 and the like compare and determine the difference value between the first potential contrast and the second potential contrast by the process in step 92 and the like, and the difference value is determined in advance. When it becomes larger than the threshold value, the corresponding circuit pattern is determined as a failure. Then, the calculation unit 31 and the like determine the accumulation time of the electric load application time at the time when the failure is determined as the ability value of the TDDB characteristic of the corresponding circuit pattern. FIG. 12 shows the distribution of the ability values of the circuit patterns in the wafer surface thus obtained. Similarly, as shown in FIG. 12, an enlarged display in the shot 128 can be performed.

  In the TDDB characteristics, a pattern that normally causes dielectric breakdown is regarded as defective. However, a threshold value is provided for the leakage current depending on the type of device, and a pattern that has a leakage current that is equal to or greater than the threshold value can be displayed as defective. For example, there are cases where defects frequently occur around the wafer, or defects occur around the shot or at places where the pattern density is sparse. The above result display is useful for accurately grasping the characteristics of such distribution, identifying the cause of the occurrence of defects, and taking measures such as process improvement at an early stage. As a result, it becomes possible to identify the process and the cause of defects at an early stage, enabling feedback to the semiconductor manufacturing process at an early stage, starting the manufacturing process at an early stage, and increasing the product yield at an early stage. Can be improved.

  The main effects obtained by using the semiconductor inspection method of this embodiment are summarized as follows.

  First, it has become possible to evaluate the reliability of a wafer in the middle of a semiconductor manufacturing process. For example, it becomes possible to evaluate reliability such as degradation of MOS characteristics due to TDDB, PBTI, NBTI, or hot carrier effect. In addition, for example, by applying an electrical load that generates hot carriers by electron beam irradiation, the load application time can be shortened compared to the conventional application method, and thus the evaluation time can be shortened. It was. Further, since a load can be locally applied to the circuit pattern, it is possible to evaluate which part of the circuit pattern is a cause of reliability deterioration, and the efficiency of the countermeasure is greatly improved. In addition, since it is now possible to evaluate reliability during the manufacturing process without creating a circuit pattern to the end, it is possible to immediately determine the quality of the process when optimizing the process conditions. The efficiency has been greatly improved, and as a result, the development period and yield improvement period of the semiconductor manufacturing process can be greatly shortened.

  In addition, since the distribution of reliability degradation within the wafer surface can be immediately identified, it is possible to grasp the correspondence with other in-line inspection results and the distribution within the wafer surface of the substrate manufacturing process at high speed and with high accuracy. As a result, it has become possible to take measures against abnormalities quickly, and as a result, the defect rate of semiconductor devices and other substrates can be reduced and productivity can be increased. In addition, it has become possible to quickly detect abnormalities and take countermeasures earlier than before, so that it is possible to prevent a large number of defects before they occur and improve the reliability of semiconductor devices. . As a result, the development efficiency of new products and the like can be improved, and the manufacturing cost can be reduced.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention.

  A semiconductor inspection method according to an embodiment of the present invention is a technique that is particularly useful when applied to an in-line inspection process performed in a pre-process of a semiconductor device, and is not limited thereto, and is an analysis technique when a defective product occurs. As such, it can be widely applied as an evaluation method for semiconductor devices such as an evaluation technique for process development.

It is a figure which shows an example of the test | inspection flow in the semiconductor test | inspection method by one embodiment of this invention. It is explanatory drawing which shows an example of a TDDB characteristic. It is explanatory drawing which shows an example of the electrical load application method to a gate pattern in the semiconductor inspection method by one embodiment of this invention. In the semiconductor inspection method by one embodiment of this invention, it is a block diagram which shows an example of the semiconductor inspection apparatus used for it. In the semiconductor inspection method by one embodiment of this invention, it is explanatory drawing which shows an example of the charged state when an electron beam is irradiated to a gate pattern. It is explanatory drawing which shows the cumulative frequency distribution of the signal strength of the secondary electron image in a gate electrode part in the semiconductor inspection method by one embodiment of this invention. It is explanatory drawing which shows the filter voltage dependence of the signal strength of a secondary electron image in the semiconductor inspection method by one embodiment of this invention. In the semiconductor inspection method by one embodiment of this invention, it is explanatory drawing which shows an example of the relationship between an electrical load application area | region and an inspection area | region. In the semiconductor inspection method by one embodiment of this invention, it is explanatory drawing which shows an example of the relationship between the test | inspection area | region in the case of applying an electrical load only to a gate pattern edge part, and an electrical load application area | region. It is explanatory drawing which shows an example of the timing of electrical load application and test | inspection image acquisition in the semiconductor test | inspection method by one embodiment of this invention. In the semiconductor inspection method by one embodiment of this invention, it is explanatory drawing which shows the example of a display of a TDDB characteristic evaluation result. In the semiconductor inspection method by one embodiment of this invention, it is explanatory drawing which shows the example of a display in the wafer surface distribution of the defective location of a TDDB characteristic evaluation result.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor inspection apparatus 2 Electron optical system 3 Stage mechanism system 4 Wafer conveyance system 5 Vacuum exhaust system 6 Optical microscope 7 Control system 8 Operation system 9a, 9b Electron gun 10a, 10b Condenser lens 11a, 11b Objective lens 12a, 12b Detector 13a , 13b Energy filters 14a, 14b Deflectors 15a, 15b Wafer height detector 16 XY stage 17 Holder 18 Wafer 19 Retarding power supply 20 Cassette mounting unit 21 Wafer loader 22 Signal detection system control unit 23 Blanking control unit 24 Beam deflection correction Control unit 25 Electron optical system control unit 26 Wafer height sensor detection system 27 Stage control unit 28 Operation screen 29 Image processing unit 30 Image / inspection data storage unit 31 Calculation unit 32 External server 33 Electrode control unit 34a, 34b Electrode 50 For inspection System 5 DESCRIPTION OF SYMBOLS 1 Load application system 52 Electron optical system 56 Wafer temperature adjustment system 57 Load application control system 66 Laser light source 67 Laser optical system 68 Thermometer 72 Signal detection system control part 73 Blanking control part 74 Beam deflection correction control part 75 Electron optical system Control unit 76 Wafer height sensor detection system 77 Electrode control unit 78 Laser optical system control unit 79 Temperature control unit 110 Gate electrodes 111 and 112 Secondary electrons 113 Gate insulating film 114 Si substrate 115 Threshold value 116 Filter voltage of pattern to be inspected Dependency 117 Dependence of filter voltage on uncharged pattern 118 Inspection area 119 Electric load application area 120 Laser light irradiation area 121 Inspection area 122 Electric load application area 123 Gate electrode 124 Active area 125 Element isolation area 126 In wafer surface distribution 127 Overflow pattern part 128 shots

Claims (5)

A first step of irradiating a surface of a semiconductor substrate on which a circuit pattern is formed with a first electron beam;
A second step of detecting first secondary electrons emitted from the semiconductor substrate by irradiation of the first electron beam;
A third step of obtaining a first potential contrast signal based on the first secondary electrons;
A fourth step of irradiating a predetermined amount of a second electron beam onto a region including the circuit pattern irradiated with the first electron beam and applying an electric load for a predetermined time to a part of the circuit pattern;
A fifth step of irradiating a region including the circuit pattern irradiated with the first electron beam with a third electron beam under irradiation conditions equivalent to the first electron beam;
A sixth step of detecting second secondary electrons emitted from the semiconductor substrate by irradiation of the third electron beam;
A seventh step of obtaining a second potential contrast signal based on the second secondary electrons;
A semiconductor inspection method comprising: an eighth step of discriminating and displaying an electrical characteristic of the circuit pattern from a variation amount of the first potential contrast signal and the second potential contrast signal. The semiconductor inspection method according to claim 1,
In the eighth step, the variation in the electrical characteristics of the circuit pattern in the wafer surface is displayed. The semiconductor inspection method according to claim 1,
A part of the circuit pattern irradiated with the second electron beam in the fourth step is a gate electrode, and the durability of the insulating film under the gate electrode is determined by the eighth step. Semiconductor inspection method. The semiconductor inspection method according to claim 1,
In the fourth step, a process of generating hot carriers in a pseudo manner by passing the second electron beam through a part of the circuit pattern that is presumed to be defective is performed. A semiconductor inspection method, wherein the durability of a part of the circuit pattern is determined. The semiconductor inspection method according to claim 1,
The semiconductor inspection method further comprises a ninth step of adjusting the circuit pattern to a predetermined temperature before the fourth step.

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