JPH04290242A - Inspection method of semiconductor element - Google Patents

Abstract

PURPOSE:To provide the inspection method of a semiconductor element, which is used to evaluate a semiconductor manufacturing process, especially a process to form a contact hole. CONSTITUTION:One or a plurality of conductor interconnections 2, 4 of a contact chain where the conductor interconnections 2, 4 have been formed so as to pass, in series, many through-holes which have been formed on an insulating film 5 on a semiconductor substrate 6 and which have been formed in an interlayer insulating film are connected electrically to the semiconductor substrate 6; after that, the secondary electron image of the contact chain is observed by using a focused ion beam(FIB) apparatus or a scanning electron microscope(SEM). The disconnected part, of the contact chain, which could not be detected by conventional electric measuring operations only can be detected easily, and the structural analysis of the disconnected part can be achieved. As a result, the cause of a disconnection can be fed back quickly.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing process, and more particularly to a semiconductor device inspection method for evaluating processes related to contact hole formation.

0002

[Prior Art] One of the evaluation devices used for process evaluation in the manufacture or development of semiconductor devices is several hundred.
There is a device (hereinafter referred to as a contact chain) in which several thousand contacts are connected in series by forming zero contact holes and connecting the top and bottom of the contact holes with conductors. This device verifies whether contact holes are being formed reliably.
The quality of the process applied to manufacturing or development is determined by whether there is continuity in the contact chain and whether the resistance of the contact chain is less than or equal to the designed electrical resistance value.

A conventional semiconductor device testing method will be explained below. FIG. 4(a) is a schematic diagram of a contact chain used in a conventional semiconductor device testing method.
b) is a schematic cross-sectional view taken along line AB in FIG. 4(a). In these figures, 1c and 1d are pads for electrical measurement, 2 is a second wiring, and 3 is a second wiring and a first wiring 4.
5 is an insulating film on the semiconductor substrate 6;
7 is a surface protective film. In the case of an inspection method using electrical measurement, metal needles (probes) are attached to pads 1c and 1d for electrical measurement.
The resistance value (voltage value/current value) of the contact chain is calculated by applying a voltage between these two metal needles and measuring the flowing current, and from that resistance value, the contact chain's resistance value is calculated. We determine pass/fail and evaluate the process.

0004

[Problems to be Solved by the Invention] However, with the above-mentioned conventional configuration, although it is possible to evaluate the entire contact chain, there is a problem in that it is not possible to identify a disconnection point in a contact chain that has several thousand contact holes. had.

The present invention solves the above-mentioned conventional problems, and by making it easy to clarify the cause of disconnection in contact holes and quickly feeding back the results, it is possible to stabilize the yield of the semiconductor device manufacturing process or shorten the semiconductor device development period. An object of the present invention is to provide a semiconductor device testing method that enables the testing of semiconductor devices.

[0006]

[Means for Solving the Problems] In order to achieve this object, the semiconductor device testing method of the present invention includes a method for inspecting a semiconductor device that includes a plurality of through holes formed in an interlayer insulating film provided on an insulating film of a semiconductor substrate. After electrically connecting one or more places of the conductor wiring of the contact chain formed by passing through the conductor wiring in series to the semiconductor substrate, using a focused ion beam (FIB) device or a scanning electron microscope (SEM), It has a configuration for observing secondary electron images of contact chains.

[0007]

[Operation] With this configuration, it is possible to easily find the breakage point of the contact chain. As a result, the cause of the disconnection can be quickly investigated through structural analysis, and feedback can be quickly provided to the semiconductor element manufacturing process or semiconductor element development process.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIGS. 1A to 1D are cross-sectional views for explaining a method for testing a semiconductor device according to an embodiment of the present invention. In FIG. 1, the same parts as in the conventional example shown in FIG. 4 are given the same reference numerals, and detailed explanations are omitted. Further, the plan view and cross-sectional view of the contact chain used in this example are the same as those in FIGS. 4(a) and 4(b), except for some parts.

The contact chain used in this example has 5000 contact holes as shown in FIG. 1(a), and has a first wiring 4, a second wiring 2
is aluminum silicon copper (AlSiCu) wiring, and interlayer insulating film 3 is boron phosphosilicate glass (BPSG).
The insulating film 5 is a thermal oxide film, and the semiconductor substrate 6 is a P-type (100
), a pad 1a for electrical measurement was formed with a second wiring having a size of 100 μm×100 μm, and a surface protection film 7 was formed of a two-layer film of SiN/PSG. Next, Figure 1
As shown in (b), the surface protective film 7 is coated with CF4+10%O
It is removed by plasma etching using gas No. 2. Next, as shown in FIG. 1(c), a pad 1a for electrical measurement is
A hole 9 smaller than the area of the pad 1a reaching the substrate 6 is formed at one location using an optical microscope equipped with a YAG laser. Next, as shown in FIG. 1(d), a conductive resin material 10a is applied to the position of the hole 9, and the pad 1a is connected to the semiconductor substrate 6. Thereafter, the entire surface of the contact chain is observed using a focused ion beam (hereinafter referred to as FIB) device or a scanning electron microscope (hereinafter referred to as SEM).

FIGS. 2(a) to 2(c) are cross-sectional views for explaining a semiconductor device testing method in a second embodiment of the present invention. The configuration of FIG. 2(a) is the same as that of FIG. 1(a), and a description thereof will be omitted. Next, as shown in FIG. 2(b), the surface protective film 7 is removed by plasma etching using CF4+10% O2 gas. Next, as shown in FIG. 2C, the pad 1b for electrical measurement and the divided area where the semiconductor substrate 6 is exposed or the fractured surface of the semiconductor substrate 1 are connected with a conductive resin material 10b. After this, the entire surface of the contact chain is observed using an FIB device or SEM.

FIG. 3 is a diagram illustrating the results of testing a contact chain using the semiconductor device testing method of this embodiment. First, after processing the sample using the above method, F
An ion-excited secondary electron image (hereinafter referred to as SIM
When observing the pad 1f connected to the board
The contact hole group 21 that is electrically conductive has higher brightness than the surrounding area, and the contact hole group 22 that is electrically connected has higher brightness than the surrounding area.
The contact hole group from the contact hole to the unprocessed pad 1e has low brightness (at about the same brightness as the surrounding area) and is observed in the SIM image. This is because Ga+ ions are used to excite the sample (contact chain) in the SIM image, so metals that are not connected to the insulator or semiconductor substrate 6 are charged to a positive potential when observing the SIM image, and have low energy. Secondary electrons are less likely to be emitted from the sample. Therefore, the second wiring 2 connected to the semiconductor substrate 6 is exposed to ion excitation.
The second wiring 2, which is not connected to the insulator or semiconductor substrate 6, is observed to have low brightness in the SIM image because it generates fewer secondary electrons due to ion excitation. It will be observed. S above
When the contrast boundary of the contact hole observed in the IM image was analyzed cross-sectionally using an FIB device, it was found that there was an aluminum wiring at the interface 23 between the first wiring 4 and the second wiring 2 of the contact hole 22 where the contrast in the SIM image changed to black. It turned out that there was a disconnection in some parts.

[0012]Furthermore, the location of the disconnection can also be identified by observing a secondary electron image using a SEM instead of the FIB device described above. In other words, the contact chain shown in Figure 1 or Figure 2 is completely disconnected when electrically measured.
When a secondary electron image of electronic excitation (hereinafter referred to as SEI) is observed using a SEM after the processing described in
Contrary to the contrast with the SIM image of the IB device, parts electrically connected to the pads connected to the semiconductor substrate 6 are observed to have low brightness, while parts not electrically connected to the semiconductor substrate 6 are observed to have high brightness. In this SEI, the contact hole in the high-brightness contact chain portion closest to the boundary between the low-brightness contact chain portion and the high-brightness contact chain portion is the disconnection location. In the case of electronic excitation, the second
This is because a material that is easily charged, such as the wiring 2 , generates more secondary electrons than the second wiring 2 connected to the semiconductor substrate 6 . In addition, when using SEM for observation, Figure 1 (
Similar effects can be expected even if the step of removing the surface protective film 7 in a) and FIG. 2(a) is omitted. This is because the electron radius of the atoms constituting the surface protective film 7 is several orders of magnitude smaller than the atomic radius of the Ga+ ion, and thus the electrons penetrate deeply into the substance. That is, Ga+ ions cannot pass through the surface protective film 7, but electrons cannot pass through the surface protective film 7.
and reaches the second wiring 2. The electrons that have reached the second wiring 2 connected to the semiconductor substrate 6
The amount of accumulated charge (potential) differs between the first wiring 2 and the second wiring 2 that is not connected to the semiconductor substrate 6, and the amount of secondary electrons emitted also changes, which appears as a difference in contrast (brightness) in SEI.

[0013]

[Effects of the Invention] As described above, in the semiconductor device testing method of the present invention, it is possible to easily find a breakage point in a contact chain, which was conventionally impossible by electrical measurement alone, and to analyze the structure of the breakage point. Since it is possible,
The cause of the disconnection can be quickly fed back to the semiconductor element manufacturing process or the semiconductor element development process, and the effect of stabilizing the yield of semiconductor elements or speeding up the development can be expected.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of each process for explaining a semiconductor device testing method in an embodiment of the present invention.

FIG. 2 is a cross-sectional view of each process for explaining the semiconductor device testing method in the second embodiment of the present invention.

[Figure 3] (a)
FIG. 3(b) is a plan view illustrating the results of testing a contact chain using the semiconductor device testing method of the present invention.
Cross-sectional view of a) taken along line A-B

FIG. 4(a) is a schematic diagram of a contact chain used in a conventional semiconductor device testing method; FIG. 4(b) is a cross-sectional view taken along line A-B in FIG. 4(a);

[Explanation of symbols]

2 Second wiring (conductor wiring) 3 Interlayer insulation film 4 First wiring (conductor wiring) 5 Insulating film 6 Semiconductor substrate

Claims (3)

[Claims] 1. One or more locations of the conductor wiring of a contact chain formed by serially penetrating a large number of through holes formed in an interlayer insulating film provided on an insulating film of a semiconductor substrate. A method for inspecting a semiconductor device, which comprises electrically connecting a contact chain to the semiconductor substrate and then observing a secondary electron image of the contact chain using a focused ion beam (FIB) device or a scanning electron microscope (SEM). 2. The method for testing a semiconductor device according to claim 1, wherein one or more locations of the conductor wiring and the semiconductor substrate are electrically connected through a through hole provided in or near a contact chain. 3. The method for testing a semiconductor device according to claim 1, wherein one or more locations of the conductor wiring and the semiconductor substrate are electrically connected at a divided region of the semiconductor substrate or a fractured surface of the semiconductor substrate.