JP4727943B2 - Inspection circuit, inspection method using the same, and semiconductor device including the inspection circuit - Google Patents

Description

  The present invention relates to an inspection circuit for detecting a short-circuit portion between wirings, an inspection method using the inspection circuit, and a semiconductor device including the inspection circuit.

  A damascene method is known as a wiring formation process of a semiconductor device. In the damascene method, the wiring is formed by embedding a metal material such as copper in the wiring groove and removing the metal material exposed outside the wiring groove by CMP (Chemical Mechanical Polishing). Thereafter, a cap film such as SiN or SiCN is formed on the wiring by CVD (Chemical Vapor Deposition). Such a cap film is provided for the purpose of preventing the leakage of inter-wiring caused by ion drift of copper constituting the wiring into the upper interlayer insulating film.

  However, since an interface state is formed on the wiring surface formed by CMP due to the influence of defects or the like, a leakage current conduction path is formed at the interface with the cap film. Further, when a strong electric field is generated between the wirings, copper is ionized, and the copper ions enter the interlayer insulating film from the location where the barrier metal and the cap film are broken. Copper ions that have entered the interlayer insulating film move from the anode side to the cathode side using the force received from the electric field as a driving force. Thereafter, the copper ions receive and deposit electrons near the cathode. The deposited copper piles up, the electric field strength increases, and a short circuit failure may occur. In order to inspect the cause and occurrence location of such a short circuit failure, an electrical characteristic analysis such as TDDB (time dependent dielectric breakdown) using an inspection circuit is performed.

  FIG. 8 is a diagram showing an example of the configuration of a conventional inspection circuit (TEG). As shown in FIG. 8A, the conventional inspection circuit has a configuration in which a pair of comb-shaped wiring patterns 2 and 4 are provided facing each other. The wiring pattern 2 and the wiring pattern 4 are formed in the interlayer insulating film 5. The wiring pattern 2 is connected to the inspection pad 20, and the wiring pattern 4 is connected to the inspection pad 22.

  The inspection is performed by observing the transition of leakage current when a voltage is applied between the inspection pad 20 and the inspection pad 22. A potential difference is applied between the test pad 20 and the test pad 22, and when a short circuit occurs, it is determined that there is a failure, and the voltage application is terminated. After that, the short part is identified and analyzed.

  Here, as shown in the figure, for example, a case where a short portion 30 occurs between the wiring pattern 2 and the wiring pattern 4 is assumed. In this state, when a voltage is applied between the test pad 20 and the test pad 22, as shown by a broken line (actual current path 40) in FIG. A current flows between patterns 4.

The current path can be observed as an image by using an OBIRCH (Optical Beam Induced Resistance Change) method in which a change in current when the laser beam is scanned is displayed as a change in luminance. However, since the diameter of the laser beam is about 1.3 μm and is usually larger than the wiring interval between the comb-teeth portions of the wiring pattern 2 and the wiring pattern 4, when the OBIRCH method is used, the current path is as shown in FIG. The oblique line (observed current path 42) is observed.
Japanese Patent Laid-Open No. 11-23668

  Therefore, the short portion 30 cannot be specified from the image using the OBIRCH method, and the range including the short portion 30 can be detected only by a large block. It is not easy to specify a short portion from such a block, and there is a problem that analysis takes a very long time. As a result, the manufacturing cost of the semiconductor device increases, and there is a problem that feedback to the process cannot be sufficiently performed.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a technique capable of efficiently narrowing down short portions between wirings and easily identifying short portions.

  According to the present invention, a test circuit used for detecting a short-circuited portion between wirings, each extending in one direction and each having a plurality of first wirings spaced from each other, and A plurality of second wirings extending in one direction and provided at intervals between the plurality of first wirings in the same layer as the plurality of first wirings; In a region overlapping the first wiring and the second wiring in a layer different from the second wiring, each extends in a direction intersecting with the plurality of first wirings and the plurality of second wirings, and spaced from each other. A plurality of third wirings provided at a distance, a plurality of first vias respectively connecting a plurality of second wirings and a plurality of third wirings, and electrically connected to the plurality of first wirings First test pad and a plurality of third wires Test circuit, characterized in that it comprises a second inspection pad which is electrically connected, is provided.

  The test circuit of the present invention may further include a first power source that applies a voltage between the first test pad and the second test pad.

  In the inspection circuit configured in this way, for example, when there is a short portion between any of the first wiring and the second wiring, between the first inspection pad and the second inspection pad. When a voltage is applied, a current flows between the first test pad and the second test pad via the shorted portion and the first via that connects the second wiring and the third wiring. Here, the second wiring and the third wiring are connected by a plurality of first vias, but the current flowing through the first via located closest to the short-circuited portion becomes the largest. For example, when a current flows from the first test pad to the first wiring, the current flows from the third wiring to the second test pad through the first via in the vicinity of the short-circuited portion. Since the third wiring extends in a direction intersecting with the first wiring, the direction of the current path changes after passing through the first via. When the current path is scanned with a laser beam using the OBIRCH method and acquired as a scanned image, there is a short portion in a region where the direction of the current path has changed, and the short portion can be efficiently narrowed down.

  In the inspection circuit of the present invention, the plurality of first wirings can be formed so as to extend substantially parallel to each other. In the inspection circuit of the present invention, the plurality of second wirings can be formed so as to extend substantially parallel to each other. Furthermore, in the inspection circuit of the present invention, the plurality of first wirings and the plurality of second wirings can be formed so as to extend substantially in parallel to each other.

  The plurality of first wirings can be formed at equal intervals. The plurality of second wirings can be formed at equal intervals. Further, the plurality of first wirings and the plurality of second wirings can be formed at equal intervals.

  In the inspection circuit of the present invention, the plurality of third wirings can be formed so as to extend substantially parallel to each other. Further, the third wiring can be formed at equal intervals.

  As described above, by forming the plurality of wirings substantially in parallel, the plurality of wirings can be efficiently arranged in a small space, and the inspection circuit can be downsized. Also, by forming a plurality of first wirings, a plurality of second wirings, and a plurality of third wirings so as to have regularity, analysis of physical phenomena such as occurrence of a short circuit due to the influence of the environment around the wiring It can be performed.

  In the inspection circuit of the present invention, the plurality of third wirings can be formed to extend in substantially parallel to each other and to extend in a direction substantially perpendicular to the plurality of first wirings. With such a configuration, a plurality of wirings can be efficiently arranged in a small space, and the inspection circuit can be downsized. Further, it is possible to easily detect the change point of the current path. Thereby, a short location can be detected efficiently.

  The inspection circuit of the present invention is arranged in a direction intersecting with the plurality of first wirings and the plurality of second wirings in the region overlapping the first wiring and the second wiring in the same layer as the plurality of third wirings. A plurality of fourth wirings that are extended and spaced apart from each other, and a plurality of second vias that connect the first wiring and the fourth wiring, respectively. Further can be included.

  With such a configuration, as described above, when the voltage is applied between the first test pad and the second test pad to narrow the short portion, the first wiring and the fourth wiring are reduced. A configuration in which the second wiring is connected to the second wiring via the second via can be a test target, and a wiring pattern closer to the actual product layout can be analyzed.

  The inspection circuit of the present invention further includes a third inspection pad electrically connected to the plurality of second wirings, and a fourth inspection pad electrically connected to the plurality of fourth wirings. be able to.

  The test circuit of the present invention may further include a second power source that applies a voltage between the third test pad and the fourth test pad.

  In the inspection circuit configured as described above, for example, when there is a short portion between any of the first wiring and the second wiring, between the third inspection pad and the fourth inspection pad. When a voltage is applied, a current flows between the third test pad and the fourth test pad via the shorted portion and the second via that connects the first wiring and the fourth wiring. Here again, the current flowing through the second via located closest to the shorted portion is the largest. For example, when a current flows from the third test pad to the second wiring, the current flows from the fourth wiring to the fourth test pad via the second via near the short-circuited portion. Since the fourth wiring extends in a direction intersecting with the second wiring, the direction of the current path changes after passing through the second via. When the current path is scanned with a laser beam using the OBIRCH method and acquired as a scanned image, there is a short portion in a region where the direction of the current path has changed, and the short portion can be efficiently narrowed down. As described above, even when a voltage is applied between the first test pad and the second test pad, the current path can be acquired as a scanned image, but the third test pad and the fourth test pad can be obtained. Since the current path is different from the case where a voltage is applied between the pad and the pad, different regions are narrowed down. Therefore, a scanned image when a voltage is applied between the first test pad and the second test pad, and a scanned image when a voltage is applied between the third test pad and the fourth test pad. By acquiring, there is a short portion in the overlapping portion of these regions, and the short portion can be narrowed down more efficiently.

  In the inspection circuit of the present invention, the plurality of fourth wirings can be formed so as to extend substantially parallel to each other. In the inspection circuit of the present invention, the plurality of third wirings and the plurality of fourth wirings can be formed so as to extend substantially parallel to each other. The plurality of fourth wirings can be formed at equal intervals.

  In the inspection circuit of the present invention, the plurality of first wirings can be formed to extend substantially parallel to each other, and the plurality of fourth wirings are in a direction substantially perpendicular to the plurality of first wirings. It can be formed to extend.

  According to the present invention, there is provided an inspection method for detecting a short-circuit portion between wirings using any of the inspection circuits described above. This method includes a step of applying a voltage between a first inspection pad and a second inspection pad, and a step of scanning a laser beam on the inspection circuit and acquiring a current path flowing through the inspection circuit as a scanned image. And including.

  According to the present invention, there is provided an inspection method for detecting a short-circuit portion between wirings using any of the inspection circuits described above. In this method, a voltage is applied between a first test pad and a second test pad, and a current path flowing through the test circuit by scanning a laser beam on the test circuit is used as a first scan image. A step of obtaining, a step of applying a voltage between the third inspection pad and the fourth inspection pad, and a second scanning image showing a current path flowing through the inspection circuit by scanning the inspection circuit with a laser beam. And obtaining the step.

  According to the present invention, there is provided a semiconductor device including any one of the inspection circuits described above. The semiconductor device can include a semiconductor chip of a product sample before producing an actual product. For example, an inspection circuit can be provided at a corner of the semiconductor chip. As a result, when a defect occurs in the actual wiring pattern, the cause can be analyzed using the inspection circuit.

  According to the present invention, it is possible to efficiently narrow down a short portion between wirings and easily identify a short portion.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

  In the following embodiments, the inspection circuit 100 can be introduced into a semiconductor chip of a product sample before an actual product is produced, for example. FIG. 7 is a diagram showing a semiconductor device 200 having a configuration in which the inspection circuit 100 is formed in the semiconductor chip 202. Here, the inspection circuit 100 is formed at a corner of the semiconductor chip 202. In this way, when a defect occurs in the actual wiring pattern of the semiconductor chip, the cause can be analyzed using the inspection circuit 100.

(First embodiment)
FIG. 1 is a diagram showing a configuration of an inspection circuit 100 in the present embodiment. The inspection circuit 100 has a configuration corresponding to the actual wiring pattern.

  FIG. 1A shows a top view of the inspection circuit 100. The inspection circuit 100 is electrically connected to the comb-shaped first wiring pattern 102, the comb-shaped second wiring pattern 104, the comb-shaped third wiring pattern 106, and the first wiring pattern 102. The first pad 120, the second pad 122 electrically connected to the second wiring pattern 104, and the third pad 124 electrically connected to the third wiring pattern 106. The first wiring pattern 102 and the second wiring pattern 104 are formed in the same layer. The first wiring pattern 102 and the second wiring pattern 104 are provided opposite to each other, and are nested so that the comb tooth portion of one wiring pattern is disposed between the comb tooth portions of the other wiring pattern. Is formed. In the present embodiment, in the first wiring pattern 102, the second wiring pattern 104, and the third wiring pattern 106, the wirings of the comb-tooth portions are formed substantially parallel to each other and at equal intervals. Is done. In addition, the wirings of the comb-tooth portions of the first wiring pattern 102 and the second wiring pattern 104 are formed substantially in parallel with each other and at equal intervals.

  The third wiring pattern 106 is formed in a different layer from the first wiring pattern 102 and the second wiring pattern 104. The comb tooth portions of the third wiring pattern 106 are formed so as to intersect with the comb tooth portions of the first wiring pattern 102 and the second wiring pattern 104. In the present embodiment, the comb-tooth portion of the third wiring pattern 106 is formed so as to intersect substantially perpendicularly with the comb-tooth portions of the first wiring pattern 102 and the second wiring pattern 104. The third wiring pattern 106 is electrically connected through vias 108 at a plurality of intersections with the second wiring pattern 104. Further, a power supply 128 and a switch 128a are provided between the first pad 120 and the third pad 124, and a voltage can be applied between the first pad 120 and the third pad 124. Yes.

  FIG.1 (b) is A-A 'sectional drawing of Fig.1 (a). As shown in FIG. 1B, the third wiring pattern 106 is formed above the first wiring pattern 102 and the second wiring pattern 104 with an interlayer insulating film (not shown) interposed therebetween. In another example, the third wiring pattern 106 may be formed below the first wiring pattern 102 and the second wiring pattern 104. In the present embodiment, the second wiring pattern 104 and the third wiring pattern 106 are electrically connected through a plurality of vias 108.

  FIG. 2 is a diagram schematically illustrating the inspection circuit 100 illustrated in FIG. Here, as shown in FIG. 2A, a case where a short portion 130 is formed between the first wiring pattern 102 and the second wiring pattern 104 will be described as an example. In such a case, when the switch 128 a is closed and a voltage is applied between the first pad 120 and the third pad 124, the current flows from the first pad 120 along the first wiring pattern 102. After flowing in the vertical direction in the drawing and passing through the short portion 130, it flows in the horizontal direction in the drawing in the direction of the third pad 124 along the third wiring pattern 106 through the via 108 closest to the short portion 130.

  Here, since the second wiring pattern 104 and the third wiring pattern 106 are electrically connected through the plurality of vias 108, the current is not only transmitted through the current path 140 but also through other paths. It is thought to flow. However, it is considered that the largest current flows through the via closest to the short portion 130. Therefore, the magnitude of the current flowing through the current path 140 shown in FIG.

  In such a case, when the OBIRCH method is used, the current path extends from the first pad 120 in the vertical direction in the drawing, and extends in the right direction in the drawing at a certain point, as indicated by the oblique lines in the drawing. Thus, it is observed as a substantially L-shaped region 142 extending to the third pad 124. As described above, since the largest current flows in the via closest to the short portion 130, the region 142 can be identified from the contrast of the image obtained by the OBIRCH method. In the present embodiment, the direction of the current path changes via the via 108 near the short portion 130. Therefore, the short portion 130 can be detected by detecting the change point of the current path. From this observation result, the short portion 130 becomes the intersection region 144 of the observation current path in the vertical direction and the observation current path in the horizontal direction. As a result, it is possible to efficiently narrow down the short locations 130 and to quickly identify the short locations. In this way, by specifying the short-circuited location, for example, when copper is used as the wiring material, it is possible to analyze and analyze physical phenomena such as copper entering and accumulating in the interlayer insulating film. It is possible to locate a portion that is a weak point of TDDB in the wiring pattern. Thereby, the reliability of the semiconductor device can be improved by improving the design of the part.

(Second embodiment)
FIG. 3 is a diagram illustrating a configuration of the inspection circuit 100 according to the present embodiment. In this embodiment, the inspection circuit 100 is electrically connected to the comb-shaped fourth wiring pattern 110 and the fourth wiring pattern 110 in addition to the inspection circuit 100 shown in FIG. 1 in the first embodiment. And a fourth pad 126 connected to the. The fourth wiring pattern 110 is formed in the same layer as the third wiring pattern 106. The third wiring pattern 106 and the fourth wiring pattern 110 are provided so as to face each other, and are nested so that the comb tooth portion of one wiring pattern is disposed between the comb tooth portions of the other wiring pattern. It is formed. The comb tooth portions of the fourth wiring pattern 110 are formed so as to intersect with the comb tooth portions of the first wiring pattern 102 and the second wiring pattern 104. In the present embodiment, the comb-tooth portion of the fourth wiring pattern 110 is formed so as to intersect substantially perpendicularly with the comb-tooth portions of the first wiring pattern 102 and the second wiring pattern 104. The fourth wiring pattern 110 is electrically connected through the vias 109 at a plurality of intersections with the first wiring pattern 102. A power source 129 and a switch 129a are provided between the second pad 122 and the fourth pad 126, and a voltage can be applied between the second pad 122 and the fourth pad 126. Yes.

  In the present embodiment, the wirings of the comb-tooth portions of the fourth wiring pattern 110 are formed substantially parallel to each other and at equal intervals. Further, the wirings of the comb-tooth portions of the third wiring pattern 106 and the fourth wiring pattern 110 are formed substantially parallel to each other and at equal intervals.

Next, with reference to FIGS. 4 to 6, an operation for detecting a short-circuit portion between the wirings will be described.
FIG. 4 is a diagram illustrating a state in which a short portion 130 is formed between the first wiring pattern 102 and the second wiring pattern 104. In such a case, as shown in FIG. 5, when the switch 128a is closed and a voltage is applied between the first pad 120 and the third pad 124, the current path 140 passes along the short circuit 130. A current flows between the first pad 120 and the third pad 124. In such a case, when the OBIRCH method is used, the current path is observed as a region 142 surrounded by a dashed line. Thereby, it can be seen that the short portion 130 is included in the intersection region 144 of the observation current path in the X direction (horizontal direction in the figure) and the Y direction (vertical direction in the figure).

  In addition, as shown in FIG. 6, when the switch 129 a is closed and a voltage is applied between the second pad 122 and the fourth pad 126, the second pad is moved along the current path 146 through the short portion 130. A current flows between 122 and the fourth pad 126. In such a case, when the OBIRCH method is used, the current path is observed as a region 148 surrounded by a dashed line. Thereby, it can be seen that the short portion 130 is included in the intersection region 150 of the observation current paths in the X direction and the Y direction.

  When the above method is used, it can be seen that the short portion 130 is included in the overlapping portion of the intersection area 144 shown in FIG. 5 and the intersection area 150 shown in FIG. Thereby, the narrow location 130 can be further narrowed down, and the short location 130 can be identified quickly.

  Further, according to the configuration of the inspection circuit 100 in the present embodiment, a voltage is applied to either the first pad 120 and the third pad 124 or between the second pad 122 and the fourth pad 126. TDDB can be analyzed between wirings in which vias are formed. As a result, the wiring pattern closer to the actual product layout can be analyzed.

  The embodiments and examples of the present invention have been described above with reference to the drawings. However, these are examples of the present invention, and various configurations other than the above can be adopted.

  For example, in the above embodiment, the inspection circuit 100 is introduced into the semiconductor chip. However, the inspection circuit may be formed on the scribe line of the semiconductor wafer.

It is a figure which shows the structure of the test | inspection circuit in embodiment of this invention. It is a figure which shows typically the test | inspection circuit shown in FIG. It is a figure which shows the structure of the test | inspection circuit in embodiment of this invention. It is a figure explaining the operation | movement for detecting the short part between wiring. It is a figure explaining the operation | movement for detecting the short part between wiring. It is a figure explaining the operation | movement for detecting the short part between wiring. It is a figure which shows the semiconductor device of the structure by which the test | inspection circuit was formed in the semiconductor chip. It is a figure which shows an example of a structure of the conventional test | inspection circuit (TEG).

Explanation of symbols

100 inspection circuit 102 first wiring pattern 104 second wiring pattern 106 third wiring pattern 108 via 109 via 110 fourth wiring pattern 120 first pad 122 second pad 124 third pad 126 fourth Pad 128 Power supply 128a Switch 129 Power supply 129a Switch 130 Short location 140 Current path 144 Intersection area 146 Current path 150 Intersection area

Claims (16)

An inspection circuit used for detecting a short-circuit between wirings,
A plurality of first wires each extending in one direction and spaced from each other;
A plurality of second wirings each extending in one direction, and in the same layer as the plurality of first wirings, each provided with a space between the plurality of first wirings;
Crossing the plurality of first wirings and the plurality of second wirings in a region overlapping the first wiring and the second wiring in a layer different from the first wiring and the second wiring, respectively. A plurality of third wirings extending in a direction to be spaced apart from each other;
A plurality of first vias respectively connecting the plurality of second wirings and the plurality of third wirings;
A first test pad electrically connected to the plurality of first wirings;
A second inspection pad electrically connected to the plurality of third wirings;
An inspection circuit comprising: The inspection circuit according to claim 1,
It said plurality of second wirings, the inspection circuit, characterized in that extending flat row to each other. In the inspection circuit according to claim 1 or 2,
It said plurality of third wirings, the inspection circuit, characterized in that extending flat row to each other. The inspection circuit according to any one of claims 1 to 3,
Wherein the plurality of first wiring test circuit, characterized in that extending flat row to each other. The inspection circuit according to any one of claims 1 to 3,
The first wiring and the second wiring test circuit, characterized in that extending flat row to each other. In the inspection circuit according to claim 4 or 5,
It said plurality of third wirings, the inspection circuit, characterized in that as well as extending flat row to each other, extending the plurality of first wirings and vertical directions. The inspection circuit according to any one of claims 1 to 6,
A test circuit further comprising a first power supply for applying a voltage between the first test pad and the second test pad. The inspection circuit according to any one of claims 1 to 7,
In a region overlapping the first wiring and the second wiring in the same layer as the plurality of third wirings, each extends in a direction crossing the plurality of first wirings and the plurality of second wirings. And a plurality of fourth wirings provided at intervals between the third wirings;
A plurality of second vias respectively connecting the first wiring and the fourth wiring;
An inspection circuit further comprising: The inspection circuit according to claim 8,
Wherein the plurality of fourth wirings, the inspection circuit, characterized in that extending flat row to each other. The inspection circuit according to claim 8 or 9,
Said plurality of third wirings and the plurality of fourth wirings, the inspection circuit, characterized in that extending flat row to each other. In the inspection circuit according to claim 9 or 10,
Testing the plurality of first wiring is configured to extend in a flat row to each other, the plurality of fourth wirings, characterized in that extending in the plurality of first wirings and vertical directions circuit. The inspection circuit according to any one of claims 8 to 11,
A third test pad electrically connected to the plurality of second wirings;
A fourth test pad electrically connected to the plurality of fourth wirings;
An inspection circuit further comprising: The inspection circuit according to claim 12, wherein
The inspection circuit further comprising a second power source for applying a voltage between the third inspection pad and the fourth inspection pad. An inspection method for detecting a short portion between wirings using the inspection circuit according to claim 1,
Applying a voltage between the first test pad and the second test pad;
Scanning a laser beam on the inspection circuit to obtain a current path flowing through the inspection circuit as a scanned image;
The inspection method characterized by including. An inspection method for detecting a short portion between wirings using the inspection circuit according to claim 12 or 13,
Applying a voltage between the first test pad and the second test pad;
Scanning the inspection circuit with a laser beam to obtain a current path flowing through the inspection circuit as a first scanned image;
Applying a voltage between the third test pad and the fourth test pad;
Scanning a laser beam on the inspection circuit to obtain a current path flowing through the inspection circuit as a second scanned image;
The inspection method characterized by including.   14. A semiconductor device comprising the inspection circuit according to claim 1.

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