JP2010192521A - Method of manufacturing semiconductor device, and teg element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To quickly specify presence as well as position of a defect of a wiring to be inspected in non-contacting manner by applying an electric potential by non-contacting manner to the wiring of TEG. <P>SOLUTION: The method of manufacturing a semiconductor device includes following procedures: a photovoltaic element 2 is formed on the upper surface of a semiconductor substrate 1; on the upper surface on an insulating layer 3 formed on the photovoltaic element 2, a wiring 4t, which is to be inspected, of which one end is connected to a positive electrode 2-1 of the photovoltaic element 2 while the other end is connected to a negative electrode 2-2 of the photovoltaic element 2 is formed; light 11 is made to enter through the lower surface of the semiconductor substrate 1 to excite the photovoltaic element 2 so that an electric potential difference is generated between both ends of the wiring 4t; and a surface electric potential distribution of the wiring 4t is measured using a non-contacting scan type surface electric potential microscope. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a semiconductor device that monitors a wiring formation process of a semiconductor device by detecting a defect of a wiring in a TEG (Test Element Group), for example, a disconnection or a short circuit, using a non-contact scanning surface potential microscope. The present invention also relates to a TEG element in which the short-circuit position can be easily specified.

  In the development or mass production process of in-element wiring of a semiconductor device, the relationship between manufacturing conditions and wiring defects, for example, wiring manufacturing conditions such as wiring shape or patterning conditions, occurrence location of disconnection or short circuit, occurrence frequency and occurrence of these defects The manufacturing yield of the semiconductor device is improved by investigating the statistical relationship with the form and feeding back the result to the manufacturing conditions at an early stage.

  In such investigation of wiring defects, a simple wiring pattern, for example, a so-called line-and-space in which a plurality of wirings are arranged in parallel at intervals to clarify the relationship between manufacturing conditions and wiring defects. A TEG having the following wiring pattern is often used. A defect is detected using such a TEG, the position of the defect is specified, and if necessary, the defect is directly observed. Thereby, the cause of the defect can be statistically grasped and the cause can be specified by direct observation.

  Wiring defects in the TEG can be detected by the presence or absence of electrical continuity in the wiring. For example, a disconnection is detected by the presence / absence of conduction between both ends of a line-and-space wiring, and a short circuit between adjacent wirings is detected by the presence / absence of conduction between adjacent wirings to be insulated. Furthermore, the disconnection location can be specified by detecting the position where conduction is interrupted.

  Conventionally, such continuity inspection of wiring has been performed by contacting a contact needle against the surface of the wiring and detecting continuity between the contact needles. However, it is time consuming to specify the presence or absence of a defect and the location where the defect occurs in an inspection using a contact needle, and it is difficult to quickly feed back to manufacturing conditions. Further, the contact of the contact needle may cause scratches or dust on the wiring surface, which is not suitable for in-line inspection.

  In order to solve this difficulty, an inspection method using VC (voltage contrast) of an electron microscope has been developed. In this method, the surface of the TEG is irradiated with an electron beam to charge the wiring, and the voltage distribution of the charged wiring is observed as the contrast of the electron microscope image. Accordingly, voltage application to the wiring and observation of the voltage distribution are performed in a non-contact manner, so that the inspection time is short and the wiring is not damaged or dusty, so that in-line inspection is possible. It is also easy to directly observe the defect location and the defect shape of the wiring.

  However, in order to clarify the contrast of the wiring image by the method using VC, it is necessary to increase the voltage difference of the wiring by irradiating an electron beam with a high current density. However, when thin wirings having a thickness of 45 nm or less are used and porous low dielectric constant insulating materials having poor mechanical strength are used as insulating layers, these thin wirings and low dielectric constant insulating layers become high-density current electrons. There is a risk of destruction by beam irradiation. For this reason, it is difficult to observe a clear wiring image in a fine wiring or a wiring formed on a low dielectric constant insulating layer that will be used in the future, and it is difficult to detect defects.

  A Kelvin force microscope (KFM) is known as a means for observing a potential difference between wirings in a non-contact manner. The Kelvin force microscope is one of scanning probe microscopes, and can observe the voltage distribution on the TEG surface in a non-contact manner.

  However, in order to observe the voltage distribution of the wiring using a Kelvin force microscope, a voltage must be applied to the wiring. Conventionally, the voltage application to the wiring of the TEG has adopted a method of contacting a contact needle with a power supply voltage applied to the wiring, or a method of supplying charges to the wiring on the TEG surface by corona discharge. However, a complete non-contact inspection cannot be performed using a contact needle, and charge supply by corona discharge is unstable, and a stable voltage cannot be applied.

JP 2001-318127 A JP 2007-303852 A JP 2000-068345 A

  As described above, in the conventional method for manufacturing a semiconductor device in which a contact needle is brought into contact with the surface of the wiring in the TEG to inspect the disconnection and short circuit of the wiring, the inspection time is long and it is difficult to provide quick feedback to the manufacturing conditions. There was a problem.

  In the conventional inspection method using an electron microscope, charges are supplied to the wiring with an electron beam, so that the inspection can be quickly performed without contact. However, in order to obtain a clear contrast wiring image, it is necessary to irradiate an electron beam with a high current density, and there is a problem that a thin wiring or an insulating layer having a low mechanical strength is destroyed.

  In addition, in the conventional method for manufacturing a semiconductor device in which a disconnection and a short circuit of a wiring are inspected using a Kelvin force microscope, a voltage is applied by bringing a contact needle into contact with the wiring, so that a complete non-contact inspection is not performed. The time will be longer. Further, in the method of supplying charges to the wiring by corona discharge, a stable voltage cannot be applied, and it is difficult to perform an inspection with excellent reproducibility.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device manufacturing method and a TEG element that can detect a defect in a TEG inspection wiring in a non-contact manner using a scanning surface potential microscope.

  In order to solve the above-described problems, a first configuration of the present invention includes a step of forming a photovoltaic element on an upper surface of a semiconductor substrate and an insulating layer that covers the photovoltaic element on the semiconductor substrate. Forming a plurality of wirings to be inspected having one end connected to the positive electrode of the photovoltaic element and the other end connected to the negative electrode of the photovoltaic element on the upper surface of the insulating layer; Using a scanning surface potential microscope that measures the surface potential in a non-contact manner, in which light is incident from the lower surface of the semiconductor substrate to excite the photovoltaic element to generate a potential difference at both ends of the wiring to be inspected The semiconductor device manufacturing method includes a step of measuring a surface potential distribution of the wiring to be inspected and a step of detecting disconnection of the wiring to be inspected based on the surface potential distribution.

  According to the present invention, the voltage is supplied from the photovoltaic element formed on the semiconductor substrate to both ends of the wiring to be inspected of the TEG. Therefore, it is necessary to supply the voltage from the outside to the wiring in order to apply the voltage to the wiring. There is no. For this reason, since the defect inspection of the wiring to be inspected by a complete non-contact can be performed using a non-contact type scanning surface potential microscope, the inspection can be performed quickly and the inspection result can be fed back to the manufacturing conditions quickly.

The wiring pattern top view of 1st Embodiment of this invention Cross-sectional view of a wiring pattern according to the first embodiment of the present invention Cross-sectional view of the wiring manufacturing process of the first embodiment of the present invention Wiring pattern plan view for explaining the inspection process in the first embodiment of the present invention Wiring potential diagram in the first embodiment of the present invention Surface potential distribution diagram for explaining the defect detection method in the first embodiment of the present invention The wiring pattern top view of 2nd Embodiment of this invention Wiring pattern sectional view of a second embodiment of the present invention The wiring pattern top view of 3rd Embodiment of this invention Cross-sectional view of a wiring pattern according to a third embodiment of the present invention The wiring pattern top view of 4th Embodiment of this invention Wiring pattern sectional view of the fourth embodiment of the present invention Wiring pattern plan view of a fifth embodiment of the present invention Wiring pattern sectional view of a fifth embodiment of the present invention Semiconductor wafer plan view of the present invention Perspective view of Kelvin force microscope The principal part sectional drawing of the Kelvin force microscope of this invention.

  1st Embodiment of this invention is related with the manufacturing method of the semiconductor device which has the defect inspection process which detects the disconnection and short circuit of the to-be-inspected wiring formed in TEG. In the first embodiment, a TEG including a semiconductor device made of an integrated circuit and a wiring to be inspected is mixedly formed on the upper surface of a semiconductor substrate made of a semiconductor wafer, for example, a silicon wafer.

  FIG. 1 is a plan view of a wiring pattern according to the first embodiment of the present invention, and shows a wiring pattern of a TEG. 2A and 2B are cross-sectional views of the wiring pattern according to the first embodiment of the present invention. FIG. 2A shows the AA 'cross section of FIG. 1, and FIG. 2B shows the BB' cross section of FIG.

  First, a TEG wiring pattern will be described.

  Referring to FIG. 1, a TEG wiring 4 according to the first embodiment includes a plurality of linearly inspected wirings 4t arranged in parallel to each other, parallel to the inspected wiring 4t and to the inspected wiring 4t. And a plurality of linear floating wirings 4f arranged adjacent to each other. Note that the wiring 4t to be inspected and the floating wiring 4f are formed in a curved shape parallel to each other (curved shape with a constant interval) or a curved shape parallel to each other (a bent curve shape with a constant interval between the straight lines). ).

  The TEG wiring 4 further includes two linear wirings extending in parallel to each other in a direction (vertical direction on the paper surface in FIG. 1) perpendicular to the extending direction of the wiring 4t to be inspected (the horizontal direction on the paper surface in FIG. 1). An n-type connection portion 6n and a p-type connection portion 6p are included. The n-type connection portion 6n and the connection portion 6p are respectively disposed at both ends of the wiring 4t to be inspected. One end of the wiring 4t to be inspected is connected to the n-type connection 6n, and the other end of the wiring 4t to be inspected is connected to the p-type connection 6p. Accordingly, the inspected wiring 4t is arranged so as to connect the two n-type and p-type connection portions 6n and 6p. The n-type connection portion 6n and the p-type connection portion 6p can be formed integrally with the wiring to be inspected 4t.

  On the other hand, the floating wiring 4f is arranged insulated from other wiring. The floating wiring 4t and the wiring 4t to be inspected are formed as, for example, a line-and-space pattern having the same wiring width and the same wiring interval as the wiring width.

  Hereinafter, the structure of the TEG of the first embodiment will be described.

  Referring to FIG. 2, a photovoltaic device comprising a pn junction type photovoltaic cell having a p-type semiconductor substrate 1 as a p-type region 2p on an upper surface of a semiconductor substrate 1 and an n-type region 2n formed on the upper surface of the semiconductor substrate 1. A power element 2 is formed. On the surfaces of the n-type region 2n and the p-type region 2p (semiconductor substrate 1) of the photovoltaic element 2, a positive electrode 2-1 and a negative electrode 2-2 made of a silicide layer are formed, respectively.

  An insulating film 3 is formed on the upper surface of the semiconductor substrate 1 so as to cover the photovoltaic element 2, and a wiring 4, for example, a damascene copper wiring 4 (inspected wiring 4t, floating wiring 4f, and n) is formed on the upper surface of the insulating film 3. The mold and p-type junctions 6n, 6p) are embedded. Further, the lower surface of the n-type and p-type junctions 6n, 6p penetrates the insulating layer 3 and connects the n-type junction 6n and the positive electrode 2-1, the peer 5 and the p-type junction 6p and the negative electrode 2 -2 is connected to -2. Accordingly, both ends of the wiring 4t to be inspected are connected to the positive electrode 2-1 and the negative electrode 2-2 of the photovoltaic element 2 through the n-type connection portion 6n, the p-type connection portion 6p, and the via 5, respectively. .

  Next, the manufacturing process of the semiconductor device according to the first embodiment of the present invention will be described.

  FIG. 3 is a cross-sectional view of a wiring manufacturing process according to the first embodiment of the present invention, showing a cross-sectional structure of the TEG in the middle of manufacture (cross section AA ′ in FIG. 1).

  With reference to FIG. 3A, in the method of manufacturing a semiconductor device according to the first embodiment, first, the photovoltaic element 2 is formed on the upper surface of the semiconductor substrate 1 simultaneously with the transistor forming step of the semiconductor device. Of course, if necessary, the photovoltaic element 2 may be formed in a step different from the step of forming the transistor. In the photovoltaic device 2, after forming an n-type region 2n by ion implantation on the upper surface of the p-type semiconductor substrate 1, positive and negative electrodes 2 made of silicide layers are formed on the upper surface of the n-type region 2n and the p-type semiconductor substrate 1 by a salicide process. Manufactured by forming -1,2-2. The semiconductor substrate 1 transmits light having a wavelength that excites the photovoltaic element 2 (light 11 in FIG. 2), and has a thickness sufficient to generate a photovoltaic force necessary for the inspection of the wiring 4t to be described later. For example, a silicon substrate or a compound semiconductor such as GaAs can be used.

  Next, referring to FIG. 3B, a low dielectric insulating film having a thickness of, for example, 100 nm is formed on the semiconductor substrate 1 to serve as the lower insulating film 3 a constituting the lower layer of the insulating layer 3. Then, the lower insulating layer 3a is etched to form a via hole that penetrates the lower insulating layer 3a and exposes the upper surface of the positive electrode 2-1 and a via hole that exposes the upper surface of the negative electrode 2-2. These via holes are filled with tungsten plugs to form vias 5.

  Next, referring to FIG. 3C, a low dielectric insulating film having a thickness of, for example, 100 nm is formed to cover the upper surface of the via 5 and the lower insulating layer 3a, which becomes the upper insulating film 3b constituting the upper layer of the insulating layer 3. To do. The lower insulating layer 3a and the upper insulating layer 3b constitute an insulating layer 3 made of a low dielectric film.

  Next, a groove is formed on the upper surface of the upper insulating layer 3b to define the wiring 4 pattern including the wiring 4t to be inspected, the floating wiring 4f, and the n-type and p-type connection portions 6n and 6p. At this time, the upper end surface of the via 5 is exposed at the bottom of the groove defining the n-type and p-type connection portions 6n and 6p. Next, the trench is filled with a wiring metal such as copper to form a damascene copper wiring 4 including n-type and p-type connection portions 6n and 6p.

  The to-be-inspected wiring 4t and the floating wiring 4f in the TEG are formed, for example, as a line and space having a width of 45 nm and an interval of 45 nm. Usually, in addition to this, it is formed including a plurality of TEGs having a wiring pattern composed of line-and-space having a width and a space before and after that.

  The TEG of the first embodiment was manufactured through the above-described steps. It should be noted that each of the TEG manufacturing processes, for example, the formation process of the lower insulating layer 3b, the upper insulating layer 3a, the via 5 and the wiring 4 is formed simultaneously with the manufacturing process of the semiconductor device. It is preferable from the viewpoint of evaluation.

  Next, a defect inspection process for the inspected wiring 4t is performed.

  FIG. 16 is a perspective view of a Kelvin force microscope, showing the main configuration of the Kelvin force microscope used as a scanning surface potential microscope. FIG. 17 is a cross-sectional view of the main part of the Kelvin force microscope of the present invention, showing the structure of the probe 37 and the XY stage 33 of the scanning surface potential microscope used in the present invention.

  16 and 17, the Kelvin force microscope (KFM) includes an XY stage 33 on which the semiconductor substrate 1 is placed, an arm 32, a control unit 34 for driving the XY stage, and a measurement unit 35. .

  The arm 32 has a probe driving unit 31 that holds the probe 37 via a cantilever at the lower end thereof, and supports the probe 37 on the semiconductor substrate 1. The probe 37 is scanned in a predetermined direction in the XY plane by a control voltage applied from the measuring unit 35 or the control unit 34 to the probe driving unit 31.

  The XY stage 33 is provided with a transparent transparent portion 33 a at least in the center, and transmits the light 11 from the light source 36 provided immediately below the center of the XY stage 33 to the upper surface of the XY stage 33. Accordingly, the light 11 from the light source 36 enters the back surface (lower surface) of the semiconductor substrate 1 placed on the XY stage 33 from below.

  In addition, a through hole 33b that vertically penetrates the XY stage 33 is provided at the peripheral portion of the XY stage 33, and a contact needle 38 that is loosely inserted into the through hole 33b is provided to be movable up and down. The upper end of the contact needle 38 is in contact with the back surface of the semiconductor substrate 1, and the lower end is connected to a lead wire 35 b to which a predetermined potential is supplied from the measuring unit 35. Accordingly, the semiconductor substrate 1 is held at a predetermined potential supplied from the measuring unit 35 via the contact needle 38.

  The measurement unit 35 applies AC voltage to the probe 37 via the lead wire 35a to cause the probe 37 to vibrate up and down, and the probe 37 and the surface of the semiconductor substrate 1 to suppress the vertical vibration of the probe 37. Control the potential difference between. Then, based on the potential difference between the probe 37 and the surface of the semiconductor substrate 1 at this time, the surface potential of the semiconductor substrate 1 is measured.

  In the defect inspection process of the first embodiment, first, the semiconductor substrate 1 on which the TEG wiring 4 pattern is formed is placed on the XY stage. Then, the control device 34 drives the XY stage 33 via the lead wire 34b and positions the semiconductor substrate 1 so that the TEG to be inspected is directly below the probe 37. Further, in order to bring the probe 37 close to the surface of the semiconductor substrate 1 to a predetermined distance, the arm 32 is lowered through the lead wire 34a.

  Next, referring again to FIG. 2 and FIG. 16, the light 11 from the light source 36 is incident from the lower surface of the semiconductor substrate 1 to excite the photovoltaic element 2 formed on the semiconductor substrate 1, and the positive and negative electrodes 2- A potential difference is generated between 1 and 2-2. The potentials of the positive and negative electrodes 2-1 and 2-2 are applied to the n-pole connection 6n and the p-pole connection 6p of the wiring 4 through the vias 5, respectively. As a result, a voltage (potential difference) equal to the potential difference between the positive and negative electrodes 2-1 and 2-2 is generated between the n-pole connection 6n and the p-pole connection 6p. For this reason, since a voltage equal to the potential difference between the positive and negative electrodes 2-1 and 2-2 is applied to both ends of the wiring 4t to be inspected, a current flows through the wiring 4t to be inspected and extends along the extending direction of the wiring 4t to be inspected. Thus, a voltage (potential) gradient is generated. As a result, a potential distribution is generated on the surface of the semiconductor substrate 1 on which the inspected wiring 4t is formed.

  Next, the XY table is driven or the probe 37 is driven using the probe drive unit 31 so that the probe 37 moves on the surface of the semiconductor substrate 1 in a predetermined scanning direction. Thereby, the surface potential distribution in the scanning direction of the semiconductor substrate 1 is measured.

  Next, the defect detection process of the wiring 4 in the first embodiment will be described in detail.

  FIG. 4 is a wiring pattern plan view for explaining the inspection process in the first embodiment of the present invention, and shows the wiring 4 including the wiring 4t to be inspected having the short-circuit portion 7s and the disconnection portion 7c as the defect 7. FIG. . The wiring 4 pattern shown in FIG. 4 is the same as the wiring 4 pattern shown in FIG.

  Referring to FIG. 4, a to-be-inspected wiring 4t extending along a straight line CC ′ has a broken portion 7c at the position of the x coordinate Xc, and is broken at that position. In this specification, the x-axis is taken in the extending direction of the wiring 4t to be inspected, and the y-axis is taken in the direction perpendicular to the x-axis included in the upper surface of the semiconductor substrate 1. In addition, the inspected wiring 4t adjacent to the floating wiring 4f extending along the straight line DD ′ (adjacent to the lower side of the drawing in FIG. 4) has a short-circuit portion 7s at the position of the x coordinate Xs. It is short-circuited to the adjacent floating wiring 4f at that position.

  In the defect detection step, the surface of the semiconductor substrate 1 is scanned with the probe 37 of the Kelvin force microscope 30 along the scanning line 12 orthogonal to the extending direction of the wiring 4t to be inspected (parallel to the y axis). The surface potential distribution of the semiconductor substrate 1 along the line was measured. The scanning line 12 is, for example, a straight line passing through the x coordinate X0.

  FIG. 5 is a wiring potential distribution diagram according to the first embodiment of the present invention, and shows a voltage distribution along the extending direction of the wiring to be inspected 4t and the floating wiring 4f. 5A shows the voltage distribution along the straight lines AA ′ and BB ′ in FIG. 4, FIG. 5B shows the voltage distribution along the straight line CC ′ in FIG. 4, and FIG. (C) represents the voltage distribution along the straight line DD ′ in FIG. In order to facilitate comparison, the voltage distribution shown in FIG. 5A is indicated by broken lines A and B in FIGS. 5B and 5C.

Referring to FIG. 5A, as indicated by a straight line A, the potential of the wiring 4t to be inspected is the potential Vn of the n-pole connecting portion 6n at the position of the x-coordinate Xn connected to the n-pole connecting portion 6n. The potential Vn of the positive electrode 2-1 of the photovoltaic element 2 is held. On the other hand, at the position of the x-coordinate Xp connected to the p-pole connection portion 6p, the potential Vp of the p-pole connection portion 6p, that is, the potential Vp of the negative electrode 2-2 of the photovoltaic element 2 is held. Accordingly, in a normal inspected wiring 4t in which no defect 7 exists, for example, inspected wiring 4t along the straight line AA ′, the surface potential is from the potential Vn along the extending direction of the inspected wiring (straight line AA ′). A potential distribution is formed that steps down at a constant voltage gradient to the potential Vp. As a result, at the position of the x coordinate X0 where the wiring to be inspected 34t and the scanning line 12 intersect, the potential Vo of the wiring to be inspected 4t takes an intermediate value between the potential Vn and the potential Vp,
Vo = (Vn−Vp) × (X0−Xp) / (Xn−Xp) + Vp (1)
Given in. For example, when the scanning line 12 passes through the center of the wiring 4t to be inspected, Vo = (Vn + Vp) / 2.

  On the other hand, the normal floating wiring 4f without disconnection and short circuit to the adjacent wiring 4t to be inspected is held at a floating potential Vf determined by various conditions at that time, as indicated by a straight line B. Therefore, the potential Vf is always observed over the entire length of the floating wiring 4t.

  FIG. 6 is a surface potential distribution diagram for explaining the defect detection method according to the first embodiment of the present invention, and shows the relationship between the surface potential distribution of the semiconductor substrate 1 along the scanning line 12 and the defects. 6A shows a part of the wiring 4 pattern shown in FIG. 4, and FIG. 6B shows a normal inspected wiring 4t (inspected wiring 4t having no defects 7 such as the shorted portion 7s and the disconnected portion 7c. ), And FIG. 6C shows the surface potential distribution observed in the to-be-inspected wiring 4t having the short-circuit portion 7s and the disconnection portion 7c shown in FIG. 6A. . 6B and 6C also show the surface potential distribution observed along the scanning line 12 using a Kelvin force microscope.

  Referring to FIG. 6B, the surface potential distribution observed in the defect-free wiring 4 pattern has the potential Vo observed when the maximum potential is directly above the to-be-inspected wiring 4t, and the minimum potential is floating. It was a sine wave shape having the potential Vf observed just above the wiring 4f. In this surface potential distribution, referring to FIG. 5A, the potentials of the wiring 4t to be inspected and the floating wiring 4f at the position (x coordinate Xo) intersecting the scanning line 12 are the potential Vo and the potential Vf, respectively. It comes from that. When the surface potential distribution is subjected to spectrum analysis by regarding the scanning distance (scanning distance in the extending direction of the scanning line 12) as a time axis, a period corresponding to the period (pitch) of the wiring 4t to be inspected and the floating wiring 4f. And a spectrum with multiple periods thereof was observed.

  As described above, the potential Vo of the wiring 4t to be inspected and the potential Vf of the floating wiring 4t depend on the position intersecting the scanning line 12 (x coordinate Xo) and various conditions contributing to the floating potential Vf, respectively. To do. Therefore, the potential Vo of the wiring 4t to be inspected and the potential Vf of the floating wiring 4t may be reversed depending on the position of the scanning line 12 and the condition for applying the floating potential. If necessary, the x-coordinate Xo of the scanning line 12 can be appropriately adjusted so that the surface potential distribution has an amplitude suitable for observation, for example, an amplitude suitable for spectrum analysis.

  Next, with reference to FIG. 6C and FIG. 5, the surface potential distribution observed in the wiring 4 pattern having the defect 7 including the short-circuit portion 7s and the disconnection portion 7c will be described.

  First, in the to-be-inspected wiring 4t having the disconnection portion 7c, referring to the folding line C in FIG. 5B, the region between the disconnection portion 7c and the n-pole connection portion 6n (from the x coordinate Xc to the x coordinate Xn). The potential is held at the potential Vn of the n-pole connection portion 6n, while the potential between the disconnection portion 7c and the p-pole connection portion 6p (from the x coordinate Xc to the x coordinate Xp) is the potential Vp of the p-pole connection portion 6p. Retained. Therefore, when the broken part 7c is closer to the n-pole connection part 6n than the scanning line 12 position (x coordinate Xn), the observed potential of the wiring 4t to be inspected is equal to the potential Vp of the p-pole connection part 6p and vice versa. In addition, when the broken part 7c is closer to the p-pole connecting part 6p than the scanning line 12 position (x coordinate Xn), the observed potential of the wiring 4t to be inspected is equal to the potential Vn of the n-pole connecting part 6n. Note that these potentials Vn and Vp have different potentials from the potential Vo observed in the normal wiring 4t with reference to the straight lines A and C. For this reason, the presence or absence of the disconnection part 7c can be detected easily.

  Referring to FIG. 6C, the observed surface potential distribution decreases to the potential Vp at the position of the inspected wiring 4t where the disconnection portion 7c exists. As described above, when the potential of the wiring 4t to be inspected is lowered to the potential Vp of the p-pole connecting portion 6p, the wiring 4t to be inspected has the disconnection portion 7c, and the disconnection portion 7c has n poles from the scanning line 12. It determines with existing in the connection part 6n side. On the contrary, when the potential of the wiring 4t to be inspected rises to the potential Vn of the n-pole connecting portion 6n, the wiring 4t to be inspected has the disconnection portion 7c, and the disconnection portion 7c is connected to the p-pole connection portion from the scanning line 12. It is determined that it exists on the 6p side. In this way, the presence or absence of the disconnection portion 7c and the approximate position (one side across the scanning line 12) are detected from the surface potential distribution.

Next, in the to-be-inspected wiring 4t having the short-circuit portion 7a, with reference to the straight line D in FIG. 5C, the potential of the floating wiring 4f that is short-circuited to the adjacent to-be-inspected wiring 4t through the short-circuit portion 7s is This is equal to the potential Vs of the wiring 4t to be inspected at the position of the short-circuit portion 7s (x coordinate Xs). The potential Vs is obtained by keeping the potential gradient of the floating wiring 4f constant.
Vs = (Vn−Vp) × (Xs−Xp) / (Xn−Xp) + Vp (2)
It becomes. From this, the x-coordinate Xs of the short-circuit portion 7s is
Xs = (Vs−Vp) × (Xn−Xp) / (Vn−Vp) + Xp (3)
Can be obtained as Here, since the electromotive force (Vn−Vp) of the photovoltaic element 2 is known and Xn and Xp are also known, the x coordinate Xs of the short-circuit portion 7s can be calculated by measuring the potential Vs. .

  Referring to FIG. 6C, in the observed surface potential distribution, the surface potential at the position of the floating wiring 4f where the short-circuit portion 7s is present rises to the above-described potential Vs. In this way, when a potential Vs different from the floating potential Vf of the normal floating wiring 4f is observed at the position of the floating wiring 4f, the wiring to be inspected adjacent to the floating wiring 4f in which the potential Vs is observed. It determines with 4t having the short circuit part 7s. As described above, the presence or absence of the short-circuit portion 7s can be determined by observing the potential of the floating wiring 4t. Furthermore, the observed potential Vs can be substituted into Equation 2 to calculate the x coordinate Xs of the short-circuit portion 7s.

  In the detection of the short-circuit portion 7s described above, even if the floating wiring 4f is short-circuited, if the potential Vs is equal to the floating potential Vf of the normal floating wiring 4f, it is the same as the surface potential distribution of the normal wiring 4 Therefore, the short circuit part 7s cannot be detected. Such a situation is caused by observing the surface potential distribution twice along two scanning lines 12 having different x-coordinates Xo, or by changing the floating potential Vf by discharging or supplying a charge. It can be avoided by observing.

  In the defect detection step of the disconnection portion 7c and the short-circuit portion 7s described above, it is preferable to first perform frequency analysis of the observed surface potential distribution, for example, spectrum analysis. The disconnection portion 7 c and the short-circuit portion 7 s add defect-induced potentials Vs and Vc to the surface potential distribution of the normal wiring 4 at positions shifted by the basic period or ½ period. Since the change in the surface potential distribution is reflected sharply in the spectrum distribution, the presence or absence of defects can be determined extremely quickly and easily.

  Subsequent to the defect detection step, the short-circuit portion 7s and the disconnection portion 7c were directly observed. In this direct observation, first, the x-coordinates Xs and Xc of the short-circuited part 7s and the disconnected part 7c were specified, and if necessary, the insulating film of the part was granted and observed using a scanning electron microscope. As described above, the x coordinate Xs of the short-circuit portion 7s can be easily calculated from the voltage Vs. On the other hand, the x-coordinate Xc of the disconnection portion 7c is obtained by scanning the probe 37 in the extending direction (x-axis direction) along the wiring 4t to be inspected where the presence of the disconnection portion 7c is selected. Can be specified by detecting a position where the change is sudden and setting this position as the x-coordinate Xc of the disconnected portion 7c.

  According to the semiconductor manufacturing method of the first embodiment of the present invention described above, the potential to the wiring 4t to be inspected is supplied from the photovoltaic element 2 formed on the semiconductor substrate 1, so that it can be promptly performed by complete non-contact. Defect detection is performed. Further, the x-coordinate Xs of the short-circuit portion 7s can be easily and quickly specified only by observing the surface potential distribution. Therefore, since there is no destruction of the wiring 4 and generation of dust by the contact needle, in-line observation is possible, and since the inspection is quick, the feedback to the manufacturing process can be performed easily and quickly.

  2nd Embodiment of this invention is related with the detection method of the disconnection part of to-be-inspected wiring which comprises a via chain.

  FIG. 7 is a plan view of a wiring pattern according to the second embodiment of the present invention, and shows the shape of the wiring 4 in the TEG. FIG. 8 is a cross-sectional view of a wiring pattern according to the second embodiment of the present invention, and represents a cross section of a straight line AA 'in FIG.

  7 and 8, the wiring 4 according to the second embodiment extends between the n-pole connection 6n and the p-pole connection 6p in parallel to each other in the x-axis direction (the left-right direction in the drawing). The existing wiring to be inspected 4t is arranged.

  Each wiring 4t to be inspected includes two lower layer inspection wirings 4st-1 and 4st-2 embedded in the insulating layer 3, and three upper layer inspections having a damascene structure formed on the surface of the leading edge layer 3. Consists of wirings 4t-1, 4t-2, 4t-3, and vias 8 that connect lower layer inspected wires 4st-1, 4st-2 and upper layer inspected wires 4t-1, 4t-2, 4t-3. Is done. Note that the number of divisions of these wirings can be set to an arbitrary number as necessary.

  These upper layer inspected wirings 4t-1, 4t-2, 4t-3 and lower layer inspected wirings 4st-1, 4st-2 are arranged on the same straight line and extend in the extending direction (extending direction of the same straight line). They are separated from each other. Then, the lower-layer inspected wirings 4st-1, 4st-2 are arranged so as to be located in the gaps (gap when viewed in plan) where the upper-layer inspected wirings 4t-1, 4t-2, 4t-3 are separated. . At this time, the upper layer inspected wirings 4t-1, 4t-2, 4t-3 and the lower layer inspected wirings 4st-1, 4st-2 are arranged so as to overlap each other. The via 8 is formed so as to connect the overlapping end portions. The thus formed wiring 4t to be inspected includes the upper layer inspection wiring 4t-1, the via 8, the lower layer inspection wiring 4st-1, the via 8, the upper layer inspection wiring 4t-2, the via 8, and the lower layer inspection wiring 4st. -2, via 8, and upper layer to-be-inspected wiring 4t-3 are configured as a straight wiring having a via chain structure connected in series.

  The upper-layer inspected wirings 4t-1 and 4t-3 located at both ends of the inspected wiring 4t are formed integrally with the n-pole connecting part 6n and the p-pole connecting part 6p, respectively. Connected to the p-pole connection 6p.

  The TEG of the second embodiment was formed by the following process.

  First, the photovoltaic element 2 is formed on the upper surface of the semiconductor substrate 1 by the same process as in the first embodiment. Next, the lower insulating film 3a is formed, and lower portions of the vias 5 that penetrate the lower insulating film 3a and connect to the positive electrode 2-1 and the negative electrode 2-2 are formed. Next, da lower layer inspection wirings 4st-1 and 4st-2 are formed on the upper surface of the lower insulating film 3a. At the same time, a via connection wiring 5 s connected to the upper end of the lower portion of the via 8 is formed.

  Next, an upper insulating layer 3b is formed to embed the lower layer to be inspected wirings 4st-1, 4st-2 and the via connection wiring 5s. Next, vias 8 that penetrate through the upper insulating layer 3b and are connected to both ends of the lower-layer inspected wirings 4st-1 and 4st-2 are formed. At the same time, an upper portion of the via 5 that penetrates the upper insulating layer 3b and is connected to the via connection wiring 5s is formed. As a result, the via 5 including the lower via portion, the via connection wiring 5s, and the upper via portion is formed. Then, damascene Cu upper-layer inspected wirings 4t-1, 4t-2, 4t-3, and n-pole and p-pole connection portions 6n, 6p are formed on the upper surface of the upper insulating layer 3a. Through this process, the TEG of the second embodiment is formed.

  In the second embodiment, a defect in the inspected wiring 4t is detected by the same process as the defect detection process in the first embodiment using a Kelvin force microscope. However, since the floating wiring 4f is not provided, the short circuit portion 7s is not detected, and only the disconnection portion 7c is detected. When determining wiring formation conditions in a semiconductor manufacturing process, it may be desirable to stand out by separating particularly noticeable defects from various other defects. According to the second embodiment, only the disconnected portion 7c can be detected regardless of the presence or absence of the short-circuit portion 7s.

  Furthermore, in the second embodiment, the wiring 4t to be inspected is connected in series by a number of vias 8. Therefore, it is effective in that the poor connection of the via can be effectively investigated especially when the poor connection of the via is a problem.

  As described above, the detection of the broken line portion 7c in the second embodiment described above is performed by observing the surface potential distribution of the wiring 4t to be inspected as in the first embodiment. However, the surface potential of the lower-layer inspected wiring 4t embedded in the insulating layer 3 is difficult. For this reason, in the observation of the surface potential distribution, the scanning line 12 is set so as to cross the portion where the wiring 4t to be inspected appears on the insulating layer 3, for example, the upper wiring 4t-2.

  The third embodiment of the present invention relates to a TEG wiring in which the inspected wiring 4t and the floating wiring 4f of the first embodiment have a via chain structure.

  FIG. 9 is a plan view of a wiring pattern according to the third embodiment of the present invention, and shows a wiring 4 pattern including a wiring to be inspected 4t and a floating wiring 4f. FIG. 10 is a cross-sectional view of a wiring pattern according to the third embodiment of the present invention, and FIGS. 10A and 10B respectively show a straight line AA ′ cross section and a straight line BB ′ cross section in FIG. 9.

  Referring to FIG. 9, the wiring 4 pattern of the third embodiment is substantially the same as the first embodiment except for the via chain structure.

  Referring to FIGS. 9 and 10A, the inspected wiring 4t of the third embodiment has the same via chain structure as that of the inspected wiring 4t of the second embodiment, that is, the upper layer divided and arranged on a straight line. Interconnection between the wirings to be inspected 4t-1 to 4t-5 and the lower wirings to be inspected 4st-1 to 4st-4, which are arranged in the gaps between the divided parts and embedded in the insulating layer 3, A via chain structure including the vias 8.

  On the other hand, with reference to FIGS. 9 and 10B, the floating wiring 4f has a via chain structure similar to that of the wiring to be inspected 4t, is formed on the insulating layer 3, and is divided and arranged on a straight line. Upper-layer floating wirings 4f-1 to 4f-3, gaps between the divided portions and lower-layer floating wirings 4sf-1 to 4sf-4 disposed at both ends of the floating wiring 4f, and upper-layer floating wiring 4f- 1 to 4f-3 and the lower layer floating wirings 4sf-1 to 4sf-4 are connected to form a peer 8 that forms a via chain structure. The floating wiring 4t is arranged between the wirings to be inspected 4 and constitutes a line and space structure. The lower layer floating wirings 4sf-1 to 4sf-4 are simultaneously formed in the same manner as the lower layer wirings 4st-1 to 4st-4.

  In the third embodiment, the defect detection of the wiring 4 is performed by the same method as in the first embodiment. However, the surface potential distribution is measured in the same manner as in the second embodiment, on the part where the inspected wiring 4t is exposed on the upper surface of the insulating layer 3, for example, on the scanning line crossing the upper layer inspected wiring 4t-3.

  According to the third embodiment, since the floating wiring 4f is provided, it is possible to detect defects in both the disconnection portion 7c and the short-circuit portion 7s of the wiring 4t to be inspected. In addition, since the wiring 4 having a via chain structure including a large number of vias 8 is used, a connection failure in the via 8 portion and a short circuit in the via 8 portion are efficiently detected. Therefore, it is particularly suitable for checking the connection failure of the via 8 and the occurrence frequency of the short circuit.

  The fourth embodiment of the present invention relates to a TEG having a to-be-inspected wiring 4t having a two-layer structure in which upper and lower layers are connected by a plurality of vias.

  FIG. 11 is a plan view of a wiring pattern according to the fourth embodiment of the present invention, and represents a wiring 4 pattern having a two-layer structure. FIG. 12 is a cross-sectional view of a wiring pattern according to the fourth embodiment of the present invention. FIGS. 12A and 12B show a straight line AA ′ cross section and a straight line BB ′ cross section in FIG. 11, respectively.

  Referring to FIG. 11, the wiring 4 pattern of the fourth embodiment is the same as that of the first embodiment except for the two-layer wiring structure. Referring to FIG. 12A, the wiring to be inspected 4t and the floating wiring 4f are made of a damascene Cu wiring formed on the upper surface of the insulating layer 3, as in the first embodiment.

  In the fourth embodiment, referring to FIG. 12B, the lower-layer inspected wiring 4st and the lower-layer floating wiring 4sf having the same pattern as the inspected wiring 4t and the floating wiring 4f are formed in the insulating layers immediately below the respective wirings. 3 is buried. The to-be-inspected wiring 4t and the floating wiring 4f are respectively connected to the lower-layer inspected wiring 4st and the lower-layer floating wiring 4st buried immediately below by a large number of vias 8 provided along the extending direction. Yes. That is, the to-be-inspected wiring 4t and the floating wiring 4f have a two-layer wiring structure connected by vias.

  According to the fourth embodiment having the two-layer wiring structure, even if the wiring of one layer of the two-layer structure is disconnected, a line that bypasses the disconnected portion is formed by the wiring and via of the other layer. Therefore, the chance that the surface potential distribution changes due to disconnection is reduced. For this reason, the detection sensitivity with respect to a disconnection falls. The detection of the disconnection is an obstacle to the detection of other defects, for example, the short-circuit portion 7s. However, since the sensitivity decreases, the other defects, for example, the short-circuit portion 7s can be detected with high sensitivity.

  The fifth embodiment of the present invention relates to a wiring of a via chain structure that connects gate electrodes.

  FIG. 13 is a plan view of a wiring pattern according to the fifth embodiment of the present invention. FIG. 14 is a cross-sectional view of a wiring pattern according to the fifth embodiment of the present invention, showing a cross section taken along a straight line AA 'in FIG.

  Referring to FIGS. 13 and 14, the fifth embodiment is the same as the second embodiment except that the lower-layer inspected wirings 4st-1 and 4st-2 are composed of gate electrodes formed on the gate insulating film 9. It is the same as the form.

  Referring to FIG. 14, in the fifth embodiment, light having p-type semiconductor substrate 1 as a p-type region and n-well formed on the upper surface of p-type semiconductor substrate 1 as an n-type region 2 n is formed on the upper surface of semiconductor substrate 1. The electromotive force element 2 is formed. Next, the gate insulating film 9 is formed on a part of the upper surface of the n-type region 2n, and a plurality of, for example, two lower inspection wirings 4st-1 and 4st-2 are formed on the gate insulating film 8. These lower-layer inspected wirings 4st-1 and 4st-2 are formed simultaneously with the gate electrodes of the transistors of the semiconductor device. Of course, if necessary, it may be formed under different manufacturing conditions. Usually, a plurality of sets of lower layer inspected wirings 4st-1 and 4st-2 having different gate lengths are formed in the same TEG.

  Further, after forming the insulating layer 3 covering the lower layer inspected wiring 4st-1 and 4st-2 on the semiconductor substrate 1, the lower layer inspected wiring penetrates the insulating layer 3 in the same manner as in the second embodiment. 4st-1, 4st-2 via 6, n-type and p-type connection 6n, via 5 connected to 6p, and upper layer inspection wiring 4t- consisting of Cu wiring having damascene structure on the upper surface of insulating layer 3 1-4t-3 are formed. The steps of forming the vias 6 and 8 and the upper-layer inspected wires 4t-1 to 4t-3 are the same as those in the second embodiment (that is, the first embodiment).

  As a result, the wiring 4 having the same via chain structure as that of the second embodiment, in which the gate electrode formed on the gate insulating film 9 is used as the lower-layer inspected wirings 4st-1 and 4st-2, was formed. If necessary, positive and negative electrodes made of a silicide layer can be formed on the lower end face of the via 5 connecting the photovoltaic element 2 and the n-type and p-type connection portions 6n and 6p layers.

  According to the fifth embodiment, the disconnection of the gate electrode wiring having the via chain structure can be selectively detected.

  As described below, the TEGs of the first to fifth embodiments described above are preferably used by selecting one or more appropriate TEGs depending on the development stage of the semiconductor device.

  FIG. 15 is a plan view of a semiconductor wafer according to the present invention, showing a TEG and a semiconductor device formation region disposed on a semiconductor substrate (semiconductor wafer). FIGS. 1A to 1C show the semiconductor wafers of the first to third embodiments, respectively.

  Referring to FIG. 15, in the method for manufacturing a semiconductor device according to the present invention, a rectangular semiconductor device forming region 20 in which a semiconductor device made of an integrated circuit is to be formed is formed on the main surface of semiconductor wafer 1 (semiconductor substrate 1). Arranged in a matrix. Hereinafter, in order to simplify the description, an example in which the semiconductor device formation regions 20 are arranged in three rows and three columns on the main surface of the semiconductor wafer 1 will be described.

  Referring to FIG. 15A, in the first embodiment, all semiconductor forming regions 20 arranged on the main surface of the semiconductor wafer 1 are used as TEG forming regions. That is, a plurality of TEGs 21 to 24 are formed in each semiconductor formation region 20 where a semiconductor device should be originally formed, and no semiconductor device is formed on the main surface of the semiconductor wafer 1.

  The plurality of TEGs 21 to 24 select TEGs that can easily detect defects most important as investigation targets and easily analyze the relationship with manufacturing conditions from the TEGs of the first to fifth embodiments. And use. At this time, each of the plurality of TEGs 21 to 24 may be different from each other, and the relationship between a plurality of types of defects may be investigated, and all of them may be the same to refine the investigation based on a large number of data collection.

  Since the first embodiment is capable of collecting a large amount of data and a large amount of data, the stage of defect occurrence is unknown, for example, the early stage of development of a semiconductor device, or the wiring pattern of a semiconductor device or the manufacturing conditions thereof are greatly increased. It is suitable for grasping the outline of the defect that actually occurs by using it at the stage when there is a major change.

  Referring to FIG. 15B, in the second embodiment, some of the semiconductor formation regions 20 arranged on the main surface of the semiconductor wafer 1 are, for example, two semiconductor formation regions 20 of TEG. Used as a formation area. For example, a plurality of TEGs 21 to 24 are formed in the two semiconductor formation regions 20, and an integrated circuit (semiconductor device) is formed in the remaining seven semiconductor formation regions 20.

  In the second embodiment, it is possible to effectively investigate a specific defect that occurs in the semiconductor manufacturing process. For this reason, it is suitable for investigating the relationship between an important specific defect and manufacturing conditions by using it in the early stage of mass production of a semiconductor device.

  Referring to FIG. 15C, the TEG 25 of the third embodiment is arranged between the semiconductor formation regions 20 arranged on the main surface of the semiconductor wafer 1, for example, on a slice line. Therefore, a semiconductor device (integrated circuit) is formed in the semiconductor device formation region 20, and no TEG is formed. It is desirable that the TEG 25 can selectively detect a specific defect, and such an appropriate TEG is selected from the first to fifth embodiments and used.

  In the third embodiment, the number of semiconductor devices formed on the same semiconductor wafer 1 can always be maximized without being affected by TEG formation. Therefore, it is suitable for monitoring manufacturing conditions in the mass production stage of semiconductor devices.

  By applying the present invention to the investigation of the relationship between manufacturing conditions and defects in the development or mass production of semiconductor devices, the results of the investigation of manufacturing conditions and wiring defects can be quickly fed back to the manufacturing conditions. Development of equipment and adjustment of manufacturing conditions in the mass production process can be performed quickly.

1 Semiconductor substrate (semiconductor wafer)
2 Photovoltaic element 2p p-type region 2n n-type region 2-1 positive electrode 2-2 negative electrode 3 insulating layer 3a lower insulating layer 3b upper insulating layer 4 wiring 4t inspected wiring 4t-1 to 4t to 5 upper inspected Wiring 4f Floating wiring 4f-1 to 4f-3 Upper layer floating wiring 4st, 4st-1 to 4st-4 Lower layer inspection wiring 4sf, 4sf-1 to 4sf-4 Lower layer floating wiring 5, 8 Via 5s For via connection Wiring 6n n-pole connection part 6p p-pole connection part 7 defect 7s short-circuit part 7c disconnection part 9 gate insulating film 11 light 12 scanning line 20 semiconductor device formation regions 21 to 24, 25 TEG
30 Kelvin force microscope (KFM)
DESCRIPTION OF SYMBOLS 31 Probe drive part 32 Arm 33 XY stage 33a Transparent part 33b Through-hole 34 Control part 34a, 34b, 35a, 36b Lead wire 35 Measurement part 36 Light source 37 Probe 38 Contact needle

Claims (6)

Forming a photovoltaic element on the upper surface of the semiconductor substrate;
Forming an insulating layer covering the photovoltaic element on the semiconductor substrate;
Forming a plurality of inspected wirings having one end connected to the positive electrode of the photovoltaic element and the other end connected to the negative electrode of the photovoltaic element on the upper surface of the insulating layer;
Injecting light from the lower surface of the semiconductor substrate to excite the photovoltaic element and generating a potential difference at both ends of the wiring to be inspected;
Measuring a surface potential distribution of the wiring to be inspected using a scanning surface potential microscope;
And a step of detecting disconnection of the wiring to be inspected based on the surface potential distribution. The plurality of wirings to be inspected are formed in parallel with each other,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of measuring the surface potential distribution measures a surface potential along a scanning direction orthogonal to an extending direction of the wiring to be inspected.   3. The method of manufacturing a semiconductor device according to claim 2, wherein a defect of the wiring to be inspected is detected from a disturbance in the period of the surface potential distribution along the scanning direction. Simultaneously with the formation of the wiring to be inspected, a process of forming a floating wiring having a floating potential extending in parallel with the wiring to be inspected on the upper surface of the insulating layer;
2. The method of manufacturing a semiconductor device according to claim 1, further comprising: detecting a disconnection of the wiring to be inspected and a short circuit between the wiring to be inspected and the floating wiring based on the surface potential distribution. The inspected wiring is a plurality of upper layer inspected wirings formed by being separated in the extending direction on the upper surface of the insulating layer;
A lower-layer inspected wiring embedded in the insulating layer;
A via for connecting the lower layer inspection wiring and the upper layer inspection wiring;
2. The method of manufacturing a semiconductor device according to claim 1, wherein a plurality of the upper layer inspected wirings formed separately are connected in series via the via and the lower layer inspected wiring. A photovoltaic element formed on the upper surface of the semiconductor substrate and excited by light incident from the lower surface of the semiconductor substrate;
An insulating layer formed on the semiconductor substrate and covering the photovoltaic element;
A plurality of wirings to be inspected formed on the upper surface of the insulating layer, one end connected to the positive electrode of the photovoltaic element and the other end connected to the negative electrode of the photovoltaic element;
A TEG element comprising:

Images