CN107591341B - Abnormal point grabbing method - Google Patents
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- CN107591341B CN107591341B CN201710771558.3A CN201710771558A CN107591341B CN 107591341 B CN107591341 B CN 107591341B CN 201710771558 A CN201710771558 A CN 201710771558A CN 107591341 B CN107591341 B CN 107591341B
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Abstract
The application provides an abnormal point grabbing method, which is applied to a three-dimensional silicon perforation technology integrated circuit comprising at least two comb-shaped lines and a substrate, and comprises the following steps: acquiring a comb-shaped line leaking electricity to the substrate as an abnormal point comb-shaped line to be grabbed; a connecting end is additionally arranged; electrically connecting the connecting end with the substrate, and forming a first loop with the comb-shaped line of the abnormal point to be grabbed; and testing the first loop and capturing abnormal points. According to the abnormal point grabbing method provided by the invention, the connecting end is additionally arranged to form a loop with the comb-shaped line with electric leakage, detection is carried out again, and the abnormal point is grabbed, so that the electric leakage formed by adopting a pressurization mode is avoided, and the loop is formed for detection, so that the problems that the original appearance is influenced and the original information is missed due to the fact that the information of the sample is damaged are avoided.
Description
Technical Field
The invention relates to the technical field of semiconductor device detection, in particular to an abnormal point grabbing method.
Background
The current products of UTS (Ultra thin stack), BSI (Backside illumination) and 3D IC are the TSV (Through Silicon Via) technology. In testing abnormal conditions, it is common to use an IMD (Inter Metal Dielectric) test structure of UTS and 3D IC products, which is shown in fig. 1A, and includes at least two Comb lines (Comb a and Comb B) each including a plurality of structural units, and a Metal line M1 connecting the plurality of structural units together. The structure of each structural unit is shown in fig. 1B, which is a partial enlarged view of a single structural unit a in fig. 1A, each structural unit includes SE (Silicon etch ), TE (Trench etch, Trench etch), DV (Deep via, Deep hole fabrication), and TM (Top metal), as shown in fig. 1C, which is a schematic view of a real sample of each structural unit, and includes a Silicon substrate 01, and a structure 02 after etching the Silicon substrate and filling metal copper (Cu), wherein an oxide layer is provided between the Silicon substrate Si and Cu for isolation, thereby preventing electric leakage.
In the prior art, when the IMD structures of the UTS and the 3D IC are abnormal, a voltage or current is usually applied to form a loop by two comb lines, and the Change of current in the whole loop is induced under a laser (laser) condition, so that an OBIRCH (optical beam induced Resistance Change) is applied to capture a hot spot, thereby locating an abnormal point.
However, due to the existence of the silicon substrate in the IMD test structure, the problem that a certain comb-shaped line leaks electricity to the silicon substrate may occur, so that a loop cannot be formed, and abnormal point grabbing cannot be performed.
In order to solve the above problems, the prior art generally adopts a technical measure that a larger voltage is continuously applied to the whole loop formed by the two comb-shaped lines and the silicon substrate, so that the other comb-shaped line also leaks electricity to the silicon substrate, or the electricity directly leaks electricity between the two comb-shaped lines, a new loop is formed, and then an abnormal point is grabbed.
However, this method destroys the information of the sample itself, such as UTS, BSI, or 3D IC, due to the large applied voltage, and affects the initial morphology, thereby missing the initial information of the sample.
Disclosure of Invention
In view of this, the invention provides an abnormal point grabbing method to solve the problems that the original appearance is affected and the original information is missed because the information of a sample is damaged when an abnormal point is grabbed in the prior art.
In order to achieve the purpose, the invention provides the following technical scheme:
an abnormal point grabbing method is applied to a three-dimensional through silicon via technology integrated circuit comprising at least two comb lines and a substrate, and comprises the following steps:
acquiring a comb-shaped line leaking electricity to the substrate as an abnormal point comb-shaped line to be grabbed;
a connecting end is additionally arranged;
electrically connecting the connecting end with the substrate, and forming a first loop with the comb-shaped line of the abnormal point to be grabbed;
and testing the first loop and capturing abnormal points.
Preferably, the additional connection end specifically includes:
and modifying the three-dimensional silicon perforation technology integrated circuit by using a focused ion beam machine, and adding a connecting end.
Preferably, the connection terminal is a connection terminal in the three-dimensional through silicon via technology integrated circuit.
Preferably, the connection terminal is a connection terminal newly added outside the three-dimensional through silicon via technology integrated circuit.
Preferably, the comb-shaped line with the electric leakage oriented to the substrate is used as a comb-shaped line with an abnormal point to be grabbed; the method specifically comprises the following steps:
selecting any two comb lines to form a second loop;
detecting a current in the second loop;
and if the currents at the two ends of the second loop are not matched, determining that the end with the larger detection current is the comb-shaped line leaking electricity to the substrate and is used as the comb-shaped line of the abnormal point to be grabbed.
Preferably, the testing the first loop and capturing the abnormal point specifically includes:
and detecting the current change in the first loop by adopting a light beam induction resistance change technology, and capturing abnormal points.
Preferably, the substrate is a silicon substrate.
Preferably, it is applied to three-dimensional through-silicon-via chip products.
Preferably, it is applied to UTS ultra thin stack or backside illuminated image sensors.
According to the technical scheme, the abnormal point grabbing method provided by the invention comprises the steps of firstly obtaining the comb-shaped line leaking electricity to the substrate as the comb-shaped line of the abnormal point to be grabbed; a connecting end is additionally arranged; electrically connecting the connecting end with the substrate, and forming a first loop with the comb-shaped line of the abnormal point to be grabbed; and testing the first loop and capturing abnormal points. The abnormal point grabbing method provided by the invention has the advantages that the connecting end is additionally arranged, the circuit is formed by the connecting end and the comb-shaped line with electric leakage, then the detection is carried out, and the abnormal point is grabbed, so that the electric leakage formed by adopting a pressurization mode is avoided, the circuit is formed for detection, and the problems that the original appearance is influenced and the original information is missed due to the fact that the information of the sample is damaged are further avoided.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1A is a diagram of an actual IMD test structure of the prior art;
FIG. 1B is a partially enlarged view of a single structural unit A in FIG. 1A;
FIG. 1C is a schematic diagram of the actual sample structure of a single structural unit;
FIG. 2 is a simplified top view schematic diagram of a prior art IMD test structure;
FIG. 3A is an equivalent circuit diagram of an IMD test structure when single-ended leakage to the silicon substrate occurs;
FIG. 3B is a diagram illustrating the structure of detecting leakage current of the circuit corresponding to FIG. 3A;
FIG. 4A is an equivalent circuit diagram of an IMD test structure provided by the prior art;
FIG. 4B is an equivalent circuit diagram of another IMD test structure provided by the prior art;
fig. 5 is a schematic flow chart of an abnormal point capturing method according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a specific process for obtaining a comb line leaking to a substrate according to an embodiment of the present invention;
FIG. 7 is an equivalent circuit diagram of an IMD test structure according to an embodiment of the present invention;
FIG. 8 is an I-V plot measured from an equivalent circuit diagram of the IMD test structure shown in FIG. 7 according to an embodiment of the present invention;
fig. 9 is a diagram illustrating a result of capturing a hot spot by detecting a change in current using OBIRCHI according to an embodiment of the present invention;
FIG. 10 is a cross-sectional view of a sample cut along line BB' of FIG. 9 using FIB according to an embodiment of the present invention;
FIG. 11 is a schematic diagram of a sample cut along the line BB' in FIG. 9 using FIB according to an embodiment of the present invention.
Detailed Description
As described in the background section, the applied voltage in the prior art is large, which damages the sample information of the UTS or the 3D IC, affects the initial morphology, and thus misses the initial information of the sample.
Specifically, as shown in fig. 2, which is a simplified top view structure diagram of the IMD test structure, two Comb lines Comb a and Comb B each include a metal line M1 and a plurality of structural units connected together by a metal line M1. The insulativity between the metals is evaluated by increasing voltage at the connecting ends at the two ends of the two comb lines, and if no current exists between the two comb lines, the test result is normal; if the test result is abnormal (initial leakage, or low voltage), the structure needs to be analyzed for failure. In the process of failure analysis and positioning, a situation that a single end (Comb a) leaks electricity to a silicon substrate Si in a loop formed by two Comb lines may occur, as shown in fig. 3A, an equivalent circuit diagram of an IMD test structure when the single end leaks electricity to the silicon substrate occurs, and a leakage path is shown as AA in the diagram; as shown in fig. 3B, the graph of the current detection result is shown, wherein the ordinate represents the magnitude of the leakage current, and the abscissa represents the magnitude of the voltage applied across the loop. The leakage current (If) at one end (Comb a) increases with the voltage applied at the two ends of the loop (such as Pad1 and Pad2 in fig. 3A), and the leakage current increases, so that the currents at the two ends of the loop are different. And only a single end (Comb a) leaks current to the silicon substrate Si, so that no loop is formed in the whole test structure, and therefore abnormal point capture cannot be performed.
In the prior art, the abnormal point is mainly positioned by applying voltage/current and capturing a hot spot by using OBIRCHI, and is mainly realized by using the current change in the whole loop caused under the laser condition.
Specifically, for the case of single-end leakage to the silicon substrate, by continuing to apply voltage, the other end (Comb B) also leaks to the silicon substrate Si, and the leakage path is BB, as shown in fig. 4A as an equivalent circuit; or the two comb lines are directly leaked with the leakage path AB to form an equivalent circuit as shown in FIG. 4B, so that loops are formed to capture abnormal points.
However, in this case, the applied voltage is large, which may damage the information of the sample itself of the UTS, BSI, or 3D IC, and affect the initial morphology, thereby missing the initial information of the sample.
Based on this, the invention provides an abnormal point grabbing method, which is applied to a three-dimensional silicon perforation technology integrated circuit comprising at least two comb lines and a substrate, and comprises the following steps:
acquiring a comb-shaped line leaking electricity to the substrate as an abnormal point comb-shaped line to be grabbed;
a connecting end is additionally arranged;
electrically connecting the connecting end with the substrate, and forming a first loop with the comb-shaped line of the abnormal point to be grabbed;
and testing the first loop and capturing abnormal points.
The abnormal point grabbing method provided by the invention comprises the steps of firstly obtaining a comb-shaped line leaking electricity to a substrate as a comb-shaped line of an abnormal point to be grabbed; a connecting end is additionally arranged; electrically connecting the connecting end with the substrate, and forming a first loop with the comb-shaped line of the abnormal point to be grabbed; and testing the first loop and capturing abnormal points. The abnormal point grabbing method provided by the invention has the advantages that the connecting end is additionally arranged, the circuit is formed by the connecting end and the comb-shaped line with electric leakage, then the detection is carried out, and the abnormal point is grabbed, so that the electric leakage formed by adopting a pressurization mode is avoided, the circuit is formed for detection, and the problems that the original appearance is influenced and the original information is missed due to the fact that the information of the sample is damaged are further avoided.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides an abnormal point grabbing method, which is applied to a three-dimensional through silicon via technology integrated circuit comprising at least two comb lines and a substrate, wherein the specific form of the three-dimensional through silicon via technology integrated circuit is not limited in the embodiment, and optionally, the three-dimensional through silicon via technology integrated circuit is a 3D IC (three-dimensional through silicon via chip product), a UTS (Universal test system) or a BSI (base station interface). In this embodiment, optionally, the substrate is a silicon (Si) substrate.
As shown in fig. 5, the outlier capture method includes:
s101: acquiring a comb-shaped line leaking electricity to the substrate as an abnormal point comb-shaped line to be grabbed;
in this embodiment, the specific steps of obtaining the comb-shaped line with the orientation substrate leakage as shown in fig. 6 include:
s1011: selecting any two comb lines to form a second loop;
because the three-dimensional silicon perforation technology integrated circuit comprises at least two comb lines, the comb line for detecting the electric leakage needs two comb lines to form a loop, then current detection is carried out, and the comb line for detecting the electric leakage is determined. And after the abnormal points are grabbed, continuously selecting other two comb-shaped lines for current detection, and if the currents at the two ends of the loop formed by the two comb-shaped lines are different, judging that the single end leaks electricity to the silicon substrate, so that the leaky comb-shaped line is determined.
S1012: detecting a current in the second loop;
in this embodiment, a specific method for detecting the current in the second loop is not limited, and optionally, the method includes: inducing current change in the second loop under the laser condition; detecting a current across the second loop.
S1013: and if the currents at the two ends of the second loop are not matched, determining that the end with the larger detection current is the comb-shaped line leaking electricity to the substrate and is used as the comb-shaped line of the abnormal point to be grabbed.
The comb-shaped line with the abnormal point leaks electricity to the substrate, so that the detected leakage current is large, and the comb-shaped line with the leakage current is detected and used as the comb-shaped line with the abnormal point to be grabbed.
When the currents at the two ends of the second loop are the same or matched, the process returns to step S1011 and is repeated.
S102: a connecting end is additionally arranged;
in this embodiment, a specific process method for adding the connection terminal is not limited, and optionally, the three-dimensional silicon perforation technology integrated circuit is modified by using an FIB (Focused Ion beam) machine, and the connection terminal is added.
In the FIB, an ion beam generated by a liquid metal (Ga) ion source is accelerated by an ion gun, focused, and irradiated on the surface of a sample to generate a secondary electron signal, thereby obtaining an electron image. This function is similar to SEM (Scanning Electron Microscope), or stripping surface atoms with a high current ion beam to achieve micro-or nano-scale surface topography.
The application of FIB technology in chip design and processing process includes: 1) IC chip circuit modification: physical modification of chip circuitry with FIBs allows chip designers to test chip problems for faster and more accurate verification of design solutions. If there is a problem in a partial area of the chip, the function of the area can be isolated or corrected by FIB so as to find the syndrome of the problem. The number of unsuccessful design scheme modifications can be reduced by using the FIB modification chip, and the development time and period are shortened. 2) Cross-Section analysis: FIB is used to make section fault at specific position of IC chip in order to observe section structure and material of material and to analyze chip structure defect at fixed point.
In the embodiment of the invention, a step of setting a connecting terminal is added, preferably, the connecting terminal is a function of an IC chip circuit modified by FIB.
It should be noted that, in this embodiment, a specific form of the additional connection terminal is not limited, and the optional connection terminal may be a connection terminal in the three-dimensional through silicon vias integrated circuit, that is, a connection terminal located at the periphery of the test structure in the UTS, BSI, or 3D IC and having no influence on the test structure. The connecting end can also be a connecting end newly added outside the three-dimensional silicon perforation technology integrated circuit, namely a connecting end is newly added through an FIB machine.
S103: electrically connecting the connecting end with the substrate, and forming a first loop with the comb-shaped line of the abnormal point to be grabbed;
referring to fig. 7, in the embodiment, the newly added connection Pad3 is connected to the silicon substrate Si in the FIB machine, and since the Comb-shaped line of the abnormal point to be captured leaks electricity to the silicon substrate Si, a complete loop, i.e., a first loop, is formed between the connection Pad3, the silicon substrate Si, and the Comb-shaped line Comb a of the abnormal point to be captured, and thus the loop can be used for capturing the abnormal point.
It should be noted that, in this embodiment, the positive and negative voltages at the connection end Pad3 and the connection end Pad1 are not limited, as long as a loop is formed between the two, fig. 7 in this embodiment is merely an example, and the embodiment of the present invention is not limited.
S104: and testing the first loop and capturing abnormal points.
In this embodiment, a specific method for capturing the outlier is not limited, and optionally, a light beam induced resistance change technology OBIRCH is used to detect a current change in the first loop to capture the outlier.
The OBIRCH technology is a novel high-resolution microscopic defect positioning technology, and can quickly and accurately position device failure defects in a large range, so that the OBIRCH technology is widely applied to device failure analysis. The method has the advantages of rapidness (the luminous point of the complex IC can be checked only by one-time imaging), universality (the method can be connected with a tester), no artificial problem, small sensitive leakage current of mu A magnitude and the like.
As shown in fig. 8, in order to measure the I-V curve of the IMD test structure shown in fig. 7 by using OBIRCHI to detect the change of current, it can be seen that the currents at both ends of the first loop are matched, identical, and the current detection can be performed normally.
As shown in fig. 9, a result diagram of capturing a hot spot by applying the OBIRCHI detection current change is shown, it can be seen that a light emitting point of the IC is obtained by one OBIRCHI detection imaging, that is, a hot spot H occurs in the entire UTS or the 3D IC, and the hot spot H is an abnormal point described in this embodiment.
Fig. 10 shows a cross-sectional view of a sample cut by FIB along the BB' line in fig. 9, and it can be seen from observation that a part of copper crosses the isolated oxide to the silicon, i.e. there is a white line between the silicon substrate 1 and SE2, as indicated by the circle 3 in fig. 10, i.e. by actual observation, the abnormal point is indeed found and the abnormal point is successfully captured, which is schematically shown in fig. 11, and the silicon substrate 1 and the copper in SE2 are electrically connected, as indicated by the circle 3 in fig. 11.
The abnormal point grabbing method provided by the invention comprises the steps of firstly obtaining a comb-shaped line leaking electricity to a substrate as a comb-shaped line of an abnormal point to be grabbed; a connecting end is additionally arranged; electrically connecting the connecting end with the substrate, and forming a first loop with the comb-shaped line of the abnormal point to be grabbed; and testing the first loop and capturing abnormal points. The abnormal point grabbing method provided by the invention has the advantages that the connecting end is additionally arranged, the circuit is formed by the connecting end and the comb-shaped line with electric leakage, then the detection is carried out, and the abnormal point is grabbed, so that the electric leakage formed by adopting a pressurization mode is avoided, the circuit is formed for detection, and the problems that the original appearance is influenced and the original information is missed due to the fact that the information of the sample is damaged are further avoided.
It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (9)
1. An abnormal point grabbing method is applied to a three-dimensional through silicon via technology integrated circuit comprising at least two comb lines and a substrate, and comprises the following steps:
acquiring a comb-shaped line leaking electricity to the substrate as an abnormal point comb-shaped line to be grabbed;
a connecting end is additionally arranged;
electrically connecting the connecting end with the substrate, and forming a first loop with the comb-shaped line of the abnormal point to be grabbed;
testing the first loop and grabbing abnormal points;
obtaining a comb-shaped line which is oriented to the substrate and leaks electricity, wherein the comb-shaped line is used as an abnormal point comb-shaped line to be grabbed; the method specifically comprises the following steps:
selecting any two comb lines to form a second loop;
detecting a current in the second loop;
and if the currents at the two ends of the second loop are not matched, determining that the end with the larger detection current is the comb-shaped line leaking electricity to the substrate and is used as the comb-shaped line of the abnormal point to be grabbed.
2. The method for grabbing abnormal points according to claim 1, wherein the adding of the connecting end specifically comprises:
and modifying the three-dimensional silicon perforation technology integrated circuit by using a focused ion beam machine, and adding a connecting end.
3. The outlier capture method of claim 2, wherein said connection terminal is a connection terminal in said three-dimensional through-silicon-via integrated circuit.
4. The outlier capture method of claim 2, wherein said connection terminal is a newly added connection terminal outside said three-dimensional through silicon via technology integrated circuit.
5. The method for capturing the abnormal point according to claim 1, wherein the detecting the current in the second loop specifically includes:
inducing current change in the second loop under the laser condition;
detecting a current across the second loop.
6. The method for capturing outliers of claim 1, wherein the testing the first loop to capture outliers comprises:
and detecting the current change in the first loop by adopting a light beam induction resistance change technology, and capturing abnormal points.
7. The method of claim 1, wherein the substrate is a silicon substrate.
8. The outlier capture method of claim 7, applied to a three-dimensional through-silicon-via chip product.
9. The method of claim 7, wherein the method is applied to an ultra-thin stack or a backside illuminated image sensor.
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| JP2012173103A (en) * | 2011-02-21 | 2012-09-10 | Renesas Electronics Corp | Failure analyzer and failure analysis method of semiconductor integrated circuit |
| CN103137511B (en) * | 2011-11-25 | 2016-01-06 | 中芯国际集成电路制造(上海)有限公司 | The method of testing of silicon through hole test structure and correspondence |
| JP2014107483A (en) * | 2012-11-29 | 2014-06-09 | Fujitsu Semiconductor Ltd | Obirch inspection method and obirch device |
| JP2016014553A (en) * | 2014-07-01 | 2016-01-28 | 三菱電機株式会社 | Failure analyzer |
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