JP4114294B2 - Semiconductor device and inspection method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device mounted on a bare chip mounting product such as a hybrid ECU and an inspection thereof.
[0002]
[Prior art]
In recent years, downsizing of semiconductor mounting products has progressed rapidly, and there is a demand for mounting semiconductor chips in a bare state. FIG. 3 is a schematic diagram relating to a conventional inspection of a semiconductor chip such as a bare chip.
[0003]
As shown in FIG. 3, a semiconductor chip J2 is mounted on a substrate J1, and a terminal J3 of one semiconductor chip J2 and a terminal J3 of another semiconductor chip J2 are connected to a wiring J4 and a wire formed on the substrate J1. They are electrically connected by a wire J5 or the like formed by a bond. In the illustrated example, the inspection terminal J6 is provided from the wiring J4 which is the same node as the two semiconductor chips J2. The semiconductor chip J2 is inspected by probing the inspection terminal J6.
[0004]
[Problems to be solved by the invention]
However, even if it is possible to judge the functional quality of this product from the limited inspection terminals provided on the mounting board, it is possible to identify and repair defective chips after mounting. There is a problem that failure analysis of whether the characteristic is broken is difficult.
[0005]
The above problem is caused by the fact that a plurality of semiconductor chips share one node after the semiconductor chips are mounted on the substrate. That is, even if a defect of a semiconductor chip is detected at the inspection terminal, this problem occurs because it is not possible to identify which semiconductor chip is defective among a plurality of semiconductor chips sharing the same node.
[0006]
In view of the above problems, an object of the present invention is to provide a semiconductor device capable of independently inspecting a semiconductor chip, an inspection method thereof, and a semiconductor chip.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, according to the first aspect of the present invention, the semiconductor chip (1) includes the test terminals (4b, 5b) electrically connected to the internal circuit (2) and the peripheral circuit. A bare chip IC having bonding terminals (4a, 5a) for connection, wherein the inspection terminals (4b, 5b) are electrically connected directly to the internal circuit (2), and bonding terminals (4a, 5a) 5a) is characterized in that it is electrically connected to the inspection terminals (4b, 5b) via the switch means (60).
[0008]
In the present invention, the semiconductor chip (1) is electrically disconnected from the peripheral circuit by electrically disconnecting the bonding terminals (4a, 5a) and the inspection terminals (4b, 5b) using the switch means (60). In the cut state, the semiconductor chip (1) can be inspected independently using the inspection terminals (4b, 5b).
[0009]
In this case, if the bonding terminals (4a, 5a) are positioned on the outer peripheral side of the inspection terminals (4b, 5b) on the upper surface of the chip as in the invention described in claim 2, the bonding terminals (4a, 5a) After being electrically connected to the peripheral circuit using 5a), the inspection can be easily performed using the inspection terminals (4b, 5b).
[0010]
In the invention according to claim 3, the semiconductor chip (1) includes the inspection terminals (4b, 5b) electrically connected to the internal circuit (2) and the bonding terminals for electrical connection to the peripheral circuits. (4a, 5a) and a bare chip IC having a said test terminals (4b, 5b) electrically connected directly said internal circuit and (2), bonding terminals (4a, 5a) is testing terminal ( 4b and 5b) are electrically connected via the switch means (60), and the bonding terminals (4a and 5a) and the inspection terminals (4b and 5b) are electrically connected using the switch means (60). After cutting, the semiconductor chip (1) is inspected using the inspection terminals (4b, 5b).
[0011]
According to the present invention, the semiconductor chip (1) can be electrically disconnected from the peripheral circuit by electrically disconnecting the bonding terminals (4a, 5a) and the inspection terminals (4b, 5b). The semiconductor chip can be inspected independently.
[0015]
In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is an electric circuit diagram of a bare chip IC according to the semiconductor device of this embodiment. As shown in FIG. 1, a logic circuit block (internal circuit) 2 is formed in a bare chip IC 1 as a semiconductor chip that is a monolithic IC, and a Vss (ground) terminal 3 is connected to the logic circuit block 2. Vdd (power supply) terminals 4a and 4b are exposed. Further, terminals 5a and 5b electrically connected to the input / output terminals of the logic circuit block 2 are provided.
[0017]
Each of the terminals 5a and 5b and the Vdd terminals 4a and 4b connected to the input / output terminals is a set of two terminals, one of which is a peripheral circuit (including electronic components, a power supply line, and a ground line). Are the bonding terminals 4a and 5a for conducting the electrical connection, and the other are the inspection terminals 4b and 5b for inspecting the bare chip IC1.
[0018]
Each inspection terminal 4b, 5b is electrically connected directly to the logic circuit block 2, and each bonding terminal 4a, 5a forms a set via a switch circuit block 60 as a switch means. The test terminals 4b and 5b are electrically connected.
[0019]
In FIG. 1, except for the Vdd terminals 4a and 4b, only one set of bonding terminals 5a and inspection terminals 5b are shown. In practice, however, the logic circuit is similar to the one set of terminals 5a and 5b. A plurality of sets of bonding terminals and inspection terminals connected to the input / output terminals of the block 2 are formed.
[0020]
Here, the switch circuit block 60 includes a transmission gate composed of a Pch MOS transistor 61 and an Nch MOS transistor 62. The gate of the Pch MOS transistor 61 and the CS (chip select) terminal 7 are connected, and the gate of the Nch MOS transistor 62 is connected to the CS terminal 7 via the inverter 63.
[0021]
Further, a pull-down resistor 8 is incorporated so that the CS signal becomes low level when the CS terminal 7 is opened, and a diode 9 for circuit protection is provided between the wiring from the CS terminal 7 and the power supply and ground. Yes. Further, the substrate potential of the Pch MOS transistor 61 and the power source of the inverter 63 are taken from the bonding terminal 4a of the Vdd terminals 4a and 4b.
[0022]
FIG. 2 is a schematic view of the bare chip IC 1 as viewed from above with respect to the arrangement of the bonding terminals 4a and 5a and the inspection terminals 4b and 5b. As shown in FIG. 2, in this embodiment, pads are formed on the upper surface of the chip, and the pads 10 arranged on the edge (outer peripheral side) of the bare chip IC1 correspond to the bonding terminals 4a and 5a. The pads 11 arranged on the inner peripheral side of the bare chip IC 1 with respect to the edge pads 10 correspond to the inspection terminals 4b and 5b.
[0023]
The bare chip IC1 is mounted on the substrate, and the pads 10 (bonding terminals) disposed on the edge of the bare chip IC1 are electrically connected to the peripheral circuit by wire bonding or the like.
[0024]
In the bare chip IC 1 having the above configuration, the CS signal is at a low level while a bias is applied from the outside of the bare chip IC 1 between the bonding terminal 4a of the Vdd terminals 4a and 4b and the Vss (ground) terminal 3. At this time, since both the Pch MOS transistor 61 and the Nch MOS transistor 62 are turned on, the transmission gate is turned on, and the bare chip IC1 is electrically connected to the peripheral circuit. On the other hand, when the CS signal is at a high level, the two types of transistors 61 and 62 are both turned off, so that the transmission gate is turned off. Electrically disconnected, and the bare chip IC1 is disconnected from the peripheral circuit.
[0025]
The bare chip IC1 is inspected by probing the pads 11 corresponding to the inspection terminals 4b and 5b in a state where the bare chip IC1 is disconnected from the peripheral circuit and the logic circuit block 2 is energized with the power supply.
[0026]
By the way, according to the present embodiment, the inspection terminals 4b and 5b and the bonding terminals 4a and 5a are provided, and the transmission gate is provided between them, so that the bare chip IC1 is electrically connected from the peripheral circuit as described above. After the bare chip IC1 is mounted on the substrate, the bare chip IC1 can be inspected alone.
[0027]
Further, since the inspection is performed by electrically disconnecting the bare chip IC1 from the peripheral circuit, the leakage current, the standby current, etc. of the bare chip IC1 can be inspected, and a highly reliable semiconductor device is obtained by improving the testability. be able to.
[0028]
Further, since the bonding terminals 4a and 5a are provided on the outer peripheral side of the bare chip IC1 with respect to the inspection terminals 4b and 5b, the wires are connected to the inspection terminals 4b and 5b after the bare chip IC1 is mounted on the substrate by wire bonding or the like. Since it does not cross over, it is possible to easily probe the inspection terminals 4b and 5b.
[0029]
In addition, since it becomes easy to identify a defective chip, it becomes possible to repair parts more appropriately. In addition, failure analysis of what characteristics of the chip have failed is facilitated. Further, by providing the inspection terminals 4b and 5b on the bare chip IC1 side that can be highly integrated, the area of the inspection terminals on the mounting substrate side can be greatly reduced. As a result, the substrate can be reduced in size, and the cost can be reduced particularly in a ceramic multilayer substrate where the substrate is expensive.
[0030]
In this embodiment, the transmission gate is turned off when the CS signal is at a high level and the bare chip IC1 is electrically disconnected. However, the bare chip IC1 is disconnected when at a low level. May be.
[0031]
Further, when the number of terminals of the bare chip IC1 is small, the pads 10 and 11 are not provided double at the edge of the bare chip IC1 as in the present embodiment, but a pair of bonding terminals at the edge of the bare chip IC1. Pads corresponding to each of 4a, 5a and inspection terminals 4b, 5b may be alternately arranged.
[0032]
In addition, in this embodiment, although it is hatching also about what is not sectional drawing, it is a thing for convenience only and does not show a cross section.
[Brief description of the drawings]
FIG. 1 is an electric circuit diagram of a bare chip IC according to a semiconductor device of an embodiment.
FIG. 2 is a schematic top view of a bare chip IC according to the semiconductor device of the present embodiment.
FIG. 3 is a schematic diagram relating to inspection of a conventional semiconductor mounted product.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip, 4a, 5a ... Terminal for bonding,
4b, 5b ... inspection terminals, 60 ... switch means.

Claims (3)

In a semiconductor device in which a semiconductor chip (1) is mounted on a substrate and the semiconductor chip (1) is electrically connected to a peripheral circuit,
The semiconductor chip (1) includes inspection terminals (4b, 5b) electrically connected to the internal circuit (2), and bonding terminals (4a, 5a) electrically connected to the peripheral circuits. A bare chip IC with
The inspection terminals (4b, 5b) are electrically connected directly to the internal circuit (2), and the bonding terminals (4a, 5a) are connected to the inspection terminals (4b, 5b) via switch means (60). A semiconductor device characterized by being electrically connected to each other.   The bonding terminals (4a, 5a) and the inspection terminals (4b, 5b) are arranged on the upper surface of the chip, and the bonding terminals (4a, 5a) are more peripheral than the inspection terminals (4b, 5b). The semiconductor device according to claim 1, wherein the semiconductor device is located on a side. In a method for inspecting a semiconductor device in which a semiconductor chip (1) is mounted on a substrate and the semiconductor chip (1) is electrically connected to a peripheral circuit,
The semiconductor chip (1) includes inspection terminals (4b, 5b) electrically connected to the internal circuit (2), and bonding terminals (4a, 5a) electrically connected to the peripheral circuits. A bare chip IC with
The inspection terminals (4b, 5b) are electrically connected directly to the internal circuit (2), and the bonding terminals (4a, 5a) are connected to the inspection terminals (4b, 5b) via switch means (60). Are electrically connected,
After electrically disconnecting the bonding terminals (4a, 5a) and the inspection terminals (4b, 5b) using the switch means (60), the semiconductor using the inspection terminals (4b, 5b) A method for inspecting a semiconductor device, comprising inspecting a chip (1).

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