JPH0299877A - Integrated circuit part and contact inspection thereof - Google Patents

Integrated circuit part and contact inspection thereof

Info

Publication number
JPH0299877A
JPH0299877A JP63251771A JP25177188A JPH0299877A JP H0299877 A JPH0299877 A JP H0299877A JP 63251771 A JP63251771 A JP 63251771A JP 25177188 A JP25177188 A JP 25177188A JP H0299877 A JPH0299877 A JP H0299877A
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit component
circuit
circuit board
state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63251771A
Other languages
Japanese (ja)
Inventor
Kiyokazu Arai
新井 喜代和
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP63251771A priority Critical patent/JPH0299877A/en
Publication of JPH0299877A publication Critical patent/JPH0299877A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To enable inspection of a junction between a circuit board and a chip by switching a normal operation mode over to a junction inspection mode in an integrated circuit chip. CONSTITUTION:A circuit is provided between a bonding pad section 21 and an input/output buffer circuit of an integrated circuit chip to switch a normal operation mode over to a junction inspection mode and a terminal 26 is used as control terminal. Then, when the terminal 26 is high, transistors (TR) 22 and 23 are turned ON while TRs 24 and 25 are turned OFF while the TRs 24 and 25 are turned ON to enter the junction inspection mode and a circuit part 20 for normal operation is separated electrically from a signal terminal. At this point, as a wire pattern for inspection is pulled out at each signal terminal of the chip on a circuit board, a probing head of an inspector is pressed on the wire pattern. Thus, by measuring a conducting state, a junction condition can be inspected in a soldering between the chip and the circuit board.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は接続検査回路を備えた集積回路部品、及びその
回路を用いて、当該集積回路部品と当該集積回路部品を
搭載する回路基板との接続状態を検査する接続検査方法
に関する。
[Detailed Description of the Invention] [Industrial Field of Application] The present invention provides an integrated circuit component equipped with a connection inspection circuit, and a method for connecting the integrated circuit component and a circuit board on which the integrated circuit component is mounted using the circuit. The present invention relates to a connection inspection method for inspecting connection status.

〔従来の技術〕[Conventional technology]

集積回路部品とこれを搭載する回路基板との接続には一
般に半田が使用される。従来、この種の集積回路部品と
回路基板との接合状態は、目視による外観検査が行われ
ていた。なお、集積回路チップ内に相互接続欠陥検出回
路を組み込み、通常動作モードで集積回路チップ間の相
互接続欠陥および内部欠陥を検出することは、例えば特
開昭57−180140号公報に記載されている。
Solder is generally used to connect integrated circuit components to the circuit board on which they are mounted. Conventionally, the state of bonding between this type of integrated circuit component and a circuit board has been visually inspected. Note that incorporating an interconnection defect detection circuit into an integrated circuit chip and detecting interconnection defects and internal defects between integrated circuit chips in a normal operation mode is described in, for example, Japanese Patent Laid-Open No. 180140/1982. .

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

集積回路部品の外形形状としては、第3図(、)に示す
様に回路基板32に信号端子33を貫通させて、半田3
4により接合するピングリッドアレイ(PGA)タイプ
のもの、同図(b)に示す様な回路基板32の表面に半
田34で直付けすべく、信号端子33が集積回路部品本
体31の周辺に出ているフラットタイプのものなどがあ
るが、これらはいずれも矢印Aの方向から見れば、半田
34の接合状態が目で見ることができ、目視による検査
が可能であった。
As for the external shape of the integrated circuit component, as shown in FIG.
4, the signal terminal 33 is protruded from the periphery of the integrated circuit component body 31 in order to be directly attached to the surface of the circuit board 32 with solder 34 as shown in FIG. There are flat types, but in all of these, the bonded state of the solder 34 can be seen with the naked eye when viewed from the direction of arrow A, and visual inspection is possible.

しかし、部品の高密度実装化に伴ない、第4図(、)に
示す様に、ピングリッドアレイでありながら、回路基板
42の表面に半田44にて信号端子43を接続する、い
わゆるbutt 5olderタイプのもの、あるいは
、同図(b)に示す様な集積回路チップ45そのものを
半田バンプ47で、セラミックなどでできた回路基板4
6に接合する、いわゆるControll Co11a
pse Bondタイプのものが使用され、これらはい
ずれも矢印Bの方向から見ても、半田の接合状態は確認
できず、目視による検査が不可能である。これらの実装
形態では、従来の目視検査が不可能なため、一般には個
々の部品の回路基板との接合状態は検査せず、部品を組
み込んだ状態での装置の機能をテストすることにより異
常の有無を検査している状況である。
However, with the increase in the density of components, as shown in FIG. type, or the integrated circuit chip 45 itself as shown in FIG.
6, the so-called Control Co11a
A pse bond type is used, and in all of these, even when viewed from the direction of arrow B, the state of solder joint cannot be confirmed, and visual inspection is impossible. Conventional visual inspection is not possible in these mounting formats, so the bonding state of individual components to the circuit board is generally not inspected, but abnormalities are detected by testing the functionality of the device with the components installed. We are currently inspecting whether or not there are any.

本発明の目的は、上記第4図に示す様な部品の実装形態
でも、部品側々の回路基板との接続状態を、電気的に検
査することを可能にすることにある。
An object of the present invention is to make it possible to electrically inspect the connection state of each part to the circuit board even in the case where the parts are mounted as shown in FIG. 4 above.

〔課題を解決するための手段〕[Means to solve the problem]

上記目的を達成するため、本発明は、集積回路部品のボ
ンディング・パッド部と、入出力バッファ回路部との間
に通常の動作モードと接合検査モ−ドとの切り換えを行
う回路を設ける。
In order to achieve the above object, the present invention provides a circuit for switching between a normal operation mode and a bond inspection mode between a bonding pad section of an integrated circuit component and an input/output buffer circuit section.

すなわち、当該集積回路部品の特定の信号端子の状態に
より、通常動作モードと接合検査モードとの切り換えを
行い、接合検査モードにした時に、当該集積回路部品の
任意の信号端子間が電気的に接続された状態となる回路
構成とし、当該集積回路部品を搭載した回路基板上から
、任意の信号端子間の導通状態を検査し、回路基板と集
積回路部品との接合検査を行うものである。
In other words, depending on the state of a specific signal terminal of the integrated circuit component, the normal operation mode and bonding inspection mode are switched, and when the bonding inspection mode is selected, any signal terminals of the integrated circuit component are electrically connected. The circuit configuration is such that the integrated circuit component is mounted, and the continuity between arbitrary signal terminals is inspected from the circuit board on which the integrated circuit component is mounted, and the bonding between the circuit board and the integrated circuit component is inspected.

〔作 用〕[For production]

集積回路部品の特定の端子を制御用端子とし、例えば、
当該制御信号端子がrHighJ状態の時、集積回路部
品の信号端子毎に、ポンディングパッド部と人出カバソ
ファ部との間に設けられたスイッチ回路が、通常動作モ
ードにスイッチする。−方、前記制御信号端子がrLo
wJ状態の時には、前記スイッチ回路が接合検査モード
になる様にスイッチし、当該集積回路部品の信号端子群
が電気的に接続される様にする。この時、通常動作用の
人出力バッファ回路部と接合検査用回路網とは、影響を
及ぼし合うことなく電気的に分離される。
A specific terminal of an integrated circuit component is used as a control terminal, for example,
When the control signal terminal is in the rHighJ state, a switch circuit provided between the bonding pad section and the crowd cover sofa section switches to the normal operation mode for each signal terminal of the integrated circuit component. - On the other hand, the control signal terminal is rLo
When in the wJ state, the switch circuit switches to a bonding inspection mode, so that the signal terminal group of the integrated circuit component is electrically connected. At this time, the human output buffer circuit for normal operation and the junction inspection circuit are electrically separated without affecting each other.

当該集積回路部品は、回路基板に信号端子部で半田等の
媒体により接合されている。当該回路基板上では、前記
集積回路部品の信号端子毎に、検査用の配線パターンが
、通常の信号用パターンからタップ・オフして引き出さ
れる。この検査用の配線パターンに検査装置のブロービ
ングヘッドを圧接し、導通状態を測定することにより、
集積回路部品と回路基板との半田による接合状態を検査
する。
The integrated circuit component is bonded to the circuit board at the signal terminal portion using a medium such as solder. On the circuit board, a wiring pattern for inspection is tapped off from a normal signal pattern and drawn out for each signal terminal of the integrated circuit component. By press-contacting the blobbing head of the testing device to this wiring pattern for testing and measuring the continuity state,
Inspect the state of solder joints between integrated circuit components and circuit boards.

すなわち、回路基板上の任意信号端子の検査用タップオ
フ配線パターンに、前記検査装置により電圧もしくは電
流を供給し、他の任意の信号端子の検査用タップオフ配
線パターンで前記供給電圧もしくは電流を測定する。信
号端子群は当該集積回路部品上で電気的に接続されてい
るために、前記供給電圧もしくは電流は、接合状態が正
常な信号端子部に伝搬し、検出することができる。一方
、接合が異常な信号端子部には、前記供給電圧もしくは
電流が検出できない。
That is, a voltage or current is supplied by the inspection device to a tap-off wiring pattern for inspection of an arbitrary signal terminal on the circuit board, and the supplied voltage or current is measured using a tap-off wiring pattern for inspection of another arbitrary signal terminal. Since the signal terminal group is electrically connected on the integrated circuit component, the supply voltage or current can be propagated to the signal terminal portion with a normal connection state and detected. On the other hand, the supply voltage or current cannot be detected at the signal terminal portion where the connection is abnormal.

この様にして、集積回路部品と回路基板との半田による
接合状態を電気的に検査することができる。
In this way, it is possible to electrically inspect the state of the solder joint between the integrated circuit component and the circuit board.

〔実施例〕〔Example〕

以下、本発明の一実施例について図面により説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第1図は本発明の検査回路を備えた集積回路チップの一
実施例の全体図である。第1図において、10は集積回
路チップ、11はボンディング・パッド、12は入出力
バッファ回路領域、13は内部回路領域である。本発明
にかへわる検査回路は12の人出力バッファ領域に設け
られる。
FIG. 1 is an overall view of one embodiment of an integrated circuit chip equipped with a test circuit of the present invention. In FIG. 1, 10 is an integrated circuit chip, 11 is a bonding pad, 12 is an input/output buffer circuit area, and 13 is an internal circuit area. The test circuit according to the present invention is provided in twelve human output buffer areas.

第2図は第1図の0部を拡大し、その回路構成を示した
ものである。第2図において、20は通常の入出力バッ
ファ回路、21がボンディング・パッドである。また、
26が通常モードと接合検査モードを切り換える制御端
子(TESTピン)であり、27がスイッチ回路へのド
ライバ回路である。スイッチ回路は、トランジスタ23
及び24.25で構成される。
FIG. 2 is an enlarged view of part 0 of FIG. 1, showing its circuit configuration. In FIG. 2, 20 is a normal input/output buffer circuit, and 21 is a bonding pad. Also,
26 is a control terminal (TEST pin) for switching between the normal mode and the bonding test mode, and 27 is a driver circuit to the switch circuit. The switch circuit is a transistor 23
and 24.25.

TESTピン26がrHighJの時、 トランジスタ
22.23がオンし、トランジスタ24,25がオフす
る。この時の等価回路を第5図(a)に示す。この時、
集積回路チップ10は通常動作モードで動作する。一方
、TESTピン26がrLowJの時、トランジスタ2
2.23がオフし、トランジスタ24.25がオンする
。この時の等価回路は、第5図(b)の様になる。この
時に集積回路チップ10は、集積回路部品と回路基板と
の接合検査用の回路に構成されて、通常動作用の回路2
0が、信号端子から電気的に切り離される。
When TEST pin 26 is rHighJ, transistors 22 and 23 are turned on and transistors 24 and 25 are turned off. The equivalent circuit at this time is shown in FIG. 5(a). At this time,
Integrated circuit chip 10 operates in a normal operating mode. On the other hand, when TEST pin 26 is rLowJ, transistor 2
2.23 is turned off and transistor 24.25 is turned on. The equivalent circuit at this time is as shown in FIG. 5(b). At this time, the integrated circuit chip 10 is configured into a circuit for inspecting the bonding between the integrated circuit component and the circuit board, and a circuit 2 for normal operation.
0 is electrically disconnected from the signal terminal.

第6図に、集積回路部品と配線基板との接合状態を説明
する図を示す。第6図(a)は集積回路部品の断面図で
、50が集積回路チップ、56が回路基板であり、52
がボンディング・ワイヤ及びパッケージ上の配線パター
ン、53がリードパン(信号端子)、54がリードピン
53と回路基板56との接合用半田、55が検査用の引
き出しパターンである。
FIG. 6 shows a diagram illustrating the bonding state between the integrated circuit component and the wiring board. FIG. 6(a) is a cross-sectional view of an integrated circuit component, in which 50 is an integrated circuit chip, 56 is a circuit board, and 52
5 is a bonding wire and a wiring pattern on the package, 53 is a lead pan (signal terminal), 54 is solder for joining the lead pin 53 and the circuit board 56, and 55 is a drawing pattern for inspection.

第6図(a)に対し、検査モード時の簡略化した回路構
成イメージ図を第6図(b)に示す。50〜55は同図
(a)に対応する。59が接合検査モードの時、集積回
路チップ50上で実現された閉回路であり、各々の信号
端子パッド51、ボンディング・ワイヤ及びパッケージ
上のパターン52、リードピン(信号端子)53、回路
基板56上の引き出しパターン55を経由して、プロー
ビングパッド57につながる。接合検査は、回路基板5
6上のプロービング用パッド57に検査装置のプローバ
ーを当て\行う。この時、TESTピン(57xピン)
をrLowJ状態にし、57nビンを検査用電圧供給ピ
ンとして電圧Vを印加すると、57 a 、 57 b
 、 57 c 、 −ピン等には接合部54が正常で
あると電圧Vが検出される。また、例えば54mピンの
接合状態が異常であると、57mピン用の検査用引き出
しパターンには電圧Vが検出されず、異常が判明する。
In contrast to FIG. 6(a), FIG. 6(b) shows a simplified image diagram of the circuit configuration in the inspection mode. 50 to 55 correspond to the same figure (a). 59 is a closed circuit realized on the integrated circuit chip 50 when in the bonding inspection mode, and each signal terminal pad 51, bonding wire and pattern 52 on the package, lead pin (signal terminal) 53, and circuit board 56 It is connected to a probing pad 57 via a pull-out pattern 55 . The bonding inspection is performed on the circuit board 5.
6. Apply the prober of the inspection device to the probing pad 57 on the top 6. At this time, TEST pin (57x pin)
When put into the rLowJ state and apply voltage V using the 57n bin as the test voltage supply pin, 57a, 57b
, 57c, − pins, etc., a voltage V is detected when the joint portion 54 is normal. Further, for example, if the connection state of the 54m pin is abnormal, the voltage V will not be detected in the test lead-out pattern for the 57m pin, and the abnormality will be revealed.

58は通常信号パターンであるが、回路基板上に複数の
集積回路部品が搭載される場合は、前記通常信号パター
ンに接続される他の集積回路部品の出力回路は、ハイイ
ンピーダンス状態もしくは当該集積回路チップと同じT
ESTモード(検査モード)にしておく必要がある。
58 is a normal signal pattern, but when multiple integrated circuit components are mounted on the circuit board, the output circuits of other integrated circuit components connected to the normal signal pattern are in a high impedance state or the integrated circuit concerned Same T as chip
It is necessary to set it to EST mode (test mode).

第7図に接合検査時のプロービング作業のイメージ図を
示す。64が検査対象の集積回路部品本体、65がチー
ドピン、66が引き出しパターン、67が接合用半田で
ある。62がプローブ、6゜がプローブ固定用モールド
、63が検査装置本体、61がケーブルである。
Figure 7 shows an image of probing work during joint inspection. Reference numeral 64 indicates the main body of the integrated circuit component to be inspected, reference numeral 65 indicates a lead pin, reference numeral 66 indicates a drawing pattern, and reference numeral 67 indicates solder for joining. 62 is a probe, 6° is a probe fixing mold, 63 is an inspection device main body, and 61 is a cable.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、集積回路のパッケージがButt 5
olderタイプとか、集積回路チップを半田バンプで
回路基板に接合するCCBタイプのように、回路基板と
集積回路部品との接合状態が目視では検査できないもの
に対して、電気的に接合検査ができる効果がある。また
、直流特性的に検査が行えるため、接合していても非常
に高抵抗な接合状態の場合にも異常の検出が可能である
According to the invention, the integrated circuit package is Butt 5
The effect of being able to electrically inspect the bonding of circuit boards and integrated circuit components that cannot be inspected visually, such as older types and CCB types that bond integrated circuit chips to circuit boards with solder bumps. There is. Furthermore, since inspection can be performed in terms of DC characteristics, it is possible to detect abnormalities even in the case of a very high resistance bonded state.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例である集積回路チップの全体
図、第2図は第1図の一部の回路構成図、第3図は従来
の集積回路部品の実装形態を示す図、第4図は本発明の
対象となる実装形態を示す図、第5図は第2図の回路の
制御状態による等価回路を示す図、第6図は本発明実施
例の集積回路部品の物理状態と回路構成イメージを示す
図、第7図は本発明実施例の集積回路部品を回路基板に
搭載した状態での接合検査方法のイメージを示す図であ
る。 10・・・集積回路チップ、  11・・・ボンディン
グ・パッド、  12・・・入出力バッファ回路領域、
13・・・内部回路領域、 20・・・人出力バッファ
回路、 21・・・ボンディング・パッド、22.23
,24.25・・スイッチ回路用1−ランパスタ、  
26・・・制御信号入力用ポンディングパッド、  2
7・・・スイッチ回路用ドライバ回路群。 (ω TEST56ン二確がりトーーイ5 几 (す r−一一コ (I))
FIG. 1 is an overall diagram of an integrated circuit chip that is an embodiment of the present invention, FIG. 2 is a partial circuit configuration diagram of FIG. 1, and FIG. 3 is a diagram showing the mounting form of conventional integrated circuit components. FIG. 4 is a diagram showing an implementation form to which the present invention is applied, FIG. 5 is a diagram showing an equivalent circuit according to the control state of the circuit in FIG. 2, and FIG. 6 is a diagram showing the physical state of an integrated circuit component according to an embodiment of the present invention. FIG. 7 is a diagram showing an image of a circuit configuration, and FIG. 7 is a diagram showing an image of a bonding inspection method in a state where an integrated circuit component according to an embodiment of the present invention is mounted on a circuit board. 10... Integrated circuit chip, 11... Bonding pad, 12... Input/output buffer circuit area,
13... Internal circuit area, 20... Human output buffer circuit, 21... Bonding pad, 22.23
,24.25...1-runpasta for switch circuit,
26...Ponding pad for control signal input, 2
7... Driver circuit group for switch circuits. (ω TEST 56 njigarari toi 5 几 (sr-11ko (I))

Claims (2)

【特許請求の範囲】[Claims] (1)入出力信号端子群及び電源給電端子群を備えた集
積回路部品において、当該集積回路部品の特定の信号端
子に第1状態の制御信号を入力することにより、当該集
積回路部品の通常の動作が可能となる状態に入出力信号
端子群を設定する場合と、前記特定の信号端子に第2状
態の制御信号を入力することにより、当該集積回路部品
の任意の信号端子どうしが電気的に導通する一方、通常
の動作をする機能部とは影響を及ぼし合うことがない様
に電気的に切り離された状態となる場合とに切り換える
回路を備えてなる集積回路部品。
(1) In an integrated circuit component equipped with an input/output signal terminal group and a power supply terminal group, by inputting a control signal in the first state to a specific signal terminal of the integrated circuit component, the normal state of the integrated circuit component can be adjusted. When setting the input/output signal terminal group to a state where operation is possible, and inputting a control signal in the second state to the specific signal terminal, arbitrary signal terminals of the integrated circuit component can be electrically connected to each other. An integrated circuit component that is equipped with a circuit that can switch between being electrically conductive and electrically disconnected from functional parts that operate normally so as not to affect each other.
(2)前記請求項(1)記載の集積回路部品の入出力信
号端子群及び電源給電端子群を接続部として、前記集積
回路部品を接続搭載する回路基板において、前記集積回
路部品の特定の信号端子に、当該回路基板上に設けられ
た引き出し配線部より制御信号を入力することにより、
前記集積回路部品の特定の信号端子以外の任意の信号端
子どうしが電気的に導通する状態に設定し、当該導通し
た信号端子群の任意のピンに、前記回路基板上に設けら
れた引き出し配線部より電気信号を入力し、他の任意の
信号端子への電気信号の伝搬状態を、前記回路基板上に
設けられた引き出し配線部より検出することにより、前
記集積回路部品と前記回路基板との接続状態を検査する
ことを特徴とする接続検査方法。
(2) In a circuit board on which the integrated circuit component is connected and mounted using the input/output signal terminal group and the power supply terminal group of the integrated circuit component as described in claim (1) as connecting portions, a specific signal of the integrated circuit component is provided. By inputting a control signal to the terminal from the lead wiring section provided on the circuit board,
Arbitrary signal terminals other than specific signal terminals of the integrated circuit component are set to be electrically connected to each other, and a lead-out wiring section provided on the circuit board is connected to an arbitrary pin of the electrically connected signal terminal group. The connection between the integrated circuit component and the circuit board is established by inputting an electrical signal from the integrated circuit component and detecting the propagation state of the electrical signal to any other signal terminal from a lead-out wiring section provided on the circuit board. A connection inspection method characterized by inspecting a state.
JP63251771A 1988-10-07 1988-10-07 Integrated circuit part and contact inspection thereof Pending JPH0299877A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63251771A JPH0299877A (en) 1988-10-07 1988-10-07 Integrated circuit part and contact inspection thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63251771A JPH0299877A (en) 1988-10-07 1988-10-07 Integrated circuit part and contact inspection thereof

Publications (1)

Publication Number Publication Date
JPH0299877A true JPH0299877A (en) 1990-04-11

Family

ID=17227676

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63251771A Pending JPH0299877A (en) 1988-10-07 1988-10-07 Integrated circuit part and contact inspection thereof

Country Status (1)

Country Link
JP (1) JPH0299877A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06289102A (en) * 1993-02-05 1994-10-18 Genrad Inc Automatic release-detecting method
JPH07110358A (en) * 1993-10-08 1995-04-25 Nec Corp Semiconductor integrated circuit
JP2005205071A (en) * 2004-01-26 2005-08-04 Olympus Corp Capsule type medical device
US8847221B2 (en) 2006-10-12 2014-09-30 Ps4 Luxco S.A.R.L. Stacked semiconductor device and method of testing the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06289102A (en) * 1993-02-05 1994-10-18 Genrad Inc Automatic release-detecting method
JPH07110358A (en) * 1993-10-08 1995-04-25 Nec Corp Semiconductor integrated circuit
JP2005205071A (en) * 2004-01-26 2005-08-04 Olympus Corp Capsule type medical device
US8847221B2 (en) 2006-10-12 2014-09-30 Ps4 Luxco S.A.R.L. Stacked semiconductor device and method of testing the same

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