JPH1138079A - Testing method for ball grid array type integrated circuit - Google Patents

Testing method for ball grid array type integrated circuit

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Publication number
JPH1138079A
JPH1138079A JP9192520A JP19252097A JPH1138079A JP H1138079 A JPH1138079 A JP H1138079A JP 9192520 A JP9192520 A JP 9192520A JP 19252097 A JP19252097 A JP 19252097A JP H1138079 A JPH1138079 A JP H1138079A
Authority
JP
Japan
Prior art keywords
electrode
integrated circuit
terminal
terminals
resistance value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9192520A
Other languages
Japanese (ja)
Inventor
Takashi Morita
隆士 森田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP9192520A priority Critical patent/JPH1138079A/en
Publication of JPH1138079A publication Critical patent/JPH1138079A/en
Pending legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To confirm the connection of all terminals to a printed board when multiple terminals are connected by providing current input/output terminals on the printed board, feeding a current, providing voltage measuring terminals, and measuring the voltage between the terminals. SOLUTION: The reference resistance value ΣRre between electrodes 8a, 8b, when the electrode 8a of the electrode group 8 of a printed board 3 connected with power terminals is electrically separated from the other electrode group, is measured in advance with a reference integrated circuit having the same circuit structure as that of a ball grid array type integrated circuit 1 subject to test and normally connected with the terminals to the printed board 3. The electrode 8a of the circuit 1 subject to test is separated, the resistance value ΣR between the electrodes 8a, 8b is measured, ΣRre and ΣR are compared, and the connection state of the power terminals to the electrode group 8 is tested. A current source is connected between an input terminal 4 and an output terminal 6, a current is fed, a voltmeter is connected between the terminals 5, 7, and the voltage between the terminals 5, 7 is measured. The resistance value between the terminals 5, 7 can be thus measured.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は2つ以上の電源端子
を有するボールグリッドアレイ型の集積回路に関し、特
にプリント基板へのはんだボールの接続試験方法に関す
る。
[0001] 1. Field of the Invention [0002] The present invention relates to a ball grid array type integrated circuit having two or more power supply terminals, and more particularly to a method for testing solder ball connection to a printed circuit board.

【0002】[0002]

【従来の技術】[Prior art]

[1]バウンダリ・スキャンテスト方法(IEEE standar
d 1149.1(JTAG)) バウンダリ・スキャンテスト方法は、集積回路の全ての
外部入出力端子を順次走査(スキャン)するように、デ
ータの入出力を行う手法である。この手法が提案する機
能は、以下の通りである。 基板に実装した集積回路間の接続の正常性を検証す
る。 基板に実装した集積回路自身の機能の正常性を検証す
る。 基板に実装した状態で各集積回路の正常動作を監視す
る。
[1] Boundary scan test method (IEEE standar
d 1149.1 (JTAG)) The boundary scan test method is a method of inputting / outputting data so that all external input / output terminals of an integrated circuit are sequentially scanned (scanned). The functions proposed by this method are as follows. Verify the normality of the connection between the integrated circuits mounted on the board. Verifies the normality of the function of the integrated circuit itself mounted on the board. The normal operation of each integrated circuit is monitored while mounted on the board.

【0003】図3は、従来例におけるバウンダリ・スキ
ャン回路の構成を示す図である。図3において、4本
(または5本)のテストアクセスポート(以下、TAP
と記述する)TCK,TMS,(TRST),TDI,
TDOによって、テストロジックに対する命令、テスト
データおよび実行結果の入出力を行う。
FIG. 3 is a diagram showing a configuration of a conventional boundary scan circuit. In FIG. 3, four (or five) test access ports (hereinafter, TAP)
TCK, TMS, (TRST), TDI,
The TDO inputs and outputs instructions, test data, and execution results to and from the test logic.

【0004】このバウンダリ・スキャンテスト方法は、
入出力信号端子の試験方法であり、電源端子およびGN
D端子を確認するのには不十分である。すなわち、最近
の高速信号を扱う集積回路では、電源端子数およびGN
D端子数は、それぞれ2端子以上あるが、バウンダリ・
スキャンテストを集積回路の電源端子およびGND端子
に適用した場合には、複数の電源端子および複数のGN
D端子をそれぞれ1つの端子とみなして試験される。
[0004] This boundary scan test method comprises:
This is a test method for input / output signal terminals.
It is not enough to confirm the D terminal. That is, in recent integrated circuits handling high-speed signals, the number of power supply terminals and GN
The number of D terminals is 2 or more, respectively.
When the scan test is applied to the power supply terminal and the GND terminal of the integrated circuit, the plurality of power supply terminals and the plurality of GNDs
The test is performed by regarding each D terminal as one terminal.

【0005】[2]X線透過試験方法 図4は、従来例におけるX線透過試験方法を説明する図
である。図4に示したX線透過試験方法は、ボールグリ
ッドアレイ型集積回路1の電源用はんだバンプ群2のプ
リント基板3への接続をX線で透視確認する方法であ
る。
[2] X-ray transmission test method FIG. 4 is a diagram illustrating an X-ray transmission test method in a conventional example. The X-ray transmission test method shown in FIG. 4 is a method in which the connection of the power supply solder bump group 2 of the ball grid array type integrated circuit 1 to the printed circuit board 3 is confirmed through X-rays.

【0006】[0006]

【発明が解決しようとする課題】第1の問題点は、バウ
ンダリ・スキャンテスト方法は、それぞれが2端子以上
マルチ接続されている電源端子およびGND端子の全て
の端子の試験をすることができないということである。
その理由は、バウンダリ・スキャンテスト方法は、入出
力信号の動作を確認する試験方法であるので、それぞれ
が2端子以上の電源端子およびGND端子のうちのそれ
ぞれ1端子ずつがプリント基板に接続されていれば、残
りの電源端子およびGND端子がプリント基板に接続さ
れていなくても正常に試験が行われるからである。
The first problem is that the boundary scan test method cannot test all of the power supply terminals and the GND terminals, each of which is multi-connected to two or more terminals. That is.
The reason is that the boundary scan test method is a test method for confirming the operation of the input / output signal, and therefore, each of the power supply terminal has at least two terminals and one of the GND terminals is connected to the printed circuit board. This is because the test is normally performed even if the remaining power supply terminal and the GND terminal are not connected to the printed circuit board.

【0007】第2の問題点は、X線透過試験方法は、は
んだバンプ群がプリント基板に信頼性上問題なくついて
いるかどうかを十分に検証することができないというこ
とである。また、プリント基板の裏面に部品等が実装さ
れている場合には、適用することができないということ
である。その理由は、X線透過試験方法は、X線による
透視確認であり、電気的に特性を確認していないからで
ある。
The second problem is that the X-ray transmission test method cannot sufficiently verify whether or not the solder bump group is attached to the printed board without any problem in reliability. In addition, when a component or the like is mounted on the back surface of the printed circuit board, it cannot be applied. The reason is that the X-ray transmission test method is a radiographic confirmation using X-rays, and the characteristics are not electrically confirmed.

【0008】本発明の目的は、複数の端子がマルチ接続
されている場合の全端子のプリント基板への接続確認を
容易に行うことである。
An object of the present invention is to easily confirm connection of all terminals to a printed circuit board when a plurality of terminals are multi-connected.

【0009】[0009]

【課題を解決するための手段】本発明のボールグリッド
アレイ型集積回路の試験方法は、同一の電気的特性を持
つ複数の第1の端子を有するボールグリッドアレイ型の
集積回路であって、該第1の端子のそれぞれが接続され
るプリント基板の第1の電極群のうちの第2の電極と該
第1の電極群のうちの第3の電極とを電気的に分離し、
該第2の電極と該第3の電極との間の第1の抵抗値を測
定し、該集積回路と同一の回路構成を有し各端子がプリ
ント基板の各電極に正常に接続されている基準集積回路
の、該第2の電極に相当する電極と該第3の電極に相当
する電極との間の第2の抵抗値を測定し、該第1の抵抗
値と該第2の抵抗値とを比較して、該第1の端子と該第
1の電極群との接続状態を試験する。
SUMMARY OF THE INVENTION A ball grid array type integrated circuit testing method according to the present invention is a ball grid array type integrated circuit having a plurality of first terminals having the same electrical characteristics. Electrically separating a second electrode of the first electrode group of the printed circuit board to which each of the first terminals is connected from a third electrode of the first electrode group;
A first resistance value between the second electrode and the third electrode is measured, and each terminal has the same circuit configuration as that of the integrated circuit and each terminal is normally connected to each electrode of the printed circuit board. Measuring a second resistance between an electrode corresponding to the second electrode and an electrode corresponding to the third electrode of the reference integrated circuit, and determining the first resistance and the second resistance; And a connection state between the first terminal and the first electrode group is tested.

【0010】上記本発明のボールグリッドアレイ型集積
回路の試験方法は、複数の電源端子を有するボールグリ
ッドアレイ型の集積回路であって、当該集積回路の電源
用はんだバンプ群が接続されるプリント基板の第1の電
極群のうちの1つの第2の電極と該第1の電極群のうち
の該第2の電極以外の第3の電極群とを電気的に分離
し、該第2の電極に2本の第1の配線を形成し、該第1
の配線の一方に電流入力端子を接続し、該第1の配線の
他方に第1の電圧測定端子を接続し、該第3の電極群の
うちの1つの第4の電極に2本の第2の配線を形成し、
該第2の配線の一方に電流出力端子を接続し、該第2の
配線の他方に第2の電圧測定端子を接続し、該電流入力
端子と該電流出力端子との間に電流源を接続し、該第1
の電圧測定端子と該第2の電圧測定端子との間に電圧計
を接続して、該第2の電極と該第4の電極との間の第1
の抵抗値を測定し、該集積回路と同一の回路構成を有し
各端子がプリント基板の各電極に正常に接続されている
基準集積回路の、該第2の電極に相当する電極と該第4
の電極に相当する電極との間の第2の抵抗値を測定し、
該第1の抵抗値と該第2の抵抗値とを比較して、該電源
端子と該第1の電極群との接続状態を試験する。
The ball grid array type integrated circuit testing method of the present invention is a ball grid array type integrated circuit having a plurality of power supply terminals, and a printed circuit board to which a power supply solder bump group of the integrated circuit is connected. Electrically separates one second electrode of the first electrode group from a third electrode group other than the second electrode of the first electrode group; Forming two first wirings,
A current input terminal is connected to one of the first wirings, a first voltage measuring terminal is connected to the other of the first wirings, and two fourth electrodes are connected to one fourth electrode of the third electrode group. 2 wiring,
A current output terminal is connected to one of the second wires, a second voltage measurement terminal is connected to the other of the second wires, and a current source is connected between the current input terminal and the current output terminal. And the first
A voltmeter is connected between the voltage measuring terminal and the second voltage measuring terminal, and a first voltage between the second electrode and the fourth electrode is connected.
Of the reference integrated circuit having the same circuit configuration as that of the integrated circuit and having each terminal normally connected to each electrode of the printed circuit board. 4
Measuring a second resistance value between the electrode corresponding to the electrode of
The connection between the power supply terminal and the first electrode group is tested by comparing the first resistance value with the second resistance value.

【0011】上記本発明のボールグリッドアレイ型集積
回路の試験方法は、電源端子のみならず、GND端子ま
たは共通信号端子にも適用することができる。
The above-described method for testing a ball grid array type integrated circuit according to the present invention can be applied not only to a power supply terminal but also to a GND terminal or a common signal terminal.

【0012】抵抗値の測定は、低抵抗測定に用いる4端
子測定法を適用して行う。具体的には、電流入力端子と
電流出力端子との間に電流源を接続して電流を流し、電
圧測定端子間に電圧計を接続して電圧を測定する。この
ようにして、基準となる抵抗ΣRreをΣRre=V/Iに
よって計算することができる。
The measurement of the resistance value is performed by applying a four-terminal measurement method used for low resistance measurement. Specifically, a current source is connected between a current input terminal and a current output terminal to flow a current, and a voltmeter is connected between voltage measurement terminals to measure a voltage. In this manner, the reference resistance ΔRre can be calculated by ΔRre = V / I.

【0013】電源端子がマルチ接続されている場合の抵
抗ΣRreは、各電源端子の抵抗Rが全て等しいと仮定し
て、電源端子数をNとすると、 ΣRre=R+R/(N−1) (1) となる。
When the number of power supply terminals is N, assuming that the resistances R of the respective power supply terminals are all equal, the resistance ΣRre when the power supply terminals are multi-connected is as follows: ΣRre = R + R / (N−1) (1) ).

【0014】電源端子の一部が接続されていない場合の
抵抗ΣR*は、接続されていない電源端子数をnとする
と、 ΣR*=R+R/(N−1−n) (2) になる。このため、全ての電源端子が接続されていると
きよりも、接続されていない電源端子があるときの方が
抵抗値は大きくなり、ΣRre<ΣR*となる。したがっ
て、全ての電源端子がプリント基板に接続されている状
態における基準となる抵抗ΣRreをあらかじめ測定して
おけば、はんだバンプ群のプリント基板への接続状態を
試験することができる。
The resistance ΣR * when a part of the power supply terminals are not connected is as follows: ΣR * = R + R / (N−1−n) (2) where n is the number of power supply terminals not connected. Therefore, the resistance value is larger when there is a power supply terminal that is not connected than when all the power supply terminals are connected, and ΔRre <ΔR *. Therefore, if the reference resistance .DELTA.Rre in a state where all the power terminals are connected to the printed circuit board is measured in advance, the connection state of the solder bump group to the printed circuit board can be tested.

【0015】[0015]

【発明の実施の形態】次に、本発明の実施の形態につい
て図面を参照して詳細に説明する。
Next, embodiments of the present invention will be described in detail with reference to the drawings.

【0016】図1は、本発明の一実施の形態におけるボ
ールグリッドアレイ型集積回路の試験方法を説明する図
であり、電源端子の試験を行う場合を示している。図1
に示すように、2つ以上の電源端子を有するボールグリ
ッドアレイ型集積回路1を電源用はんだバンプ群2を介
してプリント基板3に接続する場合に、プリント基板3
の電源用の電極群8と、電極群8のうちの1つの電極8
aに形成された2本の配線の一方が備える電流入力端子
4と、電極8aに形成された2本の配線の他方が備える
電圧測定端子5と、電極群8のうちの1つの電極8bに
形成された2本の配線の一方が備える電流出力端子6
と、電極8bに形成された2本の配線の他方が備える電
圧測定端子7とを有する構成となっている。
FIG. 1 is a diagram for explaining a method of testing a ball grid array type integrated circuit according to an embodiment of the present invention, and shows a case where a power supply terminal is tested. FIG.
As shown in FIG. 1, when a ball grid array type integrated circuit 1 having two or more power supply terminals is connected to a printed circuit board 3 through a power supply solder bump group 2, the printed circuit board 3
Power supply electrode group 8 and one electrode 8 of the electrode group 8
a, a current input terminal 4 provided on one of the two wires formed on the electrode 8a, a voltage measurement terminal 5 provided on the other of the two wires formed on the electrode 8a, and one electrode 8b of the electrode group 8. Current output terminal 6 provided on one of the two formed wirings
And a voltage measurement terminal 7 provided on the other of the two wires formed on the electrode 8b.

【0017】このような構成において、電源端子のそれ
ぞれが接続されるプリント基板3の電極群8の電極8a
を他の電極群とを電気的に分離したときの、電極8aと
電極8bとの間の基準となる抵抗値ΣRreを、試験の対
象となるボールグリッドアレイ型集積回路1と同一の回
路構成を有し各端子がプリント基板に正常に接続されて
いて基準となる集積回路を用いて、あらかじめ測定す
る。そして、試験の対象となるボールグリッドアレイ型
集積回路1の電極8aと他の電極群とを電気的に分離
し、電極8aと電極8bとの間の抵抗値ΣRを測定し、
ΣRreとΣRとを比較して、電源端子の電極群8への接
続状態を試験する。
In such a configuration, the electrodes 8a of the electrode group 8 of the printed circuit board 3 to which each of the power supply terminals is connected.
The resistance ΣRre, which is the reference between the electrodes 8a and 8b when electrically separated from other electrode groups, is set to the same circuit configuration as the ball grid array type integrated circuit 1 to be tested. The measurement is performed in advance by using a reference integrated circuit in which each terminal is normally connected to a printed circuit board. Then, the electrode 8a of the ball grid array integrated circuit 1 to be tested is electrically separated from the other electrode groups, and the resistance ΔR between the electrode 8a and the electrode 8b is measured.
The connection state of the power supply terminal to the electrode group 8 is tested by comparing ΣRre and ΣR.

【0018】[0018]

【実施例】次に本発明の実施例について図面を参照して
詳細に説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings.

【0019】図2は、本発明の一実施例におけるボール
グリッドアレイ型集積回路の試験方法を説明する図であ
り、電源端子の試験を行う場合を示している。図2にお
いては、図1に示したボールグリッドアレイ型集積回路
の試験を行う部分の電気的接続を示している。
FIG. 2 is a diagram for explaining a method of testing a ball grid array type integrated circuit according to one embodiment of the present invention, and shows a case where a power supply terminal is tested. FIG. 2 shows an electrical connection of a portion for testing the ball grid array integrated circuit shown in FIG.

【0020】図1に示した構成において、図2において
は、低抵抗測定に用いる4端子測定法を適用して、抵抗
値の測定を行う。具体的には、電流入力端子4と電流出
力端子6との間に電流源を接続して電流を流し、電圧測
定端子5と電圧測定端子7との間に電圧計を接続して電
圧測定端子5,7間の電圧を測定する。このようにし
て、電源端子間の抵抗値ΣRを測定することができる。
In the configuration shown in FIG. 1, in FIG. 2, the resistance value is measured by applying a four-terminal measurement method used for low resistance measurement. Specifically, a current source is connected between the current input terminal 4 and the current output terminal 6 to flow a current, and a voltmeter is connected between the voltage measurement terminal 5 and the voltage measurement terminal 7 to connect the voltage measurement terminal. Measure the voltage between 5 and 7. In this manner, the resistance ΔR between the power supply terminals can be measured.

【0021】試験前にあらかじめ測定する基準となる集
積回路の電源端子間の抵抗値ΣRreおよび試験において
測定する電源端子間の抵抗値ΣRは、課題を解決するた
めの手段で説明した式(1)および式(2)によって得
られる。
The resistance ΣRre between the power supply terminals of the integrated circuit and the resistance 間 の R between the power supply terminals measured in the test, which are the reference values measured in advance before the test, are calculated by the equation (1) described in the section for solving the problem. And Equation (2).

【0022】ここで、R1をプリント基板配線抵抗を含
むはんだバンプ抵抗とし、R2をケース配線抵抗を含む
ワイヤボンディング抵抗とし、R3を集積回路内の電源
パッド間の配線抵抗とすると、 R=R1+R2+R3 (3) となる。
Here, assuming that R1 is a solder bump resistance including a printed circuit board wiring resistance, R2 is a wire bonding resistance including a case wiring resistance, and R3 is a wiring resistance between power supply pads in an integrated circuit, R = R1 + R2 + R3 ( 3)

【0023】抵抗Rの値が各端子において全て等しい場
合には、ΣRre=R+R/(N−1)となる。電源用は
んだバンプ群2のうちのn個がプリント基板に接続され
ていない場合には、ΣR*=R+R/(N−1−n)と
なり、全ての電源端子が接続されている場合よりも抵抗
値が大きくなる。したがって、初めに全ての電源用はん
だバンプ群2がプリント基板3の電極群8に接続されて
いる場合の基準となる抵抗値ΣRreを測定しておけば、
試験における測定結果から算出したΣRと比較すること
で、電源用はんだバンプ群2のプリント基板3の電極群
8への接続状態を試験することができる。
When the values of the resistors R are all equal at each terminal, ΔRre = R + R / (N−1). When n of the power supply solder bump groups 2 are not connected to the printed circuit board, ΔR * = R + R / (N−1−n), and the resistance is higher than when all power supply terminals are connected. The value increases. Therefore, if the resistance value ΔRre as a reference when all the power supply solder bump groups 2 are connected to the electrode groups 8 of the printed circuit board 3 is measured first,
By comparing with ΔR calculated from the measurement result in the test, the connection state of the power supply solder bump group 2 to the electrode group 8 of the printed circuit board 3 can be tested.

【0024】発明の実施の形態および実施例において説
明した試験方法と同様の手法をGND端子に用いれば、
GND端子のプリント基板への接続状態を試験すること
ができる。また、同様の手法を共通信号端子に用いれ
ば、共通信号端子のプリント基板への接続状態を試験す
ることができる。
If a method similar to the test method described in the embodiments and examples of the invention is used for the GND terminal,
The connection state of the GND terminal to the printed circuit board can be tested. Further, if the same technique is used for the common signal terminal, the connection state of the common signal terminal to the printed circuit board can be tested.

【0025】[0025]

【発明の効果】第1の効果は、同一の電気的特性を持つ
複数の端子を有するボールグリッドアレイ型集積回路に
おいて、はんだバンプ群のプリント基板への接続状態を
試験することができるということである。その理由は、
プリント基板上に電流入出力端子を設けて電流を流し、
電圧測定端子を設けて端子間の電圧を測定することによ
って、低抵抗測定に用いられる4端子測定法を行うから
である。
The first effect is that, in a ball grid array type integrated circuit having a plurality of terminals having the same electric characteristics, the connection state of the solder bump group to the printed circuit board can be tested. is there. The reason is,
Provide current input / output terminals on the printed circuit board to allow current to flow,
This is because a four-terminal measurement method used for low resistance measurement is performed by providing a voltage measurement terminal and measuring the voltage between the terminals.

【0026】第2の効果は、X線透過試験方法による透
視では見つけられない、はんだバンプとプリント基板と
間の接続における信頼性検証をすることができるという
ことである。その理由は、はんだバンプとプリント基板
との間の接続確認を、透視ではなく電気的測定で行うか
らである。
The second effect is that it is possible to verify the reliability of the connection between the solder bump and the printed circuit board, which cannot be found by the X-ray transmission test method. The reason for this is that the connection between the solder bumps and the printed circuit board is confirmed not by seeing through but by electrical measurement.

【0027】このようにして、複数の端子がマルチ接続
されている場合に全端子がプリント基板に接続されてい
るかどうかの確認を容易に行うことができる。
In this manner, when a plurality of terminals are multi-connected, it is possible to easily confirm whether all the terminals are connected to the printed circuit board.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施の形態におけるボールグリッド
アレイ型集積回路の試験方法を説明する図
FIG. 1 is a diagram illustrating a method for testing a ball grid array integrated circuit according to an embodiment of the present invention.

【図2】本発明の一実施例におけるボールグリッドアレ
イ型集積回路の試験方法を説明する図
FIG. 2 is a diagram illustrating a test method of a ball grid array integrated circuit according to one embodiment of the present invention.

【図3】従来例におけるバウンダリ・スキャン回路の構
成を示す図
FIG. 3 is a diagram showing a configuration of a boundary scan circuit in a conventional example.

【図4】従来例におけるX線透過試験方法を説明する図FIG. 4 is a diagram illustrating an X-ray transmission test method in a conventional example.

【符号の説明】[Explanation of symbols]

1 ボールグリッドアレイ型集積回路 2 電源用はんだバンプ群 3 プリント基板 4 電流入力端子 5,7 電圧測定端子 6 電流出力端子 8 電極群 8a,8b 電極 DESCRIPTION OF SYMBOLS 1 Ball grid array type integrated circuit 2 Power supply solder bump group 3 Printed circuit board 4 Current input terminal 5, 7 Voltage measurement terminal 6 Current output terminal 8 Electrode group 8a, 8b Electrode

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 同一の電気的特性を持つ複数の第1の端
子を有するボールグリッドアレイ型の集積回路におい
て、 該第1の端子のそれぞれが接続されるプリント基板の第
1の電極群のうちの第2の電極と該第1の電極群のうち
の第3の電極とを電気的に分離し、該第2の電極と該第
3の電極との間の第1の抵抗値を測定し、 該集積回路と同一の回路構成を有し各端子がプリント基
板の各電極に正常に接続されている基準集積回路の、該
第2の電極に相当する電極と該第3の電極に相当する電
極との間の第2の抵抗値を測定し、 該第1の抵抗値と該第2の抵抗値とを比較して、該第1
の端子と該第1の電極群との接続状態を試験することを
特徴とする、ボールグリッドアレイ型集積回路の試験方
法。
1. A ball grid array integrated circuit having a plurality of first terminals having the same electric characteristics, wherein the first terminals are connected to each other in a first electrode group of a printed circuit board. Is electrically separated from the third electrode of the first electrode group, and a first resistance value between the second electrode and the third electrode is measured. .. Corresponding to the second electrode and the third electrode of the reference integrated circuit having the same circuit configuration as the integrated circuit and having each terminal normally connected to each electrode of the printed circuit board. Measuring a second resistance value between the first and second electrodes; comparing the first resistance value with the second resistance value;
A method for testing a ball grid array type integrated circuit, wherein a connection state between the terminal and the first electrode group is tested.
【請求項2】 複数の電源端子を有するボールグリッド
アレイ型の集積回路において、 当該集積回路の電源用はんだバンプ群が接続されるプリ
ント基板の第1の電極群のうちの1つの第2の電極と該
第1の電極群のうちの該第2の電極以外の第3の電極群
とを電気的に分離し、 該第2の電極に2本の第1の配線を形成し、該第1の配
線の一方に電流入力端子を接続し、該第1の配線の他方
に第1の電圧測定端子を接続し、 該第3の電極群のうちの1つの第4の電極に2本の第2
の配線を形成し、該第2の配線の一方に電流出力端子を
接続し、該第2の配線の他方に第2の電圧測定端子を接
続し、 該電流入力端子と該電流出力端子との間に電流源を接続
し、該第1の電圧測定端子と該第2の電圧測定端子との
間に電圧計を接続して、該第2の電極と該第4の電極と
の間の第1の抵抗値を測定し、 該集積回路と同一の回路構成を有し各端子がプリント基
板の各電極に正常に接続されている基準集積回路の、該
第2の電極に相当する電極と該第4の電極に相当する電
極との間の第2の抵抗値を測定し、 該第1の抵抗値と該第2の抵抗値とを比較して、該電源
端子と該第1の電極群との接続状態を試験することを特
徴とする、請求項1に記載のボールグリッドアレイ型集
積回路の試験方法。
2. A ball grid array type integrated circuit having a plurality of power supply terminals, wherein a second electrode of one of a first electrode group of a printed circuit board to which a power supply solder bump group of the integrated circuit is connected. And a third electrode group of the first electrode group other than the second electrode is electrically separated, and two first wirings are formed on the second electrode, A current input terminal is connected to one of the first wirings, a first voltage measurement terminal is connected to the other of the first wirings, and two fourth electrodes are connected to one fourth electrode of the third electrode group. 2
And a current output terminal is connected to one of the second wires, a second voltage measurement terminal is connected to the other of the second wires, and the current input terminal and the current output terminal are connected to each other. A current source is connected between the first and second voltage measuring terminals, and a voltmeter is connected between the first and second voltage measuring terminals, so that a first voltage between the second and fourth electrodes is measured. 1 is measured, and an electrode corresponding to the second electrode of the reference integrated circuit having the same circuit configuration as the integrated circuit and having each terminal normally connected to each electrode of the printed circuit board, and A second resistance value between an electrode corresponding to a fourth electrode is measured, the first resistance value is compared with the second resistance value, and the power terminal and the first electrode group are compared. 2. The test method for a ball grid array type integrated circuit according to claim 1, wherein a connection state with the circuit is tested.
【請求項3】 複数の接地端子を有するボールグリッド
アレイ型の集積回路において、 当該集積回路の接地用はんだバンプ群に接続されるプリ
ント基板の第1の電極群のうちの1つの第2の電極と該
第1の電極群のうちの該第2の電極以外の第3の電極群
とを電気的に分離し、 該第2の電極に2本の第1の配線を形成し、該第1の配
線の一方に電流入力端子を接続し、該第1の配線の他方
に第1の電圧測定端子を接続し、 該第3の電極群のうちの1つの第4の電極に2本の第2
の配線を形成し、該第2の配線の一方に電流出力端子を
接続し、該第2の配線の他方に第2の電圧測定端子を接
続し、 該電流入力端子と該電流出力端子との間に電流源を接続
し、該第1の電圧測定端子と該第2の電圧測定端子との
間に電圧計を接続して、該第2の電極と該第4の電極と
の間の第1の抵抗値を測定し、 該集積回路と同一の回路構成を有し各端子がプリント基
板の各電極に正常に接続されている基準集積回路の、該
第2の電極に相当する電極と該第4の電極に相当する電
極との間の第2の抵抗値を測定し、 該第1の抵抗値と該第2の抵抗値とを比較して、該接地
端子と該第1の電極群との接続状態を試験することを特
徴とする、請求項1に記載のボールグリッドアレイ型集
積回路の試験方法。
3. A ball grid array type integrated circuit having a plurality of ground terminals, wherein one second electrode of a first electrode group of a printed circuit board connected to a ground solder bump group of the integrated circuit. And a third electrode group of the first electrode group other than the second electrode is electrically separated, and two first wirings are formed on the second electrode, A current input terminal is connected to one of the first wirings, a first voltage measurement terminal is connected to the other of the first wirings, and two fourth electrodes are connected to one fourth electrode of the third electrode group. 2
And a current output terminal is connected to one of the second wires, a second voltage measurement terminal is connected to the other of the second wires, and the current input terminal and the current output terminal are connected to each other. A current source is connected between the first and second voltage measuring terminals, and a voltmeter is connected between the first and second voltage measuring terminals, so that a first voltage between the second and fourth electrodes is measured. 1 is measured, and an electrode corresponding to the second electrode of the reference integrated circuit having the same circuit configuration as the integrated circuit and having each terminal normally connected to each electrode of the printed circuit board, and A second resistance value between an electrode corresponding to a fourth electrode is measured, the first resistance value is compared with the second resistance value, and the ground terminal and the first electrode group are compared. 2. The test method for a ball grid array type integrated circuit according to claim 1, wherein a connection state with the circuit is tested.
【請求項4】 複数の共通信号端子を有するボールグリ
ッドアレイ型の集積回路において、 当該集積回路の共通信号用はんだバンプ群に接続される
プリント基板の第1の電極群のうちの1つの第2の電極
と該第1の電極群のうちの該第2の電極以外の第3の電
極群とを電気的に分離し、 該第2の電極に2本の第1の配線を形成し、該第1の配
線の一方に電流入力端子を接続し、該第1の配線の他方
に第1の電圧測定端子を接続し、 該第3の電極群のうちの1つの第4の電極に2本の第2
の配線を形成し、該第2の配線の一方に電流出力端子を
接続し、該第2の配線の他方に第2の電圧測定端子を接
続し、 該電流入力端子と該電流出力端子との間に電流源を接続
し、該第1の電圧測定端子と該第2の電圧測定端子との
間に電圧計を接続して、該第2の電極と該第4の電極と
の間の第2の抵抗値を測定し、 該集積回路と同一の回路構成を有し各端子がプリント基
板の各電極に正常に接続されている基準集積回路の、該
第2の電極に相当する電極と該第4の電極に相当する電
極との間の第2の抵抗値を測定し、 該第1の抵抗値と該第2の抵抗値とを比較して、該共通
信号端子と該第1の電極群との接続状態を試験すること
を特徴とする、請求項1に記載のボールグリッドアレイ
型集積回路の試験方法。
4. A ball grid array type integrated circuit having a plurality of common signal terminals, wherein a second one of a first electrode group of a printed circuit board connected to a common signal solder bump group of the integrated circuit. Is electrically separated from a third electrode group other than the second electrode of the first electrode group, and two first wirings are formed on the second electrode, A current input terminal is connected to one of the first wires, a first voltage measuring terminal is connected to the other of the first wires, and two wires are connected to one fourth electrode of the third electrode group. Second
And a current output terminal is connected to one of the second wires, a second voltage measurement terminal is connected to the other of the second wires, and the current input terminal and the current output terminal are connected to each other. A current source is connected between the first and second voltage measuring terminals, and a voltmeter is connected between the first and second voltage measuring terminals, so that a first voltage between the second and fourth electrodes is measured. 2 of the reference integrated circuit having the same circuit configuration as that of the integrated circuit and having each terminal normally connected to each electrode of the printed circuit board, and an electrode corresponding to the second electrode of the reference integrated circuit. Measuring a second resistance value between an electrode corresponding to a fourth electrode, comparing the first resistance value with the second resistance value, and comparing the common signal terminal with the first electrode; 2. The method for testing a ball grid array integrated circuit according to claim 1, wherein a connection state with the group is tested.
JP9192520A 1997-07-17 1997-07-17 Testing method for ball grid array type integrated circuit Pending JPH1138079A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9192520A JPH1138079A (en) 1997-07-17 1997-07-17 Testing method for ball grid array type integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9192520A JPH1138079A (en) 1997-07-17 1997-07-17 Testing method for ball grid array type integrated circuit

Publications (1)

Publication Number Publication Date
JPH1138079A true JPH1138079A (en) 1999-02-12

Family

ID=16292661

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9192520A Pending JPH1138079A (en) 1997-07-17 1997-07-17 Testing method for ball grid array type integrated circuit

Country Status (1)

Country Link
JP (1) JPH1138079A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001047016A1 (en) 1999-12-21 2001-06-28 Intel Corporation Method and apparatus for encoding information in an ic package
US6367023B2 (en) 1998-12-23 2002-04-02 Intel Corporation Method and apparatus of measuring current, voltage, or duty cycle of a power supply to manage power consumption in a computer system
US6564332B1 (en) 1998-12-23 2003-05-13 Intel Corporation Method and apparatus for managing power consumption in a computer system responsive to the power delivery specifications of a power outlet
JP2006029898A (en) * 2004-07-14 2006-02-02 Ricoh Co Ltd Substrate for test, and ic socket
JP2007035889A (en) * 2005-07-26 2007-02-08 Lenovo Singapore Pte Ltd Package with solder ball and detection method of abnormality of electronic equipment using the same
JP2010185747A (en) * 2009-02-12 2010-08-26 Casio Computer Co Ltd Panel and method for inspecting mount state of ic chip

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6367023B2 (en) 1998-12-23 2002-04-02 Intel Corporation Method and apparatus of measuring current, voltage, or duty cycle of a power supply to manage power consumption in a computer system
US6564332B1 (en) 1998-12-23 2003-05-13 Intel Corporation Method and apparatus for managing power consumption in a computer system responsive to the power delivery specifications of a power outlet
WO2001047016A1 (en) 1999-12-21 2001-06-28 Intel Corporation Method and apparatus for encoding information in an ic package
JP2006029898A (en) * 2004-07-14 2006-02-02 Ricoh Co Ltd Substrate for test, and ic socket
JP2007035889A (en) * 2005-07-26 2007-02-08 Lenovo Singapore Pte Ltd Package with solder ball and detection method of abnormality of electronic equipment using the same
JP4577839B2 (en) * 2005-07-26 2010-11-10 レノボ・シンガポール・プライベート・リミテッド Electronic device using package having solder balls, and method for detecting abnormal state of package having solder balls
JP2010185747A (en) * 2009-02-12 2010-08-26 Casio Computer Co Ltd Panel and method for inspecting mount state of ic chip

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