JP2006029898A - Substrate for test, and ic socket - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance measuring precision for an electric characteristic test, without bringing two contacts into contact with chip electrodes of a semiconductor device. <P>SOLUTION: An insulating substrate 5 of this substrate 3 for a test is formed, on one surface thereof, with four substrate electrodes 7 formed corresponding to the chip electrodes 1a of a wafer level CSP 1, four sets of wiring patterns 9a, 9b formed successively in the substrate electrodes 7 and provided in every of the substrate electrodes 7, and terminals 11 formed successively in a side end opposite to the substrate electrodes of the wiring patterns 9a, 9b in every of the wiring patterns 9a, 9b. An insulation film 13 for coating the wiring patterns 9a, 9b, and having opening parts on the substrate electrodes 7 and in areas in the vicinity of the terminals 11 is formed on the one surface 5a of the insulating substrate 5. In the wafer level CSP 1, the chip electrodes 1a are joined to the substrate electrodes 7 with solder to be mounted on the substrate 3 for the test. The wiring patterns 9a, 9b connected to the respective substrate electrodes 7 are connected to a testing device via the terminals 11 to be used as a sensing line and a force line. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

The present invention relates to a test substrate and an IC socket for electrical connection between a semiconductor device and a test device for conducting an electrical characteristic test of the semiconductor device.
A plurality of test substrates and IC sockets of the present invention are provided in one plane such as a semiconductor device having a chip electrode composed of lead terminals such as QFP (Quad Flat Package), a BGA (Ball Grid Array) and a CSP (Chip Size Package). The present invention is used for an electrical characteristic test of a semiconductor device such as a semiconductor device in which a plurality of chip electrodes are arranged, and is particularly useful for an electrical characteristic test of a semiconductor device having a fine chip electrode arrangement such as a wafer level CSP.

Conventionally, when conducting an electrical characteristic test of a semiconductor device such as a burn-in test, an IC socket is used to electrically connect the chip electrode of the semiconductor device and the electrode of the test device. In the IC socket, contact terminals made of a conductive material are arranged at positions corresponding to the chip electrodes.
There is a Kelvin contact type IC as an IC socket for a semiconductor device such as a QFP having a chip electrode formed of a lead terminal (see, for example, Patent Document 1 and Patent Document 2). The Kelvin contact method is a method in which a contact for a force line for applying a voltage and a contact for a sense line for detecting a voltage are brought into contact with one chip electrode as a countermeasure against contact resistance.
Further, as an IC socket for a semiconductor device in which a plurality of chip electrodes such as BGA and CSP are arranged on one plane, a pogo pin is brought into contact with the chip electrode (see, for example, Patent Document 3), or a probe needle as a chip electrode. There exists what is made to contact (for example, refer patent document 4).

  Recently, there is a wafer level CSP (see, for example, Patent Document 5). The wafer level CSP is a CSP in which chip electrodes are formed before chip dicing. The size of the wafer level CSP is, for example, about 1.0 mm (millimeter) in outer dimensions and about 0.4 mm in thickness, and the size of the chip electrode is about 0.2 mm in diameter.

JP-A-6-334072 JP 2004-63919 A JP-A-6-334072 JP 2004-63919 A JP 2000-260910 A

In an electrical characteristic test of a semiconductor device, as disclosed in Patent Document 1 and Patent Document 2, it is preferable to increase measurement accuracy by bringing two contacts into contact with a chip electrode.
However, in order to bring two contacts into contact with the chip electrode, there is a problem that the structure of the IC socket becomes complicated and the cost increases.
In addition, it is difficult with the pogo pin disclosed in Patent Document 3 to bring two contacts into contact with a plurality of chip electrodes on one plane such as BGA and CSP, and the probe needle disclosed in Patent Document 4 is used. For example, two contacts can be brought into contact with the chip electrode, but even in this case, the structure of the IC socket becomes complicated and the cost increases. Furthermore, for a semiconductor device having a fine chip electrode array such as a wafer level CSP, it is difficult to bring two contacts into contact with the chip electrode even if a probe needle is used.

  Accordingly, the present invention provides a test substrate and an IC socket using the same that can improve measurement accuracy without bringing two contacts into contact with a chip electrode of a semiconductor device in an electrical characteristic test of the semiconductor device. It is for the purpose.

  A test substrate according to the present invention includes an insulating substrate, a substrate electrode formed on the insulating substrate, to which a chip electrode of a semiconductor device is electrically connected directly or via a conductive material, and the substrate electrode. It comprises at least two wiring patterns that are separated and connected.

  In the test substrate of the present invention, an example in which the substrate electrode and the wiring pattern are formed on the same surface of the insulating substrate can be given. However, the substrate electrode and the wiring pattern are not limited to those formed on the same surface of the insulating substrate, and the substrate electrode and the wiring pattern are connected via connection holes formed in the insulating substrate. And the substrate electrode and the wiring pattern may be formed on different surfaces.

  A plurality of semiconductor device mounting regions; and a plurality of the substrate electrodes for each of the semiconductor device mounting regions, wherein the insulating substrate is folded by bending into a region between adjacent semiconductor device mounting regions of the insulating substrate. A dividing groove for dividing may be provided.

The IC socket according to the present invention has a chip housing part for housing the semiconductor device in a predetermined position, and one end arranged corresponding to the position of the chip electrode of the semiconductor device when housed in the chip housing part. And a test substrate of the present invention having a substrate electrode in contact with the other end of the contact terminal.
An example of the contact terminal is a pogo pin. Here, the pogo pin includes an elastic body such as a coiled spring made of a conductive material inside a cylindrical main body, and an electrode made of a conductive material at one or both ends of the main body. However, the contact terminal is not limited to the pogo pin, and any terminal that can electrically connect the chip electrode and the substrate electrode may be used.

  In the IC socket of the present invention, the semiconductor device to be inspected is a plurality of chip electrodes arranged on one plane, and the chip housing portion is a package housing portion for placing the semiconductor device at a predetermined position. And a biasing member for biasing the semiconductor device housed in the package housing portion downward due to weight, and the contact terminal has the chip electrode on the bottom side. The chip electrode may be disposed corresponding to the position of the chip electrode when accommodated in the package accommodating portion.

  Furthermore, the chip housing portion is temporarily disposed at a position above the package housing portion without contacting the biasing member with the semiconductor device housed in the package housing portion, and then gradually lowered to the semiconductor device. You may make it further provide the biasing member support mechanism made to contact.

As an example of the urging member support mechanism, an urging member support member that arranges the urging member so as to be movable in a vertical direction or a substantially vertical direction above the package housing portion, and the urging member in the semiconductor device. The urging member is supported by the upper step when not in contact, and the urging member is supported by an inclined portion inclined downward from the upper step when the urging member is brought into contact with the semiconductor device. The thing comprised by the slide member to which it descend | falls gradually can be mentioned.
Further, in order to prevent the pressing position of the biasing member from being applied to the semiconductor device, the biasing member support member supports the end side of the biasing member opposite to the slide member as a rotation shaft. It is preferable that
The urging member is disposed above the package housing member by the urging member support member in a state where the urging member is disposed at a position where the urging member is supported by the upper portion of the slide member. At this time, the biasing member and the upper part of the slide member are in contact with each other, but the biasing member and the semiconductor device are not in contact with each other. Thereafter, the urging member is gradually lowered along the inclined portion of the slide member by sliding the slide member to the side where the urging member contacts the inclined portion of the slide member, and the urging member and the semiconductor device are in contact with each other, The semiconductor device is gradually biased by the biasing member.

  Further, the urging member may include a rotating member for reducing friction between the urging member and the slide member at a position corresponding to the slide member.

  Further, the urging member support member may be disposed in a lid member for covering the package guide member.

  The lid fixing member further includes a lid fixing member for fixing the lid member in a state where the lid member covers the package guide member, and the lid fixing member and the slide member are integrated, and the lid fixing member Opens the lid member in a state where the upper step portion of the slide member and the biasing member are in contact with each other, and in a state where the biasing member is in contact with the semiconductor device housed in the package housing portion, You may make it slide so that a cover member may be fixed.

  In the test substrate according to the present invention, since the chip electrode of the semiconductor device is provided with at least two wiring patterns on the substrate electrode that is electrically connected directly or via a conductive material, from the test device to the substrate electrode. The wiring path can be a Kelvin contact method, and the measurement accuracy of the electrical characteristic test can be improved without contacting the two contacts with the chip electrode of the semiconductor device. For example, if a semiconductor device is solder-mounted on a substrate electrode of a test substrate, an electrical characteristic test of the semiconductor device such as a burn-in test can be performed by a Kelvin contact method without using an IC socket. In addition, although the circuit board is mounted, the electrical characteristic test can be performed with high accuracy by the Kelvin contact method. Such an example of use is particularly useful for testing electrical characteristics of a wafer level CSP having a fine chip electrode array.

  In the test substrate of the present invention, if the substrate electrode and the wiring pattern are formed on the same surface of the insulating substrate, the substrate electrode and the wiring pattern are formed on the front and back surfaces of the insulating substrate. Manufacturing costs can be reduced compared to those.

  Further, a plurality of semiconductor device mounting regions, and a plurality of the substrate electrodes for each of the semiconductor device mounting regions, and the insulating substrate is folded by bending into a region between the adjacent semiconductor device mounting regions of the insulating substrate. If a dividing groove for dividing is provided, an electric characteristic test in a state where the semiconductor device is mounted on a test substrate, for example, a semiconductor device in which a failure occurs during a burn-in test, the dividing groove is used. The insulating substrate can be divided by using and separated from a normal semiconductor device. Then, the electrical characteristic test can be continued for the normal semiconductor device after separating the failed semiconductor device, and the analysis can be performed for the failed semiconductor device.

  In the IC socket of the present invention, a chip housing portion for housing the semiconductor device in a predetermined position, and one end are arranged corresponding to the position of the chip electrode of the semiconductor device when housed in the chip housing portion. Since the test substrate of the present invention having a contact terminal, for example, a pogo pin, and a substrate electrode in contact with the other end of the contact terminal is provided, the wiring path from the test apparatus to the substrate electrode is kelvin. The contact method can be used, and the test can be performed with higher accuracy than when the electrical characteristic test is performed with a single wiring path. Furthermore, since one contact terminal may be brought into contact with the chip electrode, it is technically easier than the case where two contact terminals are brought into contact with the chip electrode, and the manufacturing cost is reduced.

In the IC socket of the present invention, when the semiconductor device to be inspected has a plurality of chip electrodes arranged on one plane, the chip housing portion is a package housing portion for placing the semiconductor device at a predetermined position. And a biasing member for biasing the semiconductor device housed in the package housing portion downward due to weight, and the contact terminal has the chip electrode on the bottom side. If it is arranged corresponding to the position of the chip electrode when accommodated in the package accommodating part,
By biasing the semiconductor device with the weight of the biasing member, a certain amount of applied pressure per single area can be applied. As a result, even if the target of the electrical characteristic test is a small semiconductor device such as a wafer level CSP, it is possible to prevent problems such as damage to the external connection terminals of the semiconductor device, chip chipping, and chip cracking. .

Furthermore, the chip housing portion is temporarily disposed at a position above the package housing portion without contacting the biasing member with the semiconductor device housed in the package housing portion, and then gradually lowered to the semiconductor device. If it is further provided with a biasing member support mechanism to contact,
Rapid pressurization to the semiconductor device can be prevented, and problems such as damage to the external connection terminals of the semiconductor device, chip chipping, and chip cracking can be prevented.

Further, the biasing member support mechanism includes a biasing member support member that displaces the biasing member in a vertical direction or a substantially vertical direction at a position above the package housing portion, and the biasing member to the semiconductor device. The urging member is supported by the upper step when not in contact, and the urging member is supported by an inclined portion inclined downward from the upper step when the urging member is brought into contact with the semiconductor device. Because it is equipped with a slide member that gradually descends,
The biasing member can gradually bias the semiconductor device, prevent sudden pressure on the semiconductor device, and prevent problems such as damage to the external connection terminals, chip chipping, and chip cracking of the semiconductor device. can do.

Furthermore, if the urging member includes a rotating member for reducing friction between the urging member and the slide member at a position corresponding to the slide member,
The biasing member can be smoothly lowered along the inclined portion of the slide member, and friction between the biasing member and the slide member can be reduced to reduce wear of the slide member.

Furthermore, if the urging member support member is arranged in a lid member for covering the package guide member,
When the semiconductor device is accommodated in the package accommodating portion, the urging member support member and the urging member can be excluded from the working range, and work efficiency when accommodating the semiconductor device in the package accommodating portion can be improved. .

The lid fixing member further includes a lid fixing member for fixing the lid member in a state where the lid member covers the package guide member, and the lid fixing member and the slide member are integrated, and the lid fixing member Opens the lid member in a state where the upper step portion of the slide member and the biasing member are in contact with each other, and in a state where the biasing member is in contact with the semiconductor device housed in the package housing portion, If you slide to fix the lid member,
When the urging member is urging the semiconductor device, it is possible to avoid problems such as breakage of the semiconductor device and the urging member due to temporary application of variable pressure such as an external force to the urging member.

  1A and 1B are diagrams showing an embodiment of a test substrate, in which FIG. 1A is a plan view showing the whole, FIG. 1B is an enlarged view of a portion surrounded by a dot-dash line circle position in FIG. ) Is a cross-sectional view taken along the line AA ′ in FIG. 5B, (D) is an enlarged view showing a state in which the wafer level CSP is mounted, and (E) is a cross-sectional view taken along the line BB ′ in FIG. is there. 2A and 2B are views showing a wafer level CSP to be inspected, wherein FIG. 2A is a plan view on the chip electrode side, and FIG. 2B is a side view.

First, the wafer level to be inspected will be described with reference to FIG.
The wafer level CSP1 is a CSP in which a chip electrode 1a is formed on the bottom surface 1b before chip dicing. The wafer level CSP1 has, for example, an outer dimension of 0.82 × 1.32 mm and a thickness of 0.40 mm. Four chip electrodes 1a made of, for example, solder are arranged vertically and horizontally on the bottom surface 1b of the wafer level CSP1. The tip electrode 1a has, for example, a diameter of 0.18 mm and a height of 0.08 mm. The interval between the chip electrodes 1a arranged vertically and horizontally is, for example, 0.50 mm in the width direction and 1.00 mm in the length direction.

The test substrate will be described with reference to FIG.
The test substrate 3 includes an insulating substrate 5 made of, for example, glass epoxy. Four substrate electrodes 7 arranged corresponding to the chip electrode 1a of the wafer level CSP 1 and the substrate electrode 7 are formed on one surface 5a of the insulating substrate 5, and are provided for each substrate electrode 7. Four sets of wiring patterns 9a and 9b, and terminals 11 formed continuously at the opposite ends of the wiring patterns 9a and 9b from the substrate electrodes 7 are formed. The substrate electrode 7, the wiring patterns 9a and 9b, and the terminal 11 are formed by, for example, gold plating on the surface of copper.
Insulating film 13 covering wiring patterns 9a and 9b on one surface 5a of insulating substrate 5 and having openings on substrate electrode 7 and in the vicinity of terminal 11 (illustration in (A) and (D) is omitted) Is formed. The insulating film 13 is made of, for example, an epoxy resin resist.

  As shown in (D) and (E), in the electrical characteristic test of the wafer level CSP1, the wafer level CSP1 is mounted on the test substrate 3 with the chip electrode 1a solder-bonded to the substrate electrode 7. Two wiring patterns 9a and 9b are connected to each substrate electrode 7. Each wiring pattern 9a and 9b is connected to a test apparatus via a terminal 11 and used as a sense line and a force line. As a result, the wiring path from the test apparatus to the substrate electrode 7 can be made in the Kelvin contact method, and the measurement accuracy of the electrical characteristic test is improved without bringing the two contacts into contact with the chip electrode 1a of the wafer level CSP1. Can be made.

  3A and 3B are diagrams showing another embodiment of the test substrate, in which FIG. 3A is a plan view showing the whole, and FIG. 3B is a cross-sectional view at the C-C ′ position in FIG. Parts having the same functions as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

  Two semiconductor device mounting regions are provided on the insulating substrate 5 of the test substrate 15, and the substrate electrode 7, the wiring patterns 9 a and 9 b, and the terminals 11 are provided on one surface 5 a of the insulating substrate 5 for each semiconductor device mounting region. Is formed in the same configuration as the embodiment described with reference to FIG. An insulating film (not shown) is formed on one surface 5a of the insulating substrate 5 so as to cover the wiring patterns 9a and 9b and have openings on the substrate electrode 7 and in the vicinity of the terminals 11.

  Dividing grooves 17 are respectively formed on one surface 5a and back surface 5b of insulating substrate 5 between the two semiconductor device mounting regions. For example, the thickness of the insulating substrate 5 is 1.6 mm, the depth of the dividing groove 17 is 0.5 mm on one side, and the width is 0.2 mm. The thickness of the insulating substrate 5 in the dividing groove 17 is 0.6 mm. . Thus, the insulating substrate 5 can be divided into the semiconductor device mounting regions by bending the insulating substrate 5 with the dividing grooves 17.

  A wafer level CSP is mounted in both semiconductor device mounting regions of the test substrate 15 in the same manner as in FIGS. 1D and 1E, and the two wafer level CSPs are electrically mounted in the state of being mounted on the test substrate 15. A characteristic test is performed. When a failure occurs in any of the wafer level CSPs during the test, for example, during the burn-in test, the insulating substrate 5 can be divided and taken out using the dividing grooves 17. The electrical characteristic test can be continued for the normal wafer level CSP after separating the failed wafer level CSP, and the analysis can be performed for the failed wafer level CSP.

  In this embodiment, two semiconductor device mounting areas are provided on the test substrate 15, but the test substrate of the present invention is not limited to this, and for example, as shown in FIG. 3 may include three semiconductor device mounting regions, or may include four semiconductor device mounting regions in a matrix as shown in FIG. Further, the number of semiconductor device mounting regions, the arrangement direction, and the arrangement direction of the terminals 11 are not limited to these. Moreover, in the aspect provided with the several semiconductor device mounting area | region, the groove | channel for a division | segmentation does not necessarily need to be provided between semiconductor device mounting areas. Further, the dividing grooves may be formed only on one surface of the insulating substrate.

In the above embodiment, the wafer level CSP is a measurement target. However, by changing the size, arrangement, and number of the substrate electrodes 7, a semiconductor device in which a plurality of chip electrodes such as BGA and CSP are arranged in one plane is used. Can respond.
In addition, a semiconductor device having a chip electrode made of a lead terminal such as QFP can be a measurement target.

  5A and 5B are diagrams showing still another embodiment of the test substrate, FIG. 5A is a plan view showing an enlarged semiconductor device mounting region, FIG. 5B is a plan view showing a state in which the QFP is mounted, and FIG. ) Is a cross-sectional view taken along the line DD in (B). Parts having the same functions as those in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed description thereof is omitted.

The QFP test substrate 19 is formed on the one surface 5a of the insulating substrate 5 so as to be continuous with the six substrate electrodes 7 corresponding to the lead terminals (chip electrodes) 21a of the QFP 21 and the substrate electrode 7. 6 sets of wiring patterns 9a and 9b provided for each of the wiring patterns 9a and 9b, and terminals (not shown) formed continuously at the opposite ends of the wiring electrodes 9a and 9b are formed for the wiring patterns 9a and 9b. Has been.
An insulating film 13 (not shown in (A) and (B)) is formed on one surface 5 a of the insulating substrate 5 so as to cover the wiring patterns 9 a and 9 b and to have an opening on the substrate electrode 7. .

  As shown in (B) and (C), in the electrical characteristic test of the wafer level CSP1, the QFP 21 is mounted on the QFP test substrate 19 with the lead terminal 21a solder-bonded to the substrate electrode 7. Also in this embodiment, since two wiring patterns 9a and 9b are connected to each substrate electrode 7, the wiring path from the test apparatus to the substrate electrode 7 can be made a Kelvin contact system, and the lead terminal of the QFP 21 The measurement accuracy of the electrical characteristic test can be improved without bringing the two contacts into contact with 21a.

  5 shows only the semiconductor device mounting area of the QFP test substrate 19, the number of semiconductor device mounting areas provided on the QFP test substrate 19 may be one or more. In the case where a plurality of semiconductor device mounting areas are provided, a dividing groove may be provided between the semiconductor device mounting areas as in FIGS.

Next, an embodiment of the IC socket will be described.
6A and 6B are diagrams showing an embodiment of an IC socket, in which FIG. 6A is a plan view, FIG. 6B is a cross-sectional view taken along the line XX ′ in FIG. It is sectional drawing in a Y 'position.
The IC socket 23 has a substantially rectangular parallelepiped base 25. A space penetrating from the upper surface to the lower surface is formed in the base 25, and a contact terminal support portion 27 is disposed in the space with a gap from the base 25 in the horizontal plane direction so that position adjustment can be performed.
On the side surface of the base 25, an adjustment screw 29 is provided for making a slight adjustment of the position and inclination of the contact terminal support portion 27 in the horizontal plane direction by three-point support for each of two pairs of opposing side surfaces. .
The test substrate 3 is disposed on the upper surface of the contact terminal support portion 27, and the pogo pin support portion 31 is disposed thereon. The test substrate 3 is the same as shown in FIGS. 1A, 1B and 1C, for example.

7A and 7B are enlarged views showing the structure in the vicinity of the test substrate 3 and the pogo pin support 31. FIG. 7A is a plan view, and FIG. . In (A), illustration of the positioning guide 37 is omitted.
The test substrate 3 is disposed on the contact terminal support portion 27. On one surface 5a of the insulating substrate 5 of the test substrate 3, four substrate electrodes 7 corresponding to the chip electrode 1a (see FIG. 2) of the wafer level CSP 1 to be measured are formed in succession. The four wiring patterns 9a, 9b provided for each substrate electrode 7 and terminals (not shown) formed continuously at the opposite ends of the wiring patterns 9a, 9b from the substrate electrodes are the wiring patterns 9a. , 9b. These terminals are connected to a test apparatus provided outside the IC socket 23 by wiring (not shown).
A pogo pin support 31 made of an insulating material is disposed on the test substrate 3. A pogo pin arrangement hole 31 a is formed in the pogo pin support portion 31 corresponding to the substrate electrode 7 of the test substrate 3. A pogo pin 33 as an example of a contact terminal is arranged in the pogo pin arrangement hole 31a.

Returning to FIG. 6, the description of the IC socket will be continued.
A cover chassis 35 is provided on the upper surface of the base 25 so as to cover the contact terminal support portion 27. The cover chassis 35 has an opening at the center, and a positioning guide (package guide member) 37 is disposed in the opening.

FIG. 8 is a perspective view showing a positioning guide. The positioning guide 37 will be described with reference to FIG.
A recess 39 is formed in the positioning guide 37. At the bottom of the recess 39, a package housing portion 41 is formed which is a recess having a planar shape slightly larger than the external dimension of the wafer level CSP1 (see FIG. 2) to be measured. Process reliefs are formed at the four corners of the planar shape of the package housing portion 41. A through hole 41 a is formed at the bottom of the package housing portion 41 corresponding to the arrangement of the chip electrodes 1 a and the pogo pins 33 of the wafer level CSP 1.

In this embodiment, for example, four through holes 41a are formed in the package accommodating portion 41, and the dimensions of the package accommodating portion 41 excluding machining relief are 1.50 mm in length, 1.00 mm in width, and depth in depth. The thickness of the bottom hole is 0.60 mm, and the through hole 41a has a diameter of 0.35 mm.
Examples of the material of the positioning guide 37 include zirconia-based ceramics. However, in the present invention, the shape, material, size, function, and the like of the package guide member are not limited to the positioning guide 37.

FIG. 9 is an enlarged perspective view showing the package housing portion.
The package housing unit 41 positions the horizontal plane position and the vertical position of the wafer level CSP to be measured.
Pogo pins 33 are arranged at positions below the package housing portion 41 corresponding to the arrangement of the through holes 41a and the chip electrodes 1a of the wafer level CSP1. The tip of the pogo pin 33 is disposed in the through hole 41a (see also FIG. 7B).

  The cover chassis 35 has openings corresponding to the four corners of the contact terminal support 27, and screw holes are formed in the four corners of the contact terminal support 27 corresponding to the openings. Yes. A fixing screw 43 is screwed into a screw hole of the contact terminal support 27 through the opening of the cover chassis 35, and the contact terminal support 27 is fixed to the cover chassis 35. The opening of the cover chassis 35 is formed with a size smaller than the diameter of the screw portion of the fixing screw 43 and larger than the head of the fixing screw 43, and is positioned by the adjusting screw 29 by the fixing screw 43. The adjusted contact terminal support 27 can be fixed at the adjusted position. Thereby, after adjusting the position of the contact terminal support 27 with the adjustment screw 29, it is possible to prevent the position of the contact terminal support 27 from being moved after the position adjustment. Further, after the position of the contact terminal support 27 is fixed with the fixing screw 43, it is not necessary to continue positioning the contact terminal support 27 with the adjustment screw 29. Therefore, the adjustment screw 29 is removed or loosened. The pressure of the adjustment screw 29 against the contact terminal support 27 can be eliminated or loosened. When using the IC socket 23, the adjusting screw 29 may be removed.

Returning to FIG. 6, the description of the IC socket will be continued.
A shaft support 45 is fixed to the upper surface of the cover chassis 35. The shaft support 45 is provided with a shaft 47 parallel to the horizontal plane.
A cover (lid member) 49 and a weight 51 are provided so as to rotate about the shaft 47. FIG. 6 shows a state in which the cover 49 is closed. FIG. 10 shows a state where the cover 49 is opened.
The cover 49 and the weight 51 have the shaft 47 as a common rotation axis, but are not fixed to each other and are attached to the shaft 47 so that they can rotate independently. The weight 51 is disposed inside the cover 49, and the lowering width when the cover 49 is closed is limited by the lowering width adjusting screw 55 attached to the cover 49.
The cover 49 is fixed to the shaft 47, and a hydraulic damper 53 for limiting the opening / closing speed of the shaft 47 and the cover 49 is provided at one end of the shaft 47. The hydraulic damper 53 prevents the wafer level CSP1 from jumping out of the package housing portion 41 due to the cover 49 being rapidly closed and the IC socket 23 being vibrated. The mechanism for limiting the opening and closing speed of the cover 49 is not limited to the hydraulic damper 53, and may be another mechanism.

  The weight 51 is provided with a pressure head 57 at a position corresponding to the package housing portion 41. The pressure head 57 is for urging the surface opposite to the surface on which the chip electrodes of the wafer level CSP arranged in the package housing portion 41 are arranged downward. A resin ball member is provided at the tip of the pressure head 57, and the ball member contacts the wafer level CSP. An elastic body, for example, a winding spring, is accommodated in the pressure head 57. The winding spring contracts to prevent destruction of the wafer level CSP and adjusts the pressing pressure to a certain level or more.

In the weight 51, a ball member 59 is disposed on the lower surface on the end side opposite to the shaft 47. The weight 51, the pressure head 57, and the ball member 59 constitute an urging member of the IC socket of the present invention.
A cover fixing member (lid fixing member) 61 is also arranged on the upper surface of the cover chassis 35 on the opposite side of the shaft support 45 with the positioning guide 37 interposed therebetween. A long hole 63 is formed in the cover fixing member 61 in parallel with the shaft 47. A pin 65 fixed to the cover chassis 35 is disposed in the long hole 63. The cover fixing member 61 is arranged to be slidable parallel to the shaft 47 in the horizontal plane with the elongated hole 63 as a guide.

FIG. 11 is an enlarged plan view around the cover fixing member 61. (A) shows a state where the cover 49 is fixed, and (B) shows a state where the cover 49 is not fixed. In FIG. 6A, the position indicated by the solid line of the cover fixing member 61 indicates a state where the cover 49 is fixed, and the position indicated by a two-dot chain line indicates a state where the cover 49 is not fixed.
The cover fixing member 61 is provided with a protrusion 61a. The cover 49 has a recess 49a and a step 49b corresponding to the protrusion 61a.

When the cover 49 is closed, as shown in FIG. 11B, the cover fixing member 61 is positioned so that the protrusion 61a of the cover fixing member 61 is disposed at a position corresponding to the concave portion 49a of the cover 49 (cover opening). position).
After the cover 49 is closed, as shown in FIG. 11A, the cover fixing member 61 is slid so that the projection 61a of the cover fixing member 61 is positioned on the stepped portion 49b of the cover 49 (cover fixing position). .
In this way, the cover 49 is fixed by the cover fixing member 61.

  When the cover 49 is open and the cover fixing member 61 is positioned at the cover fixing position (see FIG. 11A), the stepped portion 29 of the cover 49 is fixed to the cover 49 even if the cover 49 is closed. The cover 49 does not close by contacting the protrusion 61a of the member 61. Thereby, it is possible to prevent an excessive force from acting on the wafer level CSP arranged in the package housing portion 41 by mistake.

  FIG. 12 is an enlarged view showing a cross section at the position F-F ′ in FIG. As shown in FIG. 12, the cover fixing member 61 is provided with a ball contact base (sliding member) 67 at a position corresponding to the ball member 59 of the weight 51. The ball contact base 67 includes an upper step portion 67a, an inclined portion 67b inclined downward from the upper step portion 67a, and a lower step portion 67c provided at a position lower than the upper step portion 67a continuously to the inclined portion 67b. Is formed.

In this embodiment, the base 25, the cover chassis 35, the positioning guide 37, the shaft support 45, the shaft 47, the cover 49, the weight 51, the hydraulic damper 53, the lowering adjustment screw 55, the pressure head 57, the ball member 59, the cover The fixing member 61 and the pin 65 constitute a chip housing portion of the IC socket of the present invention.
Further, the shaft 47 and the lowered width adjusting screw 55 constitute an urging member supporting member of the IC socket of the present invention, and an urging member supporting member comprising the shaft 47 and the lowered width adjusting screw 55 and a ball contact base (sliding member) 67. Constitutes an urging member supporting mechanism of the IC socket of the present invention.

Next, the position adjustment operation of the pogo pin 33 and the through hole 41a of the package housing part 41 will be described. The wiring unit will be described.
After the adjustment screw 29 is screwed into the base 25 so that the contact terminal support 27 can be supported by the adjustment screw 29, the fixing screw 43 is loosened. The probe unit is arranged on a microscope having a length measuring function, and the adjustment screw 29 is rotated while checking with the microscope to move the contact terminal support 27, and the tip of the pogo pin 33 is moved to a predetermined position. After the adjustment of the tip of the pogo pin 33 is completed, the fixing screw 43 is tightened to fix the position of the contact terminal support portion 27. At this time, it is preferable to tighten the fixing screw 43 while confirming whether or not the tip position of the pogo pin 33 is displaced with a microscope.

Next, an operation when accommodating the wafer level CSP1 to be measured in the IC socket 23 will be described.
As shown in FIG. 10, the cover 49 is opened, the wafer level CSP is accommodated in the package accommodating portion 41, and then the cover 49 is closed. 11B and FIG. 12, when the cover fixing member 61 is disposed at the cover open position and the cover 49 is not fixed, the upper stage portion 67a of the ball contact base 67 is a weight. 51, the ball member 59 is in contact with the upper step portion 67a.

FIG. 13 shows a cross-sectional view in a state where the cover 49 is closed and the cover fixing member 61 does not fix the cover 49 at the XX position in FIG.
In this state, the ball member 59 of the weight 51 is in contact with the upper step portion 67a of the ball contact base 67 (see also the two-dot chain line in FIG. 11), and the weight 51 is supported by the upper step portion 67a and the shaft 47. . At this time, the tip of the pressure head 57 is not in contact with the wafer level CSP accommodated in the package accommodating part 41.

  When the cover fixing member 61 is slid from the cover open position shown in FIG. 11 (B) to the cover fixing position side shown in FIG. 11 (A), the ball member 59 of the weight 51 rotates on the ball contact table 67, The upper stage portion 67a on the contact base 67 sequentially contacts the inclined portion 67b, and the position of the ball member 59 in the vertical direction is gradually lowered. Along with this, the weight 51 and the pressure head 57 are also gradually lowered, the pressure head 57 comes into contact with the wafer level CSP accommodated in the package accommodating portion 41, and the wafer level CSP is gradually pressurized downward. The weight of the weight 51 is adjusted to an appropriate size, and by gradually pressurizing with the weight of the weight 51, the occurrence of defects such as damage to the chip electrode of the wafer level CSP, chip chipping and chip cracking can be prevented. Can do.

  In a state where the cover fixing member 61 is located at the cover fixing position, the weight 51 is supported by the shaft 47, the lowered position adjusting screw 33 and the wafer level CSP, and the wafer level CSP is pressurized by the pressure head 57 with an appropriate pressure. At this time, the amount by which the wafer level CSP is pushed down is limited by the bottom surface of the package housing portion 41. Thereby, the chip electrode of the wafer level CSP and the pogo pin 33 of the contact unit 11 are electrically connected with a good contact state.

  After the wafer level CSP electrical characteristic test is performed, when the wafer level CSP is taken out from the package housing 41, the cover is fixed from the cover fixing position shown in FIG. 11A to the cover opening position shown in FIG. 11B. The member 61 is slid. As a result, the ball member 59 of the weight 51 sequentially contacts the upper step portion 67a from the inclined portion 67b of the ball contact base 67, the weight 51 rises and the pressure head 57 also rises, and the wafer level CSP is released from the pressure state. Is done. Thereafter, the cover 49 is opened, and the wafer level CSP is taken out from the package housing portion 41.

In the embodiment of the positioning guide and IC socket described above, the wafer level CSP shown in FIG. 5 is the measurement object, but the semiconductor device to be measured by the present invention is not limited to this, and the package accommodation It can be applied to various semiconductor devices by changing the size of the portion and the arrangement of contact terminals and substrate electrodes, for example, BGA, CSP and QFP.
Further, the configuration of the chip housing portion is not limited to the above embodiment, and the semiconductor device is housed in a predetermined position so that the chip electrode of the semiconductor device is brought into contact with the substrate electrode of the wiring board via the contact terminal. Any configuration is possible as long as it can be performed.
In the above embodiment, the pogo pin is used as the contact terminal. However, the present invention is not limited to this, and other contact terminals such as those made of an electrically conductive material having elasticity such as a probe needle. It may be.

In addition, as shown in FIG. 14, one or a plurality of IC socket portions 69 may be provided on the test substrate 3. In this embodiment, the test substrate 3 is formed so that the planar dimension of the insulating substrate 5 (see FIG. 1) is larger than that of the embodiment described with reference to FIG. The pogo pins 33 are aligned and the IC socket part 69 is fixed on the insulating substrate 5. The IC socket portion 69 has the same structure as the IC socket 23 described with reference to FIGS. However, the IC socket portion 69 does not include the contact terminal support portion 27 and the adjustment screw 29 with respect to the IC socket 23.
The IC socket portion disposed on the test substrate of the present invention is not limited to the IC socket portion 69, and a contact terminal such as a pogo pin can be disposed on the substrate electrode of the test substrate, and the contact terminal As long as the semiconductor device can be accommodated while contacting the chip electrode of the semiconductor device, the IC socket portion having any configuration may be used.

  The embodiment of the present invention has been described above, but the present invention is not limited to this, and the shape, material, arrangement, dimensions, etc. are examples, and are within the scope of the present invention described in the claims. Various changes can be made.

BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows one Example of the board | substrate for a test, (A) is a top view showing the whole, (B) is an enlarged view of the part enclosed by the dashed-dotted line circle position of (A), (C) is ( (B) is a cross-sectional view at the position AA ′, (D) is an enlarged view showing a state in which the wafer level CSP is mounted, and (E) is a cross-sectional view at the position BB ′ in (D). It is a figure which shows wafer level CSP which is a test object, (A) is a top view by the side of a chip electrode, (B) is a side view. It is a figure which shows the other Example of the board | substrate for a test, (A) is a top view showing the whole, (B) is sectional drawing in the C-C 'position of (A). It is a figure which shows the further another Example of the board | substrate for a test. It is a figure which shows the further another Example of the board | substrate for a test, (A) is a top view which expands and shows a semiconductor device mounting area, (B) is a top view which shows the state which mounted QFP, (C) is ( It is sectional drawing in the DD 'position of B). It is a figure which shows one Example of IC socket, (A) is a top view, (B) is sectional drawing in the XX 'position of (A), (C) is the YY' position of (A). FIG. It is a figure which expands and shows the structure of the test substrate which comprises the Example, and the pogo pin support part vicinity, (A) is a top view, (B) is sectional drawing in the EE 'position of (A). is there. It is a perspective view which shows an example of the positioning guide which comprises the Example. The perspective view which expands and shows the package accommodating part which comprises the Example is shown. It is sectional drawing which shows the state which the cover of the Example opened. It is a top view which shows the periphery of the cover fixing member which comprises the Example, (A) is the state which is fixing the cover, (B) shows the state which is not fixing the cover. It is a figure which expands and shows the cross section in the F-F 'position of FIG. 1 (A). It is sectional drawing which shows the state which closed the cover in the Example and the cover fixing member has not fixed the cover. It is sectional drawing which shows the further another Example of the board | substrate for a test.

Explanation of symbols

1 Wafer level CSP
DESCRIPTION OF SYMBOLS 1a Chip electrode 1b Bottom surface 3 Test substrate 5 Insulating substrate 5a One surface of insulating substrate 5b Back surface of insulating substrate 7 Substrate electrode 9a, 9b Wiring pattern 11 Terminal 13 Insulating film 15 Test substrate 17 Dividing groove 19 QFP test Substrate 21 QFP
21a Lead terminal (chip electrode)
23 IC socket 25 Base 27 Contact terminal support portion 29 Adjustment screw 31 Pogo pin support portion 31a Pogo pin placement hole 33 Pogo pin 35 Cover chassis 37 Positioning guide 39 Recess 41 Package housing portion 41a Through hole 43 Fixing screw 45 Shaft support base 47 Shaft 49 Cover 51 Weight 53 Hydraulic damper 55 Lowering adjustment screw 57 Pressure head 59 Ball member 61 Cover fixing member 63 Long hole 65 Pin 67 Ball contact base 69 IC socket part

Claims (11)

  An insulating substrate, a substrate electrode formed on the insulating substrate, to which a chip electrode of the semiconductor device is electrically connected directly or via a conductive material, and at least two connected to the substrate electrode separately from each other A test board equipped with a wiring pattern.   The test substrate according to claim 1, wherein the substrate electrode and the wiring pattern are formed on the same surface of the insulating substrate.   A plurality of semiconductor device mounting regions and a plurality of the substrate electrodes for each of the semiconductor device mounting regions, and the insulating substrate is divided by bending into regions between adjacent semiconductor device mounting regions of the insulating substrate. The test substrate according to claim 1, further comprising a dividing groove.   A chip accommodating portion for accommodating the semiconductor device in a predetermined position; a contact terminal having one end arranged corresponding to the position of the chip electrode of the semiconductor device when accommodated in the chip accommodating portion; and the contact An IC socket comprising the test substrate according to claim 1, further comprising a substrate electrode in contact with the other end of the terminal for use.   The IC socket according to claim 4, wherein the contact terminal is a pogo pin. A semiconductor device to be inspected has a plurality of chip electrodes arranged in one plane,
The chip housing portion includes a package guide member having a package housing portion for placing the semiconductor device at a predetermined position, and an attachment for biasing the semiconductor device housed in the package housing portion downward by weight. A force member,
6. The IC socket according to claim 4, wherein the contact terminal is disposed corresponding to a position of the chip electrode when the semiconductor device is housed in the package housing portion with the chip electrode facing down.   The chip housing portion temporarily disposes the biasing member in a position above the package housing portion without contacting the semiconductor device housed in the package housing portion, and then lowers the biasing member to contact the semiconductor device. The IC socket according to claim 6, further comprising a biasing member support mechanism.   The urging member support mechanism does not allow the urging member to contact the semiconductor device, and the urging member support member that disposes the urging member so as to be movable in a vertical direction or a substantially vertical direction above the package housing portion. In the state, the urging member is supported by the upper stage, and when the urging member is brought into contact with the semiconductor device, the urging member is gradually supported by being supported by the inclined part inclined downward from the upper stage. The IC socket according to claim 7, further comprising a slide member to be lowered.   The IC socket according to claim 8, wherein the urging member includes a rotating member for reducing friction between the urging member and the slide member at a position corresponding to the slide member.   The IC socket according to claim 8 or 9, wherein the urging member support member is disposed in a lid member for covering the package guide member.   A lid fixing member for fixing the lid member in a state where the lid member covers the package guide member; the lid fixing member and the slide member are integrated; The lid member is opened when the upper stage portion of the slide member and the biasing member are in contact with each other, and the lid member is opened when the semiconductor device accommodated in the package housing portion and the biasing member are in contact with each other. The IC socket according to claim 10, which is slid so as to be fixed.

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