JP2884780B2 - TAB type semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a TAB (Tape Automated Bonding; TAPE AUTOMA).
TED BONDING) type semiconductor device,
The present invention relates to a structure of a TAB type semiconductor device that can easily detect that a power supply wiring has an open defect.

[0002]

2. Description of the Related Art As shown in a plan view of FIG. 3, a general TAB type semiconductor device has leads 2 provided on a carrier tape 1 and bumps 4 provided on electrodes on an IC chip 3.
Are formed by aligning a tip portion (inner lead bonding portion; hereinafter, referred to as an ILB portion) 5 of the lead with the bump 4 and bonding by a method such as thermocompression bonding.

Normally, the tip (ILB portion) 5 of the lead is
Bonding to the bumps 4 of the C chip 3 is called inner lead bonding.

In the above-described TAB type semiconductor device, the opposite side of the ILB portion 5 is formed as a conductive pattern on a carrier tape, and the end portion is a measurement electrode group 6 for measuring the electrical characteristics of the semiconductor device. .

When the TAB type semiconductor device having the above-described structure is actually mounted, the leads 2 are cut within the holes 7 of the carrier tape 1 so that the outer lead bonding portion (outside the IC chip) is cut. A protruding portion, hereinafter referred to as an OLB portion) 8 is bonded to a substrate such as a printed wiring board. This is usually called outer lead bonding.

In the TAB type semiconductor device, since the OLB portion 8 drawn from the IC chip is directly bonded to the substrate, a general wire bonding type semiconductor device or the like is used in terms of high-density mounting and heat dissipation of the IC chip with large power consumption. It has the feature that it is more advantageous than.

By the way, in general, when the power consumption of the IC chip becomes large, it is necessary to make the lead thicker due to the limitation of the allowable current of the lead drawn out.

In this case, it is particularly necessary to increase the thickness of the leads on the ground and supply sides of the power supply.

However, if only some of the leads in the IC chip are made thicker, the temperature and pressure bonding time during inner lead bonding and outer lead bonding differ depending on the leads, and thus the characteristics of the TAB type semiconductor device. One of the problems is that batch bonding cannot be performed.

Therefore, when the allowable current is exceeded, it is common practice to increase the number of leads instead of making the leads thicker.

In the measurement electrode group 6 in the plan view of the TAB type semiconductor device shown in FIG. 3, the measurement electrodes G _{AO to} G _DO and the measurement electrodes V _{AO to} V _DO are provided with a plurality of leads as described above. Is shown.

FIG. 4 is a schematic plan view of the plan view of FIG. 3, in which an IC chip of a conventional TAB type semiconductor device is applied to the IC chip 3 to show an electrical connection state. The state described above means that the circuit in the IC chip 3 is divided into circuits A, B, C and D in FIG. 4 and a power supply current is supplied from an external power supply 9 to each circuit.

[0013]

In a TAB type semiconductor device, a test is performed as to whether or not the function is satisfied while being mounted on a carrier tape.

The test detects an IC chip that does not satisfy its function due to a defect in an electric circuit in the IC chip or a defect in the inner lead bonding.

In this case, not only the defective IC chip is detected by the function test, but also the distinction between the defective circuit in the IC chip and the defective inner lead bonding is necessary for the improvement of the subsequent defect. Is important.

Particularly, in recent TAB type semiconductor devices, the number of pins tends to increase, so it is important to reliably detect an open defect in inner lead bonding and feed it back to design and manufacture.

However, in the conventional TAB semiconductor device, it is not possible to distinguish between an open defect of the inner lead bonding and a defective circuit in the IC chip.

The description is given below. Now, in FIG. 4, it is assumed that there is an open defect 10 in the inner lead bonding in the ground electrode _GDI .

In this case, the circuit D does not operate. Therefore,
In a functional test in which a power supply voltage is applied from an external power supply 9, a specified input signal is input to the input terminal 11, and a specified output signal is output to the output terminal 12, this IC chip is defective. .

However, since a current is supplied to the ground terminal GND, it is difficult to identify an open defect of the inner lead bonding at the ground electrode _GDI .

As a test of the electrical characteristics of the IC chip, since a DC parametric test of each terminal is performed in addition to the function test, it is easy to detect the open state of the input terminal 11 and the output terminal 12. Even if Figure 4
It is difficult to determine when the ground electrodes G _{AI to} G _DI provided in parallel are finally integrated as the ground terminal GND as shown in FIG.

On the other hand, in FIG. 4, the ground electrodes G _{AI to} G _DI are integrated into the ground terminal GND. However, if the continuity check is performed using the measurement electrodes G _{AO to} G _DO without integrating them, the inner lead is used. Opening failure of bonding can be detected, but in this case, it is necessary to separately perform a functional test to which power is applied, which increases the number of manufacturing steps.

Also, by observing with a microscope or the like, it is possible to detect a lead that has not been normally subjected to inner lead bonding. However, when the number of pins is extremely large as in a recent TAB type semiconductor device, However, this method is not practical because the number of steps significantly increases.

[0024]

A TAB type semiconductor device according to the present invention is connected to the power supply lead in a TAB type semiconductor device comprising a carrier tape including a plurality of power supply leads provided in parallel and an IC chip. A resistor is provided for each wire in the IC chip, and the resistor has an end connected to the wire in the IC chip and the other end connected to another lead provided on the carrier tape. , And have the same shape.

[0025]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a schematic plan view showing a first embodiment of the present invention.

The present embodiment is different from the conventional TAB type semiconductor device shown in FIG.

In this embodiment, when the ground electrodes G _{AI to} G _DI are provided corresponding to the circuits A, B, C and D in the IC chip 13, the resistors _{RGA to} R _GD are connected to the respective ground electrodes.
Is connected. The other end of each resistor is connected to a measurement electrode E _O on the carrier tape via an electrode E _I separately provided on the IC chip 13.

The lead 2 for each of the ground electrodes, the inner · ILB portion 5 of the tip in a portion of the ground electrode G _AI ~G _DI
Lead-bonded and the other ends measured electrodes G _{AO to} G _DO
Through a ground terminal GND.

The power supply also has a resistor R _VA similar to the ground side.
To R _VD are provided, each resistor has one end connected to a respective power electrodes V _AI ~V _DI, is connected to the measuring electrode F _O on the carrier tape and the other end via the electrode F _I for measurement ing.

The lead 2 for each of the power supply electrodes, inner is ILB portion 5 of the tip portions of the power supply electrode V _AI ~V _DI
Lead-bonded and the other ends measured electrodes V _{AO to} V _DO
Through a power supply terminal VEE.

A case where the characteristics between terminals are measured with the above configuration will be considered. Now, the resistance value of each resistor in FIG. 1 R _GA = R
_GB = R _GC = R _GD = 1 kΩ, R _VA = R _VB = R _VC = R _VD = 1
kΩ between the ground terminal GND and the measurement electrode E _O.
Then was applied 1V, ground current I _G flowing to the ground terminal GND, the _{I G = 0.1 ÷ (1/4)} = 0.4mA.

Similarly, when 0.1 V is applied between the power supply terminal VEE and the measurement electrode F _O and the power supply current I _V flowing through the power supply terminal VEE is measured, it becomes 0.4 mA.

[0033] Here, for example, if the inner lead bonding in the ground electrode G _DI is open,
The aforementioned current I _G is 0.3 mA. Therefore, one of the ground electrodes G _AI ~G _DI is set to limit the I _G> 0.35 mA as the inspection standard can be determined that an open.

[0034] However, variation in the resistance value of the semiconductor integrated circuit, since there is about ± 20%, will be varied between I _G = 0.32~0.48mA as the value of the current I _G, above The inspection standard is I _G > 0.35m
In the determination of the absolute value of A, there may be cases where the determination cannot be made correctly.

It is well known that in a semiconductor integrated circuit, when resistors are formed in the same shape in the same chip, the absolute values of the resistors vary, but the relative variation between the resistors is small. is there.

[0036] Therefore, seek resistance R _G from the measured ground current I _G, also in the power source current I _V obtains the resistance value R _V, both in agreement within the allowable variation (e.g. ± 5%) By determining whether or not the inner lead bonding is open, it is possible to correctly determine whether or not the inner lead bonding is open.

Next, a second embodiment of the present invention will be described. FIG. 2 is a schematic plan view showing a second embodiment of the present invention.

The present embodiment differs from the first embodiment shown in FIG. 1 in the portion of the resistor _RGA connected to the ground electrode G _AI on the IC chip 14.

In this embodiment, one end of the resistor _RGA is connected to the ground electrode G _AI on the IC chip 14, and the other end is connected to the electrode H _I in the IC chip 14 via a lead that is inner lead bonded. Measuring electrode H _O on the carrier tape
It is connected to the.

In this embodiment, in order to determine the open defect of the inner lead bonding, first, the resistance _RGA is obtained from the characteristics between the measurement electrode H _O on the carrier tape and the ground terminal GND.

Next, from the characteristics between the measurement electrode E _O and the ground terminal GND, the value of the resistance R connected to the measurement electrode E _O is calculated.
_G is obtained, and similarly, from the characteristics between the measurement electrode F _O and the power supply terminal VEE, the value R _V of the resistance connected to the measurement electrode F _O is obtained, and the two resistances are relatively compared.

In this case, in this embodiment, since one resistance value is obtained first and this is used as a comparison reference, the judgment accuracy is improved.

The arithmetic processing required for the above determination can be easily realized by the current characteristic test apparatus.

[0044]

As described above, according to the present invention,
By adding several resistors and leads to a TAB type semiconductor device having a plurality of power leads having the same function,
It is possible to provide a TAB type semiconductor device capable of easily and reliably detecting an open failure in inner lead bonding of a power supply lead.

[Brief description of the drawings]

FIG. 1 is a schematic plan view showing a first embodiment of the present invention.

FIG. 2 is a schematic plan view showing a second embodiment of the present invention.

FIG. 3 is a plan view of a TAB type semiconductor device.

FIG. 4 is a schematic plan view of a conventional TAB type semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Carrier tape 2 Lead 3, 13, 14 IC chip 4 Bump 5 ILB part 6 Measurement electrode group 7 Hole 8 OLB part 9 Power supply 10 Open defect 11 Input terminal 12 Output terminal

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/60 311 H01L 21/66 H01L 21/60 321 G01R 31/28 G01R 31/26

Claims (1)

(57) [Claims] In a TAB type semiconductor device including a carrier tape including a plurality of power supply leads provided in parallel and an IC chip, a resistor is provided for each wiring in the IC chip connected to the power supply lead. Has one end connected to wiring in the IC chip, and the other end connected to an electrode in the IC chip connected to another lead provided on the carrier tape, and has the same shape. TAB semiconductor device.