JP4577839B2 - Electronic device using package having solder balls, and method for detecting abnormal state of package having solder balls - Google Patents

Description

  The present invention relates to various electronic devices including a personal computer (PC), and more particularly to an electronic device mounted with a package substrate on which solder balls are arranged.

  In recent years, electronic devices such as notebook PCs and desktop PCs have widely used package substrates as their main components. The package substrate is a printed circuit board represented by a small electronic component such as a BGA (Ball Grid Array) package or a CSP (Chip Size Package). These include an LSI (Large Scale Integrated circuit) and have a function of electrically connecting the silicon chip and the outside of the LSI. This BGA package is one of integrated circuit (IC) packages, and input / output pads are arranged on the back surface of the package, and are widely used for surface mounting of multi-pin ICs. Wire bonding or flip chip is used for connection between the IC chip and the substrate in the BGA package. The connection to the printed circuit board is made by solder ball electrodes arranged in a two-dimensional lattice pattern. On the other hand, the CSP is an ultra-small package that realizes almost the same size as an IC chip with the same basic structure as a BGA package. And this is arrange | positioned at a two-dimensional lattice form, and a connection with a printed circuit board is made.

  As a conventional technique described in the publication, for example, there is a BGA substrate mounted with a BGA package, in which the inner periphery of a BGA substrate that is vulnerable to temperature stress is connected and connected to a constant current circuit and a voltage monitoring circuit. To do. The quality of the BGA junction is determined by the wiring connecting the BGA substrate, the BGA, and the BGA receiving substrate, the constant current circuit supplying a constant current to the wiring, and the voltage monitoring circuit. Is constantly monitored (see, for example, Patent Document 1). In addition, a technique for inspecting a connection failure between a solder ball arranged at a corner portion of a BGA / CSP type electronic component which is a rectangular (square shape) package and a solder connection pad provided at each corner portion of a printed wiring board. (For example, refer to Patent Document 2). Here, when mechanical stress is applied to a BGA / CSP type electronic component in an actual use environment, a poor contact between the corner portion and the physical connection between the BGA / CSP type electronic component and the printed wiring is likely to occur. Is detected.

JP 2002-76187 A (page 3, FIG. 1) JP 2001-244359 A (page 6, FIG. 1)

  Thus, the package substrate using the solder ball, which is a BGA / CSP type electronic component, is weaker in strength than other packages against stress such as bending. For this reason, if excessive stress is applied to the substrate, the solder balls are cracked, resulting in poor conduction, and system operation abnormalities. With respect to the problem of the package substrate using such solder balls, it is possible to grasp the connection state of the BGA junction by using the techniques described in Patent Document 1 and Patent Document 2. However, for example, in the technique described in Patent Document 1, the inner peripheral portion of the BGA substrate, which is the most important region for mounting LSI, is secured for inspection. For this reason, this technique is difficult to realize in a normal use state unless special substrate specifications can be adopted, and is not preferable in practice.

  Moreover, in the said patent document 1 and the patent document 2, as shown in FIG. 11, the method of connecting a solder ball in a chain shape is employ | adopted. A system board 200 shown in FIG. 11 includes a BGA package 201 and a BGA receiving board 204. The BGA package 201 is configured such that solder balls 203 are arranged on a BGA substrate 202, and the BGA substrate 202 can be connected to the BGA receiving substrate 204 via the solder balls 203. Further, a connection pattern 206 is provided on the BGA receiving substrate 204, and a connection pattern 205 is also provided on the BGA substrate 202. In the example shown in FIG. 11, a daisy chain is formed by these connection patterns 205 and 206 and the solder balls 203. In Patent Document 1 and Patent Document 2 described above, a loop of a plurality of solder balls 203 is formed using such a daisy chain, and the continuity of both ends thereof is confirmed, thereby realizing the inspection of the plurality of solder balls 203. ing.

  However, although Patent Document 1 and Patent Document 2 describe a substrate to be inspected and a mounting form, they do not mention a specific defect recognition method or software processing of the recognition result. For this reason, for example, a technique necessary for recognizing a defect in an electronic device such as a notebook PC remains unsolved. In other words, what is most problematic in the market is what kind of usage the solder ball cracked in the actual usage environment, but in the prior art, it occurred when mounted on an electronic device. It is difficult to monitor abnormal conditions.

The present invention has been made in order to solve the technical problems as described above. The object of the present invention is to make a package using solder balls such as a BGA package and a CSP mounted on a device. Thus, the defect is to be recognized well when the solder ball is cracked.
Another object is to identify the location of a crack or the like for a defect caused by a crack in a solder ball in a state where it is mounted on an apparatus.
Still another object of the present invention is to store the crack status in a memory and use it as a history for a defect caused by a crack in a solder ball in a state where it is mounted on a device.
It is still another object of the present invention to detect failures early and shorten the solution time in the operating state of an apparatus on which a package using solder balls is mounted.

  For this purpose, the present invention is an electronic device on which a package having a solder ball such as a BGA package or a CSP is mounted, monitors the state of a plurality of solder balls selected from the solder balls, and The circuit includes a circuit for identifying a solder ball in which an abnormality has occurred from among the balls, and a conductive member that connects each of the plurality of solder balls to the circuit.

  Here, the solder balls in a plurality of locations of the package can be characterized in that they are solder balls in a plurality of corner regions of the package. In general, since the corner area of the package is rarely used as an LSI signal terminal, it is easy to incorporate inspection wiring. The corner area of the package is the place where the solder ball is most likely to crack. Therefore, it is preferable to detect an abnormal state in the corner area of the package.

In addition, the circuit detects an abnormality in at least one of the plurality of solder balls, and detects an abnormal point individually based on an instruction from the system side that controls the electronic device. And a selector circuit for detection.
Further, this circuit can be characterized by comprising a latch circuit that holds the state when a potential change with respect to the solder ball occurs.

The plurality of solder balls may be connected to a ground (GND) layer included in the package.
Further, the plurality of solder balls may be connected to a power source (VDD). This power supply (VDD) connection can be characterized by being connected to a power supply (VDD) layer of this package.

  From another viewpoint, the present invention is an electronic device on which a system board formed by a package in which solder balls are arranged and a receiving board of the package is mounted, and is connected to the solder balls in the corner area of the package. A wiring connected to the wiring for monitoring the state of the solder ball in the corner area, a CPU connected to the circuit for recognizing the abnormality of the solder ball, and information relating to the abnormality recognized by the CPU And a memory to be used.

  Here, in this wiring, a plurality of solder balls in the corner region form a daisy chain by the receiving substrate and the substrate forming the package, and this circuit is one of the plurality of solder balls forming the daisy chain. It can be characterized in that a crack is detected from the output level of the system board.

  In addition, the CPU may identify an abnormal solder ball from the circuit, and the memory may store information on the identified solder ball as a history.

On the other hand, the present invention is an abnormal state detection method for detecting an abnormality occurring in a solder ball in an electronic device in which a package using the solder ball is mounted, and the abnormal state occurring in the solder ball in the corner area of the package is detected. Detecting using a detection circuit, transmitting the detected abnormal state from the detection circuit to the system controlling the electronic device, and storing information on the detected abnormal state in the memory on this system side Can do.
Here, the system side is further characterized in that the location of the solder ball in an abnormal state is specified using a detection circuit.

  Further, one end of the solder ball in the corner region is connected to ground (GND) and the other end is connected to a current source by the substrate forming the package and the receiving substrate of the package, and the potential between the one end and the other end of the solder ball is connected. By detecting the change, it is possible to detect an abnormal state generated in the solder ball.

  Furthermore, a plurality of solder balls in the corner region form a daisy chain by the substrate forming the package and the receiving substrate of the package, and one end of the daisy chain is connected to the ground (GND) and the other end is connected to the current source, By detecting a change in potential between the one end and the other end, an abnormal state generated in the solder balls forming the daisy chain can be detected.

The BIOS (Basic Input / Output System) on the system side stores the acquired information in the memory and detects an abnormal state during POST (Power On Self Test) executed when the computer is turned on. An error display can be performed based on the history of abnormal conditions.
In addition, the system side can display an error by application software executed under the control of the OS when an abnormal state is acquired while the OS is operating.

    ADVANTAGE OF THE INVENTION According to this invention, the defect when a crack enters into a solder ball in the state where the package using solder balls, such as a BGA package and CSP, was mounted in the apparatus can be recognized well.

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.
[Embodiment 1]
FIG. 1 is a diagram showing an appearance of a computer apparatus 1 such as a notebook personal computer (notebook PC). Although this embodiment is applied to an electronic device typified by a notebook PC, the present embodiment is not necessarily limited to the notebook PC and can be applied to other electronic devices. In particular, it is suitable to be applied to an electronic device (such as a mobile phone, a PDA, or a portable DVD device) that is expected to generate a stress such as bending with a high frequency with respect to an interior board.

A computer apparatus 1 shown in FIG. 1 includes a base-side casing 2 that houses a system board, various boards, and peripheral devices on which main components (LSIs) are mounted, and a display panel-side casing 3 that is a lid. ing. The display panel side housing 3 is coupled to the base side housing 2 by a rotating shaft 4 and is configured to be openable and closable. The base side housing 2 is provided with a keyboard 5 on which the user performs key input, a track point 6 for moving the cursor, a click button 7 for designating an item designated by the cursor, and the like. . In addition, an LCD (Liquid Crystal Display) 8 as a display unit is embedded in a substantially central portion inside the display panel side housing 3. For example, antenna structures 9 for performing wireless communication are disposed on both sides of the outer peripheral side surface of the display panel 3.
The base side housing 2 incorporates various components such as a CPU and various system boards. Among these various components, there are those using devices (package substrates) connected by solder balls such as BGA (Ball Grid Array) packages and CSP (Chip Size Packages).

  FIG. 2 is a diagram illustrating a system configuration viewed from the hardware of the computer apparatus 1. The CPU 11 functions as the brain of the entire computer apparatus 1 and executes various programs under the control of the OS. The CPU 11 includes an FSB (Front Side Bus) 12 that is a system bus, a PCI (Peripheral Component Interconnect) bus 20 that is a high-speed I / O device bus, and an LPC (Low PC) that is an interface that replaces an ISA (Industrial Standard Architecture) bus. Pin Count) is interconnected with each component via a bus 40. Further, in order to compensate for the shortage of the capacity of the primary cache provided in the CPU 11, a secondary cache 14 may be placed via a BSB (Back Side Bus) 13 that is a dedicated bus.

  The FSB 12 and the PCI bus 20 are connected by a CPU bridge 15. The CPU bridge 15 includes a function for controlling an access operation to the main memory 16 and a data buffer for absorbing a difference in data transfer speed between the FSB 12 and the PCI bus 20. The main memory 16 is a writable memory used as an execution program reading area for the CPU 11 and a work area for writing processing data. This execution program includes firmware such as an OS, various drivers, various application programs (crack error detection software described later), and basic input / output system (BIOS). The video subsystem 17 processes a drawing command from the CPU 11 and outputs drawing information to the LCD 8.

The PCI bus 20 is connected to an I / O bridge 21, a card bus controller 22, an audio subsystem 25, a docking station interface (Dock I / F) 26, a mini PCI connector (slot) 27, and the like. The card bus controller 22 is a dedicated controller for directly connecting the bus signal of the PCI bus 20 to the card bus of the card bus slot 23, and a PC card 24 can be loaded into the card bus slot 23. The docking station interface 26 is used when connecting a function expansion device of the computer apparatus 1. The mini PCI connector 27 is connected to, for example, a mini PCI (mini PCI) card 28.
The I / O bridge 21 has a bridge function between the PCI bus 20 and the LPC bus 40. Further, a hard disk drive (HDD) 31, a CD-ROM drive 32, and a USB connector 30 are connected. Furthermore, an EEPROM 33 is connected to the I / O bridge 21 via an SM bus. A connector 47 is connected from the I / O bridge 21 via an AC 97 (Audio CODEC '97), an LCI (LAN Connect Interface), a USB, or the like, so that a communication card 48 can be connected. Further, the I / O bridge 21 is connected to a power supply circuit 29 that receives power supply from an AC adapter, a battery, or the like.

  An embedded controller (EC) 41, a flash ROM 44, and a Super I / O controller 45, which are sub CPUs, are connected to the LPC bus 40. The embedded controller 41 is responsible for a part of the power management function for the power circuit 29 and is connected to a gate array logic 42. An I / O port 46 is connected to the Super I / O controller 45. Further, an NVRAM (non-volatile RAM) 49 that holds BIOS settings executed by the CPU 11 is connected to the LPC bus 40. In the present embodiment, the embedded controller 41 notifies the BIOS of the detection result when the solder ball is cracked in an LSI using a device connected by a solder ball such as a BGA package or CSP. .

Next, detection of cracks in the solder ball, which is a characteristic configuration of the present embodiment, will be described.
FIG. 3 is a diagram showing a configuration example of the system board 50 having a mechanism for detecting cracks in the solder balls and the crack detection circuit 70. FIG. 4 is a cross-sectional view of a part of the system board 50 shown in FIG.

  The system board 50 includes a BGA package 51 shown in FIGS. 3 and 4 and a BGA receiving board 56 shown in FIG. In this BGA package 51, a plurality of solder balls 53 are arranged on the BGA substrate 52 at a minute interval. Solder balls 53 a, 53 b, 53 c, 53 d are arranged at four corners of the BGA substrate 52. A wiring pattern 57 connected to each of the solder balls 53a, 53b, 53c, and 53d is formed on the BGA receiving substrate 56 shown in FIG. On the other hand, as shown in FIG. 4, the BGA substrate 52 has a GND layer 54 formed therein. As shown in FIGS. 3 and 4, the BGA substrate 52 is formed with GND wiring 55 that connects the solder balls 53 a, 53 b, 53 c, 53 d at the corners to the GND layer 54.

The wiring patterns 57 extending from the four solder balls 53 a, 53 b, 53 c, 53 d in the corner portion are connected to the crack detection circuit 70. As shown in FIG. 3, the crack detection circuit 70 includes a potential measurement circuit 71, a selector circuit 75, and an OR circuit 76. The potential measurement circuit 71 is a circuit that measures the potential from GND for each of the solder balls 53a, 53b, 53c, and 53d. The potential measurement circuit 71 includes a pull-up (current source) 72 that supplies a potential of 3.3 V, for example, and a latch circuit 73 that holds the state when a potential change (edge) occurs. The pull-up 72 and the latch circuit 73 are provided in each of OUT1 to OUT4 which are the wiring patterns 57 from the solder balls 53a, 53b, 53c, and 53d, and four sets are provided in the example of FIG.
The OR circuit 76 interrupts the embedded controller 41 when any one of the latch circuits 73 operates. The selector circuit 75 is used when the embedded controller 41 recognizes which solder ball of the solder balls 53a, 53b, 53c, 53d has a crack failure.

  For example, when the system board 50 mounted on the computer apparatus 1 shown in FIG. 1 is not subjected to any stress, the current from the pull-up 72 is supplied to the GND layer 54 via the solder balls 53a, 53b, 53c, 53d. Flowing into. After that, when some kind of stress is applied to the system board 50 mounted on the computer apparatus 1 and a crack failure such as cracking or peeling occurs in at least one of the solder balls 53a, 53b, 53c, 53d, OUT1 to OUT4. A change occurs in the potential from. This potential change is held in the latch circuit 73. At this time, the OR circuit 76 outputs an interrupt signal (INT) to the embedded controller 41 in accordance with the operation of any one of the latch circuits 73. When the embedded controller 41 is interrupted by the OR circuit 76, the embedded controller 41 operates the selector circuit 75 to sequentially observe the state of the latch circuit 73 connected to OUT1 to OUT4. As a result, the embedded controller 41 can recognize where a failure has occurred at the four corners of the BGA package 51.

  Here, it is known that the cracks are large at the four corners in the package using the solder balls, and some conventional packages are purposely designed not to provide the solder balls at the four corners. In this embodiment, one of the four corners of the solder balls 53a, 53b, 53c, and 53d is connected to GND, and the potential is measured from the other of the corner portions that are generally difficult to use. In this way, simple wiring is simply applied to the solder balls 53a, 53b, 53c, 53d at the four corners, and the design burden is greatly reduced for the manufacturer who manufactures the system board 50. It is not necessary that the corners are complete four corners, and the same wiring may be connected to the solder balls 53 that are in a certain region of the corner portion and are not used for mounting to form a circuit. it can.

  Further, the latch state by the latch circuit 73 can be held until it is intentionally cleared. For example, the embedded controller 41 may be configured to arbitrarily reset after the problem part can be identified. For example, when the number of failures is to be accumulated, it is necessary to arbitrarily reset. For example, even when a failure such as a crack occurs in a part of the solder ball during use of the apparatus by the user, the user may continue to use it as “no problem”. In such a case, after the failure state is temporarily stored in the memory, the latch circuit 73 is reset, and the failure frequency is integrated according to the use state of the user by accumulating the number of failures. It becomes.

Next, processing by software will be described.
FIG. 5 is a flowchart showing the flow of crack detection processing by the embedded controller 41. First, when a crack occurs in at least one of the solder balls 53a, 53b, 53c, 53d in the BGA package 51 (step 101), the crack is detected by the crack detection circuit 70 (step 102). More specifically, the latch circuit 73 continues to monitor the high level output for the outputs (OUT1 to OUT4) of the respective pins. When any output becomes high level, it is latched that a crack has occurred, and the OR result is transmitted to the embedded controller 41 as an interrupt signal by the OR circuit 76. If no crack has occurred in step 101, the processing in step 102 and the subsequent steps is not performed, and the processing ends as it is. When the occurrence of a crack is detected via the OR circuit 76 of the crack detection circuit 70, the embedded controller 41 controls the selector circuit 75 of the crack detection circuit 70 to determine which latch circuit 73 is causing the interrupt. By investigating, the location of the crack is specified (step 103). The embedded controller 41 holds the crack occurrence information in a predetermined memory (not shown) that it has (step 104). Then, the embedded controller 41 notifies the BIOS 93 of SMI / SCI (step 105), and the process ends.

Next, processing when a crack error occurs will be described.
FIG. 6 is a functional diagram for executing software processing when a crack error occurs during OS operation. Here, as software functions, an OS 91 that is basic software that is executed by the CPU 11 shown in FIG. 2 and manages the entire computer apparatus 1 and a crack error detection that is application software executed under the control of the OS 91. Software 92 and BIOS 93 that controls various devices connected to the computer apparatus 1 are shown. The crack error detection software 92 is executed to display an error when the OS 91 is in operation and notify the user that a crack error has occurred.

  When the crack is detected by the crack detection circuit 70, the embedded controller 41 notifies the BIOS 93 of SMI (System Management Interrupt) / SCI (System Control Interrupt). The BIOS 93 notifies the crack error detection software 92 of the occurrence of a crack, and writes the crack occurrence information in the NVRAM 49. As the crack occurrence information written in the NVRAM 49, it is possible to store information relating to the time when the crack occurred in addition to information relating to the occurrence location (location) of the crack.

  FIG. 7 is a flowchart showing the flow of processing when a crack error occurs during OS operation. First, when a crack occurs in at least one of the solder balls 53a, 53b, 53c, 53d in the BGA package 51 (step 201), the crack is detected by the crack detection circuit 70 (step 202). If no crack is generated in step 201, the processing in step 202 and the subsequent steps is not performed, and the processing ends as it is. When the occurrence of a crack is detected via the OR circuit 76 of the crack detection circuit 70, the embedded controller (EC) 41 controls the selector circuit 75 of the crack detection circuit 70 to identify the crack location and SMI / SCI is notified (step 203). The BIOS 93 that has received the SMI / SCI reads crack location information from the embedded controller 41 (step 204). Further, the BIOS 93 writes crack occurrence information (crack location information, date) in the NVRAM 49 from the read location information (step 205). Further, the BIOS 93 informs the crack error detection software 92 of the occurrence of the crack (step 206). The crack error detection software 92 that has been notified of the occurrence of a crack notifies the OS 91 of the occurrence of an error (step 207). In addition, the crack error detection software 92 displays an error on the LCD 8 shown in FIGS. 1 and 2 (step 208), and the process ends.

Next, processing when a crack error is recognized during POST (Power On Self Test) will be described. Here, POST is a test of each device that is automatically executed when the computer apparatus 1 is powered on.
FIG. 8 is a functional diagram of software that executes crack error processing during POST. Since the OS is not operating during POST, the OS 91 and the crack error detection software 92 shown in FIG. 6 are not shown in the functional diagram shown in FIG.
When a crack is detected by the crack detection circuit 70, the embedded controller 41 notifies the BIOS 93 of SMI / SCI, and displays a crack error by the BIOS 93. Further, the BIOS 93 writes crack occurrence information in the NVRAM 49 and reads the crack occurrence information from the NVRAM 49 as necessary for history display or the like.

  FIG. 9 is a flowchart showing the flow of crack error processing executed by the BIOS 93 during POST. First, when the CPU 11 is powered on at the start-up of the system, the BIOS 93 confirms the crack occurrence status from the embedded controller (EC) 41 (step 301). When information indicating that a crack has occurred is obtained (step 302), the BIOS 93 reads crack location information from the embedded controller (EC) 41 (step 303). Also, the BIOS 93 writes crack occurrence information (crack location information, date) in the NVRAM 49 (step 304). Then, a POST error is displayed on the LCD 8 by the BIOS 93 (step 305).

  On the other hand, if information indicating that a crack has occurred is not obtained in step 302, the BIOS 93 reads crack occurrence information from the NVRAM 49 (step 306). If there is information on the occurrence history of cracks in the NVRAM 49 (step 307), the process proceeds to step 305, and a POST error is displayed on the LCD 8 by the BIOS 93. On the other hand, if it is determined in step 307 that there is no information on the history of occurrence of cracks, normal boot is executed by the BIOS 93, the OS 91 is read from the HDD 31 into the memory, and the computer apparatus 1 is operable. become.

  As described above, according to the present embodiment, when an abnormal state occurs such as when the solder ball 53 is cracked in the BGA / CSP device used for the mounted system board 50 or the like. In addition, it is possible to quickly detect the phenomenon electrically and notify the user that a malfunction occurs. Further, according to the present embodiment, it is possible not only to detect the occurrence of a crack, but also to specify the location of the crack. As a result, it is possible to easily verify the defect, and to significantly reduce the verification time and analysis time. In the first embodiment, the example of the BGA package 51 has been described. However, the present invention can be similarly applied to a CSP. Further, in the example shown in FIG. 3, one end of the solder balls 53a, 53b, 53c, 53d at the four corners is connected to the GND layer 54. It is also possible. That is, when GND is used as a power source and pull-up is used as a pull-down, an abnormality can be detected by a falling edge latch. Also, since the polarity is reversed, it is necessary to reverse the polarity when using an OR circuit.

[Embodiment 2]
In the first embodiment, not only the occurrence of a crack is detected, but also the location of the crack can be specified. In the second embodiment, the location of a crack cannot be specified, but the system side is characterized by simply detecting the occurrence of a crack and notifying the user. In addition, the same code | symbol is used about the function similar to Embodiment 1, The detailed description is abbreviate | omitted here.

FIGS. 10A to 10C are views for explaining a solder ball crack detection method according to the second embodiment. In the system board 60 shown in FIG. 10A, the solder balls 53 at the corners to be detected by the BGA package 51 constitute a daisy chain by mounting. This daisy chain is formed by the substrate design on the BGA package 51 shown in FIG. 10B and the wiring 66 on the BGA receiving substrate 65 side shown in FIG. In the board design on the BGA package 51, the solder balls 53 at the four corners (corresponding to 53a to 53d shown in FIG. 3) and the solder balls 53 at the corner portions (constant areas) adjacent thereto are wired 61. Connected with and shorted. One side (IN side) of the daisy chain is connected to the next BGA package 51 having a similar structure adjacent to GND. The other side (OUT side) is connected to the embedded controller 41 by a wiring 81. A pull-up 82, which is a current source, is connected to the wiring 81, and a latch 83 for holding the OUT-side state is provided in the embedded controller 41 ahead of the wiring 81. In addition, a voltage detection function (not shown) is provided. The embedded controller 41 further includes software for transmission to the system side and recording in the NVRAM 49 or the like.
The IN side may be connected to a power source. However, in this case, pull-down instead of pull-up, and the latch becomes a falling edge.

  Here, if the IN side is connected to GND, the LOW level continues to be output from the OUT side. However, when a crack occurs in the solder ball 53 in the middle of the daisy chain, the output level becomes High due to the current source (pull-up 82) connected to the OUT side. The embedded controller 41 detects this change and transmits it to the system (for example, the BIOS 93 shown in FIG. 8) to inform the user that an unstable operation situation due to hardware (H / W) occurs. it can. The embedded controller 41 records that the occurrence of a crack is detected directly in the NVRAM 49 such as a flash memory or via the BIOS 93 or the like. This makes it possible to know later the initial state of crack generation that is difficult to reproduce.

  As described above in detail, according to the present embodiment (Embodiment 1 and / or Embodiment 2), a package using a solder ball such as a BGA package or CSP is used for a notebook personal computer or the like. An abnormal state such as a crack generated in a solder ball can be well recognized when mounted on various electronic devices (devices). Further, it is possible to identify an abnormal portion such as a crack with respect to an abnormal state generated in the solder ball during mounting on an electronic device. Furthermore, the crack status can be stored in a memory and used as a history for defects caused by cracks in the solder balls when mounted on an electronic device. Furthermore, it is possible to detect failure early and shorten the solution time in an operating state of an electronic device on which a package using solder balls is mounted.

  The present invention can be applied to computer devices such as notebook PCs and desktop PCs, various electronic devices, and the like.

1 is a diagram illustrating an appearance of a computer device such as a notebook personal computer (notebook PC). It is the figure which showed the system configuration seen from the hardware of the computer apparatus. It is the figure which showed the example of a structure of the system board | substrate which has a mechanism for the crack detection of a solder ball, and a crack detection circuit. It is the figure which showed the cross section about a part of system board | substrate shown in FIG. It is a flowchart which shows the flow of the crack detection process by an embedded controller. FIG. 6 is a functional diagram for executing software processing when a crack error occurs during OS operation. It is the flowchart which showed the flow of the process when the error of a crack arises at the time of OS operation. FIG. 3 is a functional diagram of software that executes crack error processing at the time of POST. It is the flowchart which showed the flow of the process of the crack error performed by BIOS at the time of POST. (a)-(c) is a figure for demonstrating the crack detection method of the solder ball in Embodiment 2. FIG. It is a figure for demonstrating the method of connecting the conventional solder ball in chain shape.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Computer apparatus, 8 ... LCD (liquid crystal display device), 11 ... CPU, 41 ... Embedded controller, 49 ... NVRAM (non-volatile RAM), 50 ... System board, 51 ... BGA package, 52 ... BGA board, 53 ... Solder balls, 54 ... GND layer, 55 ... GND wiring, 56 ... BGA receiving substrate, 57 ... wiring pattern, 60 ... system substrate, 61 ... wiring, 70 ... crack detection circuit, 71 ... potential measurement circuit, 72 ... pull-up, 73 ... Latch circuit, 75 ... Selector circuit, 76 ... OR circuit, 91 ... OS, 92 ... Crack error detection software, 93 ... BIOS

Claims (6)

An electronic device on which a package having solder balls is mounted,
A circuit for monitoring a state of a plurality of solder balls selected from the solder balls and identifying a solder ball in which an abnormality has occurred from the plurality of solder balls;
Look including a conductive member for connecting the respective said circuit of said plurality of solder balls,
The electronic device according to claim 1, wherein the circuit includes a latch circuit that holds a state when a potential change occurs with respect to the solder ball.   The circuit includes an OR circuit that detects that there is an abnormality in at least one of the plurality of solder balls, and an abnormal location individually based on an instruction from the system side that controls the electronic device. The electronic device according to claim 1, further comprising a selector circuit for detecting The electronic device according to claim 1, wherein the plurality of solder balls are connected to a ground (GND) layer included in the package. An electronic device on which a system board formed by a package in which solder balls are arranged and a receiving board of the package is mounted,
Wiring connected to solder balls in corner areas of the package;
A circuit connected to the wiring and monitoring the state of the solder ball in the corner region;
A CPU connected to the circuit and recognizing an abnormality of the solder ball;
Look including a memory for storing information relating to anomalies that is recognized by the CPU,
In the wiring, a plurality of solder balls in the corner region form a daisy chain by the receiving substrate and the substrate forming the package.
The circuit detects from the output level of the system board that a crack has occurred in any of the plurality of solder balls forming the daisy chain,
The CPU identifies an abnormal solder ball from the circuit,
The electronic device is characterized in that the memory stores information of the identified solder ball as a history. An abnormal state detection method for detecting an abnormality occurring in the solder ball in an electronic device in which a package using a solder ball is mounted,
Detecting an abnormal state generated in the solder ball in the corner area of the package using a detection circuit,
The detected abnormal state is transmitted from the detection circuit to the system controlling the electronic device,
On the system side, information on the detected abnormal state is stored in a memory ,
One end of the solder ball in the corner region is connected to ground (GND) and the other end is connected to a current source by the substrate forming the package and the receiving substrate of the package,
An abnormal state detection method, wherein an abnormal state generated in the solder ball is detected by detecting a change in potential between the one end and the other end of the solder ball. 6. The abnormal state detection method according to claim 5 , wherein the system side specifies the location of the solder ball in an abnormal state using the detection circuit.

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