JP2005043202A - Failure detection device and failure detection method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a failure detection device and a failure detection method capable of quickly dealing with a failure such as repairing of a failed part, etc., since not only the occurrence of a failure of a substrate or wiring conductor, but also the substrate or wiring conductor in failure can be specified. <P>SOLUTION: By CPUs 113, 122 mounted on the substrates (1)11, (2)12 respectively, whether a failure occurs in the substrates (1)11, (2)12 or a wiring conductor 14 between these substrates is inspected from the operating states of the substrates (1)11, (2)12 and the operating states of the wiring conductors 14 between the substrates. On the basis of these individual inspection result signals ins1_in, ins1_out, ins2_in, ins2_out, a substrate or wiring conductor whose failure occurs is specified by a CPU 133 mounted on a substrate (3)13, and the specified failed part is displayed on a failed part display section 16. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a failure detection device and a failure detection method, and more particularly, to a failure detection device and a failure detection method for detecting a failure occurring in each of a plurality of substrates mounted on the device and a failure occurring in wiring between the plurality of substrates. About.

  In the board mounted on the device, the IC mounted on the board or the pin of the passive element is in an open state, shorted, or the wiring pattern on the board is disconnected, Wiring failures such as disconnection of the wiring that electrically connects the substrates may occur. As a well-known method for detecting these board and wiring faults, a fault detection circuit for observing the interface unit is added, and the board faults are compared by comparing with normal data during operation. In general, there are known a method of detecting a failure and a method of inputting inspection data and inspecting a failure of the substrate from the output result.

  In addition to the wiring check for the entire device, only a partial wiring check between the device and optional equipment can be executed. An ASIC (Application Specific Integrated Circuit) equipped with data transfer means is provided, wiring between boards is checked, and a CPU (Central Processing Unit) that controls each part of the device diagnoses which wiring has failed. (For example, refer to Patent Document 1).

JP 2002-286781 A

  However, in the conventional well-known failure detection method, if a circuit for detecting a failure is added to each interface unit in order to increase the accuracy of failure detection, the scale of hardware added for inspection increases. There is a problem. Moreover, in the prior art described in Patent Document 1, only an abnormality in wiring is detected, and a failure such as a pin open or short of an IC or a passive element mounted on a substrate, or a wiring pattern on the substrate is disconnected. When a substrate failure occurs, there is a problem that the failed substrate cannot be specified.

  In order to solve the above-described problem, in the present invention, in detecting a failure occurring in each of the plurality of substrates and a failure occurring in wiring between the plurality of substrates in an apparatus having a plurality of substrates mounted thereon, Inspecting whether or not a failure has occurred in the plurality of substrates or the wiring from the operation state of the substrate and the operation state of the wiring between the plurality of substrates, and each inspection of the operation state of the substrate and the operation state of the wiring Based on the result, a configuration is adopted in which a board or wiring in which a failure has occurred is specified.

  By using the inspection results of the operation state of the substrate and the operation state of the wiring, it is possible not only to detect that a failure has occurred in the substrate or wiring, but also to identify the substrate or wiring in which the failure has occurred.

  According to the present invention, not only the occurrence of a failure of a substrate or wiring, but also the substrate or wiring in which the failure has occurred can be identified, so that it is possible to quickly take measures such as repair of the failure location.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[First Embodiment]
FIG. 1 is a block diagram showing a hardware configuration example of a failure detection apparatus according to the first embodiment of the present invention. In the failure detection device according to the present embodiment, when a failure occurs in the device body during normal operation in a device body on which a plurality of substrates, for example, three substrates (1) 11 to (3) 13 are mounted, a failure occurs. The case where the substrate or the wiring between the substrates that caused the failure, that is, the wiring where the failure has occurred or the wiring between the substrates is specified will be described as an example.

  In FIG. 1, a substrate (1) 11 and a substrate (2) 12 are electrically connected via wirings 14 at respective interface portions 111 and 121. Further, the substrate (1) 11 and the substrate (3) 13 are electrically connected to each other through the wiring 15 at the interface portions 112 and 131, respectively. A failure location display unit 16 is connected to the interface unit 132 of the substrate (3) 13.

  The board (1) 11 includes a CPU 113 as an inspection unit that performs control for operating the apparatus main body and an inspection of a board failure and wiring failure, an ASIC 114 that performs control for operating the apparatus main body, and a CPU 113. And a memory 115 connected to the. In the substrate (1) 11, the ASIC 114 outputs an interface signal Sa1 such as a data signal or a control signal. The interface output signal Sa1 is transmitted to the substrate (2) 12 via the wiring 14 after passing through the interface unit 111, and also supplied to the CPU 113.

  The CPU 113 outputs an interface signal Sb1 such as a data signal or a control signal. The interface output signal Sb1 is transmitted to the substrate (2) 12 through the wiring 14 after passing through the interface unit 111 and also supplied to the CPU 113. The CPU 113 is further supplied with an interface input signal Sc1 such as a data signal or a control signal that is transmitted from the substrate (2) 12 through the wiring 14 and input via the interface unit 111.

  The CPU 113 compares the input interface output signal Sa1, the interface output signal Sb1, and the interface input signal Sc1 with the signal patterns in the normal state of these signals Sa1, Sb1, and Sc1, which are stored in advance in the memory 115, for example. Thus, whether or not a failure has occurred in the substrate (1) 11 or whether or not a failure has occurred in the wiring 14 between the substrate (2) 12 and the interface of the substrate (1) 11 is checked. The inspection result signal ins1_in of the input signal Sc1 and the inspection result signal ins1_out of the interface output signals Sa1 and Sb1 of the substrate (1) 11 are output.

  As in the case of the board (1) 11, the board (2) 12 has a control for operating the apparatus main body and a CPU 122 for inspecting the board or wiring, and a control for operating the apparatus main body. An ASIC 123 to perform and a memory 124 connected to the CPU 122 are mounted. In this board (2) 12, an interface input signal Sa 2 transmitted from the board (1) 11 through the wiring 14 and inputted via the interface unit 121 is supplied to the ASIC 123 and the CPU 122.

  Further, an interface input signal Sb2 transmitted from the board (1) 11 through the wiring 14 and input via the interface unit 121 is supplied to the CPU 122. The CPU 122 outputs an interface signal Sc2 such as a data signal or a control signal. The interface output signal Sc2 is transmitted to the substrate (1) 11 through the wiring 14 after passing through the interface unit 121 and also supplied to the CPU 122.

  The CPU 122 compares the input interface output signal Sa2, the interface output signal Sb2, and the interface input signal Sc2 with the signal patterns in the normal state of these signals Sa2, Sb2, and Sc2, which are stored in advance in the memory 124, for example. Thus, whether or not a failure has occurred in the substrate (2) 12 or whether or not a failure has occurred in the wiring 14 between the substrate (1) 11 and the interface of the substrate (2) 12 is checked. The inspection result signal ins2_in of the input signals Sa2 and Sb2 and the inspection result signal ins2_out of the interface output signal Sc2 of the substrate (2) 12 are output.

  The board (3) 13 is mounted with a CPU 133 as specifying means for specifying a board or wiring in which a failure has occurred, and a memory 134 connected to the CPU 133. In this board (3) 13, the inspection result signal ins1_in of the interface input signal and the inspection result signal ins1_out of the interface output signal from the board (1) 11 are transmitted to the CPU 133 through the wiring 15, and the board (2) 12 The test result signal ins2_in of the interface input signal and the test result signal ins2_out of the interface output signal are transmitted by the wiring 15 via the substrate (1) 11.

  When the failure occurs in the main body of the apparatus based on the inspection result signals ins1_in, ins1_out, ins2_in, and ins2_out, the CPU 133 determines whether the failure is caused by the board (1) 11 or not. Whether the substrate (2) 12 or the wiring 14 between these substrates is specified. Then, the specified result is given to the failure location display unit 16. In the failure location display unit 16, for example, in addition to the board number and the wiring number, the component number is displayed to indicate the failed component (failure location), and the failure content is also displayed. However, the display content mentioned here is only an example, and is not limited to these.

  Signal patterns in the normal state of the interface input / output signals Sa1, Sa2, Sb1, Sb2, Sc1, and Sc2 on the board (1) 11 and board (2) 12 are shown in the timing waveform diagram of FIG. The interface output signal Sa1 output from the ASIC 114 of the substrate (1) 11 is input to the ACIC 123 as the interface input signal Sa2 to the substrate (2) 12. The interface output signal Sb1 output from the CPU 113 of the substrate (1) 11 is input to the CPU 122 as the interface input signal Sb2 to the substrate (2) 12, and then output from the CPU 122 as the interface output signal Sc2. 11 is input to the CPU 113 as an input signal Sc1.

  FIG. 3 is a flowchart illustrating an example of a processing procedure for detecting a board failure and a wiring failure. First, as failure inspection processing for each substrate, failure inspection processing on the substrate (1) 11 (step S11) and failure inspection processing on the substrate (2) 12 (step S12) are performed, and then the interface input signal Any one of the test result signal ins1_in, the interface output signal test result signal ins1_out, the interface input signal test result signal ins2_in, and the interface output signal test result signal ins2_out is logic “1” (hereinafter simply referred to as 1). Whether or not (step S13).

  If any of the interface input signal inspection result signal ins1_in, the interface output signal inspection result signal ins1_out, the interface input signal inspection result signal ins2_in, or the interface output signal inspection result signal ins2_out is 1, the fault location identification process ( Step S14) is performed, and a series of processes for detecting a board failure and a wiring failure is completed. The interface input signal test result signal ins1_in, the interface output signal test result signal ins1_out, the interface input signal test result signal ins2_in, and the interface output signal test result signal ins2_out are all logic “0” (hereinafter simply referred to as 0). In this case, since the state is normal, each of the failure inspection process (step S11) on the substrate (1) 11 and the failure inspection process (step S12) on the substrate (2) 12 is performed again.

  Subsequently, an example of specific processing of the failure inspection processing (step S11) on the substrate (1) 11, the failure inspection processing (step S12) on the substrate (2) 12 and the failure location identification processing (step S14) will be described. To do.

  First, a specific example of the failure inspection process on the substrate (1) 11 will be described with reference to the flowchart of FIG. This failure inspection process is executed according to a failure inspection program stored in the failure inspection CPU 113 mounted on the board (1) 11.

  First, the inspection result signal ins1_in of the interface input signal and the inspection result signal ins1_out of the interface output signal are set to 0 (step S21). Next, the interface input / output signal at the substrate (1) 11 is fetched for a certain period from a certain time (step S22). Next, for each interface output signal, the number of pulses within a certain period is compared with the number of pulses in a normal state (step S23). If it is not equal to the number of pulses in the normal state, the inspection result signal ins1_out is set to 1 (step S24), and the failure inspection processing on the substrate (1) 11 is ended.

  If it is equal to the number of pulses in the normal state, the number of pulses in a certain period is compared with the number of pulses in the normal state for each interface input signal (step S25). If it is not equal to the number of pulses in the normal state, the inspection result signal ins1_in is set to 1 (step S26), and the failure inspection processing on the substrate (1) 11 is ended. ins1_out and ins1_in = 1 are abnormal signals indicating that the signal pattern of the interface input / output signal does not match the signal pattern in the normal state. When the number of pulses of each interface output signal is equal to the number of pulses in a normal state and the number of pulses of each interface input signal is equal to the number of pulses in a normal state, no processing is performed as it is, that is, ins1_out, The failure inspection process on the substrate (1) 11 is terminated with ins1_in = 0. ins1_out and ins1_in = 0 are normal signals indicating that the signal pattern of the interface input / output signal matches the signal pattern in the normal state.

  Next, a specific example of failure inspection processing on the substrate (2) 12 will be described with reference to the flowchart of FIG. This failure inspection process is executed according to a failure inspection program stored in the failure inspection CPU 122 mounted on the board (2) 12.

  Similar to the failure inspection process on the board (1) 11, first, the inspection result signal ins2_in of the interface input signal and the inspection result signal ins2_out of the interface output signal are set to 0 (step S31). Next, the interface input / output signal at the substrate (2) 12 is fetched for a certain period from a certain time (step S32). Next, for each interface input signal, the number of pulses within a certain period is compared with the number of pulses in a normal state (step S33). If it is not equal to the number of pulses in the normal state, the inspection result signal ins2_in is set to 1 (step S34), and the failure inspection processing on the substrate (2) 12 is terminated.

  If it is equal to the number of pulses in the normal state, the number of pulses within a certain period is compared with the number of pulses in the normal state for each interface output signal (step S35). If it is not equal to the number of pulses in the normal state, the inspection result signal ins2_out is set to 1 (step S36), and the failure inspection processing on the substrate (2) 12 is ended. ins2_out and ins2_in = 1 are abnormal signals indicating that the signal pattern of the interface input / output signal does not match the signal pattern in the normal state. When the number of pulses of each interface input signal is equal to the number of pulses in the normal state and the number of pulses of each interface output signal is equal to the number of pulses in the normal state, no processing is performed as it is, that is, ins2_out, The failure inspection process on the substrate (2) 12 is terminated with ins2_in = 0. ins2_out and ins2_in = 0 are normal signals indicating that the signal pattern of the interface input / output signal matches the signal pattern in the normal state.

  Finally, a specific example of the failure location specifying process will be described with reference to the flowchart of FIG. This failure location specifying process is performed on a plurality of boards, in this example, the board (1) 11 to board (3) 13 according to a fault identification program stored in the CPU 133 mounted on the board (3) 13. Go in sequence order. First, it is determined whether or not the inspection result signal ins1_out of the interface output signal is 1 (step S41). If ins1_out = 1, that is, if a failure is detected in the interface output signal of the board (1) 11, it has occurred. The failure is identified as a failure of the substrate (1) 11 (step S42).

  If ins1_out = 0, it is determined whether or not the inspection result signal ins2_in of the interface input signal is 1 (step S43), and ins2_in = 1, that is, a failure is detected by the interface input signal of the board (2) 12. In this case, the fault that has occurred is identified as a wiring fault between the board (1) 11 and the board (2) 12 (step S44). If ins2_in = 0, it is determined whether or not the inspection result signal ins2_out of the interface output signal is 1 (step S45), and ins2_out = 1, that is, a failure is detected in the interface output signal of the board (2) 12. In this case, the failure that has occurred is identified as a failure of the substrate (2) 12 (step S46). If ins2_out = 0, the fault that has occurred is identified as a wiring fault between the board (1) 11 and the board (2) 12 (step S47). The identified failure location is displayed on the failure location display unit 16.

  Hereinafter, specific failure examples 1 to 3 will be described, and failure location specifying processing when a failure has occurred in the apparatus main body will be described below.

(Failure example 1)
FIG. 7 is a block diagram showing a failure location (marked with x in the figure) in failure example 1 in which the wiring pattern 116 that transmits the interface signal Sa1 output from the ASIC 114 of the board (1) 11 to the interface unit 111 is disconnected. is there. FIG. 8 shows signal patterns of the interface input / output signals Sa1, Sa2, Sb1, Sb2, Sc1, and Sc2 in the failure example 1. When the wiring pattern 116 on the substrate (1) 11 is disconnected, the interface unit 111 has different operation states of the interface output signals Sa1 and Sa2 from the normal state, as is apparent from the comparison of the signal patterns in FIGS. .

  According to the board failure and wiring fault detection processing procedure of FIG. 3, first, in the fault inspection process (step S11) on the board (1) 11, the interface output signal inspection result signal ins1_out is set to 1, and the interface input signal inspection is performed. The result signal ins1_in is set to 0, and in the fault inspection process (step S12) in the board (2) 12, the inspection result signal ins2_in of the interface input signal is 1 and the inspection result signal ins2_out of the interface output signal is 0, respectively. Is set.

  Next, from the result of the fault inspection process (step S11) on the board (1) 11 and the result of the fault inspection process (step S12) on the board (2) 12, the fault location specifying process (step S14) Process to identify the location. In this failure location specifying process (step S14), since the inspection result signal ins1_out of the interface output signal is set to 1, in the flow chart of FIG. 6, it is determined that ins1_out = 1 (step S41), whereby the substrate (1 ) It can be specified that a failure has occurred in the substrate (1) 11 due to the disconnection of the wiring pattern 116 on the substrate 11 (step S42).

(Failure example 2)
FIG. 9 is a block diagram showing a failure location (marked with x in the drawing) in failure example 2 in which the signal line in the wiring 14 between the substrate (1) 11 and the substrate (2) 12 is disconnected. FIG. 10 shows signal patterns of the interface input / output signals Sa1, Sa2, Sb1, Sb2, Sc1, and Sc2 in the failure example 2. When the wiring 14 between the board (1) 11 and the board (2) 12 is disconnected, the interface units 111 and 121 receive each interface input / output signal as is apparent from the comparison of the signal patterns in FIGS. The operating status of Sb2, Sc1, and Sc2 is different from the normal status.

  According to the board failure and wiring fault detection procedure in FIG. 3, first, in the fault inspection process (step S11) on the board (1) 11, the interface output signal inspection result signal ins1_out is set to 0, and the interface input signal inspection is performed. The result signal ins1_in is set to 1, respectively. In the fault inspection process (step S12) in the board (2) 12, the inspection result signal ins2_in of the interface input signal is 1 and the inspection result signal ins2_out of the interface output signal is 0, respectively. Is set.

  Next, from the result of the fault inspection process (step S11) on the board (1) 11 and the result of the fault inspection process (step S12) on the board (2) 12, the fault location specifying process (step S14) Process to identify the location. In this fault location specifying process (step S14), the inspection result signal ins1_out of the interface output signal is set to 0 and the inspection result signal ins2_in of the interface input signal is set to 1, so ins1_out = 0 in the flowchart of FIG. By determining (step S41) and further determining that ins2_in = 1 (step S43), it can be identified that a disconnection has occurred in the wiring 14 between the substrate (1) 11 and the substrate (2) 12 (step S43). S44).

(Failure example 3)
FIG. 11 shows a failure location (marked with x in the figure) in failure example 3 in which an output pin (not shown) that outputs, for example, interface signal Sc2 of CPU 122 of substrate (2) 12 has failed due to, for example, solder failure. It is a block diagram. FIG. 12 shows signal patterns of the interface input / output signals Sa1, Sa2, Sb1, Sb2, Sc1, and Sc2 in the failure example 3. When the wiring pattern 125 on the substrate (2) 12 is disconnected, the interface units 111 and 121 have normal operation states of the interface input / output signals Sc1 and Sc2, as is apparent from the comparison of the signal patterns in FIGS. It is different from the state.

  According to the board failure and wiring fault detection procedure in FIG. 3, first, in the fault inspection process (step S11) on the board (1) 11, the interface output signal inspection result signal ins1_out is set to 0, and the interface input signal inspection is performed. The result signal ins1_in is set to 1, respectively. In the fault inspection process (step S12) in the board (2) 12, the inspection result signal ins2_in of the interface input signal is set to 0, and the inspection result signal ins2_out of the interface output signal is set to 1. Is set.

  Next, from the result of the fault inspection process (step S11) on the board (1) 11 and the result of the fault inspection process (step S12) on the board (2) 12, the fault location specifying process (step S14) Process to identify the location. In this fault location identification process (step S14), the inspection result signal ins1_out of the interface output signal and the inspection result signal ins2_in of the interface input signal are set to 0, and the inspection result signal ins2_out of the interface output signal is set to 1. In the flowchart of FIG. 6, it is determined that ins1_out = 0 (step S41), ins2_in = 1 is determined (step S43), and ins2_out = 1 is determined (step S45), whereby the output pin of the interface signal Sc2 of the CPU 122 is set. It can be specified that a failure has occurred (step S46).

  In the failure example 3, the case where the failure of the board (2) 12 is detected when the output pin of the CPU 122 fails due to, for example, a solder failure has been described as an example, but the interface output from the pin of the CPU 122 is described. A failure of the substrate (2) 12 when the wiring pattern 125 that transmits the output signal Sc2 to the interface unit 121 is disconnected can be detected in the same manner.

  In each of the above failure examples 1 to 3, only the disconnection failure of the wiring (including the failure of the input / output pin due to a soldering failure or the like) was taken up. However, the failure is not limited to the disconnection failure, the semiconductor integrated circuit such as the ASIC, the resistance Even when a passive element such as a failure occurs, it is possible to identify a failed substrate or a failed wiring by the substrate failure and wiring failure detection process of FIG.

  As described above, when the main unit fails during normal operation, it is checked whether a failure has occurred in multiple boards or wiring from the operational status of multiple boards and the operational status of wiring between multiple boards. By using each inspection result of these operating states, not only can the failure of the board or wiring be detected, but also the board or wiring in which the failure has occurred can be identified, so that repairs such as repairs can be quickly performed. It can be carried out.

  In particular, by comparing the signal pattern of the interface signal that passes through the interface part of the board with the signal pattern in the normal state, the interface part is inspected for the operation state of the board or the operation state of the wiring. Without adding hardware for inspection, it is possible to inspect the failure with a simple configuration because the failure of the substrate or wiring can be identified, and furthermore, the substrate or wiring where the failure has occurred can be identified. The failure location can be identified.

  Moreover, in the signal pattern comparison, a normal signal is output if the comparison results match, and an abnormal signal is output if they do not match, and the board or wiring in which the failure has occurred is identified from the combination of these normal signals and abnormal signals. Therefore, the substrate or the wiring can be specified easily and reliably.

  In the hardware configuration example according to the present embodiment, one signal line is wired for each inspection result signal and the inspection result signal is transmitted as a parallel signal. However, as shown in FIG. It is also possible to adopt a configuration in which the combination of the inspection result signals is converted into a pulse train signal and these inspection result signals are transmitted as serial signals (Modification 1). By adopting this configuration, it is possible to transmit a plurality of inspection result signals collectively through a single signal line, so that the wiring between the substrate (1) 11 and the substrate (3) 13 can be simplified. .

  In the present embodiment, the failure inspection CPU 113 mounted on the substrate (1) 11, the failure inspection CPU 122 mounted on the substrate (2) 12, and the failure substrate mounted on the substrate (3) 13. Alternatively, the CPU 133 for specifying the wiring is used separately for each processing, but as shown in FIG. 14, both the fault inspection program and the fault specifying program are included in the CPU 113 mounted on the board (1) 11. Is configured to detect a board failure or wiring failure by each of these programs, specify the failure location, and directly display the result of the failure location identification processing in the CPU 113 on the failure location display unit 16 It is also possible to adopt (Modification 2).

  In the present embodiment, the case where the CPU is mounted on all of the substrate (1) 11, the substrate (2) 12, and the substrate (3) 13 has been described as an example. However, as illustrated in FIG. ) 12 and the substrate (3) 13 are mounted with CPUs 122 and 133, while the substrate (1) 11 is mounted with an FPGA (Field Programmable Gate Array) 117, which is a rewritable gate array, and the FPGA 117 is mounted on the substrate (2). It is also possible to adopt a configuration in which control is performed by the CPU 122 mounted on 12) (Modification 3). Even in the case of adopting this configuration, it is possible to identify a failed board or a failed wiring by a similar method.

  Further, as shown in FIG. 16, the CPUs 122 and 133 are mounted on the substrate (2) 12 and the substrate (3) 13, while the ASIC 118 is mounted on the substrate (1) 11, and the ASIC 118 is mounted on the substrate (2) 12. It is also possible to adopt a configuration that is controlled by the CPU 122 mounted in (Modification 4). Even in the case of adopting this configuration, it is possible to identify a failed board or a failed wiring by a similar method.

[Second Embodiment]
FIG. 17 is a block diagram showing a hardware configuration example of a failure detection apparatus according to the second embodiment of the present invention, in which the same parts as those in FIG. In the failure detection device according to the present embodiment, when a failure occurs in the device body during normal operation in a device body on which a plurality of substrates, for example, three substrates (1) 11 to (3) 13 are mounted, a failure occurs. A case will be described as an example in which it is determined whether or not the cause of this is the wiring between the substrates and the faulty wiring is identified.

  The failure detection apparatus according to the present embodiment is almost the same as the failure detection apparatus according to the first embodiment in terms of hardware configuration, and is different from the substrate (1) 11 through the wiring 15 to the substrate (3). The only difference is that the inspection result signal transmitted to 13 is changed from the inspection result signals ins1_in, ins1_out, ins2_in and ins2_out of the interface input / output signals of the board to the inspection result signal ins12 of the wiring. This inspection result signal ins12 is output from the CPU 122 mounted on the board (2) 12, and transmitted from the board (2) 12 to the board (1) 11 via the wiring 14, and via the board (1) 11, the wiring is transmitted. 15 is transmitted to the substrate (3) 13.

  FIG. 18 is a flowchart showing the procedure of the wiring failure detection process. In the wiring failure detection process, first, the wiring inspection result signal ins12 is set to 0 (step S51). Next, the CPU 113 of the substrate (1) 11 generates inspection data from input / output pins (not shown) of the interface input / output signals Sa1, Sb1, and Sc1 (step S52). Next, the CPU 122 of the substrate (2) 12 observes inspection data input to input / output pins (not shown) of the interface input / output signals Sa2, Sb2, and Sc2 (step S53). Next, it is determined whether or not the observation result matches the data generated in step S52 (step S54). If they match, the wiring is determined to be normal (step S55). If the observation result does not match the data generated in step S52, the inspection result signal ins12 is set to 1 and the wiring is determined to be faulty (step S56).

  FIG. 19 shows signal patterns of the interface input / output signals Sa1, Sa2, Sb1, Sb2, Sc1, and Sc2 when the wiring is in the normal state in the failure detection apparatus according to the present embodiment. The inspection data output from the CPU 113 of the substrate (1) 11 is output from the substrate (1) 11 through the wiring pattern that transmits the interface input / output signals Sa1, Sb1, and Sc1, and then the substrate (2 ) 12 and input to the CPU 122 as interface input / output signals Sa2, Sb2, and Sc2, respectively.

  Here, a procedure for detecting a wiring failure when the signal line between Sb1 and Sb2 in the wiring 14 between the board (1) 11 and the board (2) 12 is disconnected and a failure occurs in the apparatus main body. This will be described below.

  FIG. 20 is a block diagram showing a failure location (marked with x in the figure) when the signal line between Sb1 and Sb2 in the wiring 14 between the board (1) 11 and the board (2) 12 is disconnected. FIG. 21 shows the operation states of the interface input / output signals Sa1, Sa2, Sb1, Sb2, Sc1, and Sc2 in this failure example. When the signal line between Sb1 and Sb2 is disconnected, in the interface unit 121, the operation state of the interface input signal Sb2 is different from the normal state, as is apparent from the comparison of the signal patterns in FIGS.

  According to the wiring failure detection processing procedure of FIG. 18, first, the CPU 113 of the board (1) 11 generates inspection data from the input / output pins (not shown) of the interface input / output signals Sa1, Sb1, and Sc1 (step S52). ). Next, the CPU 122 of the substrate (2) 12 observes inspection data input to input / output pins (not shown) of the interface input / output signals Sa2, Sb2, and Sc2 (step S53). As a result of the observation, if the waveform Sb1 indicating the inspection data generated by the CPU 113 of the substrate (1) 11 and the waveform Sb2 input to the CPU 122 of the substrate (2) 12 do not match (step S54), the signal line being wired It can be determined that the wiring has failed due to disconnection.

  As described above, when the apparatus main body fails during normal operation, inspection data is transferred from one of the two substrates to the other substrate through the wiring between the two substrates among the plurality of substrates. Transmit and observe the inspection data on the other board, and check whether or not a failure has occurred in the wiring between one board and the other board based on the observation result. By identifying the wiring where the failure occurred among the wiring between the boards, it is possible to identify the wiring where the failure occurred and the wiring where the failure occurred without adding hardware for inspection to the interface section. Therefore, the failure can be inspected with a simple configuration and the failure location can be specified.

  In the present embodiment, the case where the signal line disconnected in one wiring 14 is specified has been described. For example, the wiring between the substrate (1) and the substrate (2), the substrate (2) and the substrate (3), .., Ins (n-1), in the plurality of wirings such as wiring between the substrate (n-1) and the substrate (n). ) (n), and the wiring when ins (i-1) (i) is 1 is determined to be faulty, it becomes possible to identify the faulty wiring.

It is a block diagram which shows the hardware structural example of the failure detection apparatus which concerns on 1st Embodiment of this invention. It is a timing waveform diagram showing a signal pattern in a normal state of interface input / output signals. It is a flowchart which shows an example of the procedure of a detection process of a board | substrate failure and a wiring failure. It is a flowchart which shows an example of the specific procedure of the failure inspection process in a board | substrate (1). It is a flowchart which shows an example of the specific procedure of the failure inspection process in a board | substrate (2). It is a flowchart which shows an example of the specific procedure of a failure location identification process. It is a block diagram which shows the failure location in the failure example 1. FIG. FIG. 6 is a timing waveform diagram showing signal patterns of interface input / output signals in failure example 1; It is a block diagram which shows the failure location in the example 2 of a failure. FIG. 10 is a timing waveform diagram showing signal patterns of interface input / output signals in failure example 2. It is a block diagram which shows the failure location in the example 3 of a failure. It is a timing waveform diagram which shows the signal pattern of the interface input / output signal in the failure example 3. It is a block diagram which shows the hardware structural example of the failure detection apparatus which concerns on the modification 1 of 1st Embodiment. It is a block diagram which shows the hardware structural example of the failure detection apparatus which concerns on the modification 2 of 1st Embodiment. It is a block diagram which shows the hardware structural example of the failure detection apparatus which concerns on the modification 3 of 1st Embodiment. It is a block diagram which shows the hardware structural example of the failure detection apparatus which concerns on the modification 4 of 1st Embodiment. It is a block diagram which shows the hardware structural example of the failure detection apparatus which concerns on 2nd Embodiment of this invention. It is a flowchart which shows the procedure of the detection process of wiring failure. It is a timing waveform diagram showing a signal pattern of the interface input / output signal when the wiring is in a normal state. It is a block diagram which shows the failure location in the wiring between board | substrates. It is a timing waveform diagram showing a signal pattern of an interface input / output signal in a failure example in wiring between boards.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Board | substrate (1), 12 ... Board | substrate (2), 13 ... Board | substrate (3), 14, 15 ... Inter-substrate wiring, 113, 122, 133 ... CPU, 114, 123, ... ASIC, 115, 124, 134 ... memory,

Claims (6)

In a device equipped with a plurality of substrates, a failure detection device that detects a failure that occurs in each of the plurality of substrates and a failure that occurs in wiring between the plurality of substrates,
Inspection means for inspecting whether or not a failure has occurred in the plurality of substrates or the wiring from the operation state of the plurality of substrates and the operation state of the wiring between the plurality of substrates;
A failure detection apparatus comprising: a specifying unit that specifies a substrate or a wiring in which a failure has occurred based on each inspection result of the operation state of the substrate and the operation state of the wiring by the inspection unit. The inspection unit inspects an operation state of the substrate or an operation state of the wiring by comparing a signal pattern of an interface signal passing through the interface unit of the substrate with a signal pattern in a normal state. Item 5. A failure detection apparatus according to item 1. The inspection means outputs a normal signal if the comparison result matches, and an abnormal signal if the result does not match,
The failure detection apparatus according to claim 2, wherein the specifying unit specifies a substrate or a wiring in which a failure has occurred from a combination of the normal signal and the abnormal signal. In a device equipped with a plurality of substrates, a failure detection device that detects a failure that occurs in the wiring between the plurality of substrates,
Inspection data is transmitted from one of the two substrates to the other of the two substrates through the wiring between the two substrates of the plurality of substrates, and the inspection data is transmitted to the other substrate An inspection means for inspecting whether or not a failure has occurred in the wiring between the one substrate and the other substrate from the observation results,
A failure detection apparatus comprising: a specifying unit that specifies a wiring in which a failure has occurred among the wirings between the plurality of substrates based on an inspection result of the inspection unit. In a device equipped with a plurality of substrates, a failure detection method for detecting failures occurring in each of the plurality of substrates and failures occurring in wiring between the plurality of substrates,
Inspecting whether or not a failure has occurred in the plurality of substrates or the wiring from the operation state of the plurality of substrates and the operation state of the wiring between the plurality of substrates,
A failure detection method comprising: identifying a substrate or a wiring in which a failure has occurred based on each inspection result of the operation state of the substrate and the operation state of the wiring. In a device equipped with a plurality of substrates, a failure detection method for detecting a failure that occurs in the wiring between the plurality of substrates,
Inspection data is transmitted from one of the two substrates to the other of the two substrates through the wiring between the two substrates of the plurality of substrates, and the inspection data is transmitted to the other substrate And inspecting whether or not a failure has occurred in the wiring between the one substrate and the other substrate from this observation result,
A failure detection method comprising: identifying a wiring in which a failure has occurred among the wirings between the plurality of substrates based on the inspection result.

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