JP2009069036A - Printed circuit board failure analysis system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the failure analysis accuracy of a printed circuit board having an analog input/output function and a digital input/output function, even when using a simple test device. <P>SOLUTION: An AI terminal 6 of a failure printed circuit board 2 is connected to an AO terminal 9 of a non-defective printed circuit board 3 via an AI/O cable 14. An AO terminal 7 of the defective printed circuit board 2 is connected to an AI terminal 8 of the non-defective printed circuit board 3 via an AI/O cable 15. A DI terminal 10 of the defective printed circuit board 2 is connected to a DO terminal 13 of the non-defective printed circuit board 3 via a DI/O cable 17. A DO terminal 11 of the failure printed circuit board 2 is connected to a DI terminal 12 of the good printed circuit board 3 via a DI/O cable 16. A failure analysis control part 1 sends transmission data to the defective printed circuit board 2 and the non-defective printed circuit board 3, and performs defective analysis of the defective printed circuit board 2, based on the response from the defective printed circuit board 2 and the non-defective printed circuit board 3 to the transmission data. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a printed circuit board failure analysis system, and in particular, applied to a method for failure analysis of a printed circuit board having an analog input / output function and a digital input / output function while comparing the operations of a defective printed circuit board and a non-defective printed circuit board. Is preferred.

  Examples of failure modes of printed circuit boards on which electronic components such as ICs including microprocessors are mounted include malfunctions due to internal failures of electronic components such as ICs, failure of input / output units, and contact failures due to poor soldering. is there. As a method for detecting a faulty part of such a printed circuit board, there are a method using an in-circuit tester, a method for performing visual inspection, a method for causing a microprocessor mounted on the printed circuit board to execute a self-diagnosis function, and the like.

In addition, using a dedicated test device, a specific signal set in advance is input to an inspection point, and a signal pattern output corresponding thereto is compared with a normal signal pattern to detect defective parts. There is also a method.
Further, in such a method, in order to reduce the cost of the test apparatus, the number of pulses at a specific inspection point of the defective printed circuit board and the non-defective printed circuit board is counted, or the signal level is measured and determined in advance. There has been proposed a method of extracting a fault location by evaluating a difference from the level (Patent Document 1).
JP 2002-181892 A

However, in the method of comparing the number of pulses and voltage values measured from a defective printed circuit board with a non-defective printed circuit board, for example, a circuit applied to an industrial device having a function of generating a pulse by an input signal from a sensor. As described above, there is a problem that it is difficult to set a clear criterion for those affected by the external state.
In particular, in the method of judging the digital value converted by the A / D converter circuit based on the number of pulses and the signal level, a carry or a carry occurs at the time of digital conversion due to an error in the input signal from the outside, and the bit pattern changes greatly. Therefore, it is difficult to set a judgment standard.

In addition, it is difficult to detect a failure in a register inside a microprocessor and a memory inside and outside the microprocessor by a method of judging a digital value by the number of pulses or a signal level. The signal line inside the microprocessor cannot be observed from the outside, and the memory data on the external bus becomes indefinite during the change from “0” → “1” or “1” → “0”. The number of pulses cannot be determined accurately.
Therefore, an object of the present invention is to provide a printed circuit board failure analysis system capable of improving the failure analysis accuracy of a printed circuit board having an analog input / output function and a digital input / output function even when a simple test apparatus is used. Is to provide.

  In order to solve the above-described problem, according to the defect analysis system for a printed circuit board according to claim 1, the external signal input unit of the failure analysis target printed circuit board and the external signal output unit of the non-defective printed circuit board are connected to each other, A connection means for connecting the external signal output unit of the defect analysis target printed circuit board and the external signal input unit of the non-defective print circuit board to each other; and transmission data to the defect analysis target print circuit board and the non-defective print circuit board. And a failure analysis control unit that performs failure analysis of the failure analysis target printed circuit board based on responses from the failure analysis target printed circuit board and the non-defective printed circuit board.

  According to the printed circuit board failure analysis system of claim 2, an analog input unit and a digital input unit are provided as the external signal input unit, and an analog output unit and a digital output unit are provided as the external signal output unit. The connection means connects the analog input part of the printed circuit board subject to failure analysis to the analog output part of the printed circuit board, and connects the digital input part of the printed circuit board subject to failure analysis to the digital output part of the printed circuit board. The analog output unit of the target printed circuit board is connected to the analog input unit of the non-defective printed circuit board, and the digital output unit of the defect analysis target printed circuit board is connected to the digital input unit of the non-defective printed circuit board.

  According to the printed circuit board failure analysis system according to claim 3, the failure analysis target printed circuit board and the non-defective printed circuit board are provided with a microprocessor and transmission control means for receiving the transmission data, and the failure analysis is performed. The control unit sends the transmission data to the failure analysis target printed circuit board and the non-defective printed circuit board so that the microprocessor executes the failure analysis operation of the failure analysis target printed circuit board and the non-defective printed circuit board in synchronization. The failure analysis of the failure analysis target printed circuit board is performed based on the failure analysis result.

  According to the printed circuit board failure analysis system according to claim 4, the failure analysis control unit sends a test program to the failure analysis target printed circuit board and the non-defective printed circuit board. The failure analysis of the failure analysis target printed circuit board is performed by executing the test program on a non-defective printed circuit board.

  In the printed circuit board failure analysis system according to claim 5, the failure analysis control unit operates the failure analysis target printed circuit board and the non-defective printed circuit board in synchronization with the transmission data, and the failure analysis is performed. If there is a difference in the analog input / output values of the target printed circuit board, it is determined that there is a failure in the analog input portion of the printed circuit board subject to failure analysis. If there is a difference in the analog input / output values of the non-defective printed circuit board, the failure analysis is performed. It is determined that there is a failure in the analog output unit of the target printed circuit board, and if there is a difference in the digital input / output value of the printed circuit board for failure analysis, it is determined that there is a failure in the digital input unit of the printed circuit board for failure analysis, If there is a difference in the digital input / output values of the non-defective printed circuit board, it is determined that there is a failure in the digital output unit of the printed circuit board subject to failure analysis. And features.

  As described above, according to the present invention, the external signal input unit and the external signal output unit are connected to each other by connecting the defect analysis target printed circuit board and the external signal input / output unit of the non-defective printed circuit board to each other. Failure analysis of the printed circuit board subject to failure analysis can be performed without being connected to each other on the board, and the failure of the external signal input unit and the external signal output unit can be identified. For this reason, it is possible to accurately inspect the analog input / output function and the digital input / output function without using a highly functional test apparatus, and improve the defect analysis accuracy while suppressing the cost increase of the test apparatus. be able to.

Hereinafter, a printed circuit board failure analysis system according to an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a perspective view showing a schematic configuration of a printed circuit board failure analysis system according to an embodiment of the present invention.
In FIG. 1, a defective printed circuit board 2 is mounted with a connector 5a, an AI terminal 6, an AO terminal 7, a DI terminal 10, a DO terminal 11, and an electronic component 18 such as an IC including a microprocessor. .
On the non-defective printed circuit board 3, a connector 5b, an AI terminal 8, an AO terminal 9, a DI terminal 12, and a DO terminal 13 are mounted, and an electronic component 19 such as an IC including a microprocessor is mounted.

  The AI terminal 6 of the defective printed circuit board 2 is connected to the AO terminal 9 of the non-defective printed circuit board 3 through the AI / O cable 14, and the AO terminal 7 of the defective printed circuit board 2 is connected through the AI / O cable 15. The DI terminal 10 of the defective printed board 3 is connected to the AI terminal 8 of the non-defective printed board 3 and the DI terminal 10 of the defective printed board 2 is connected to the DO terminal 13 of the non-defective printed board 3 via the DI / O cable 17. Is connected to the DI terminal 12 of the non-defective printed circuit board 3 via the DI / O cable 16.

The transmission line 4a is connected to the connector 5a of the defective printed circuit board 2. The defective printed circuit board is connected to the failure analysis control unit 1 through the transmission line 4a and transmitted to the connector 5b of the non-defective printed circuit board 3. The line 4b is connected, and the non-defective printed circuit board 3 is connected to the failure analysis control unit 1 through the transmission line 4b.
Here, the failure analysis control unit 1 sends transmission data to the defective printed board 2 and the non-defective printed board 3, and based on the responses from the defective printed board 2 and the non-defective printed board 3 to the transmission data, the defective printed board 2. Failure analysis can be performed.

Then, the failure analysis control unit 1 sends transmission data to the defective printed circuit board 2 and the non-defective printed circuit board 3 through the transmission lines 4a and 4b, respectively. The analog data output from the AO terminal 7 of the defective printed circuit board 2 is input to the AI terminal 8 of the non-defective printed circuit board 3 via the AI / O cable 15. The digital data output from the DO terminal 11 of the defective printed circuit board 2 is input to the DI terminal 12 of the non-defective printed circuit board 3 via the DI / O cable 16. The analog data output from the AO terminal 9 of the non-defective printed circuit board 3 is input to the AI terminal 6 of the defective printed circuit board 2 through the AI / O cable 14. The digital data output from the DO terminal 13 of the non-defective printed circuit board 3 is input to the DI terminal 10 of the defective printed circuit board 2 via the DI / O cable 17. Then, the failure analysis control unit 1 performs failure analysis of the defective printed circuit board 2 based on the response to the transmission data sent to the defective printed circuit board 2 and the non-defective printed circuit board 3.
Here, the defective printed circuit board 2 and the non-defective printed circuit board 3 can have the same configuration. The defective printed circuit board 2 and the non-defective printed circuit board 3 include a microprocessor and a failure analysis control unit 1 that control the entire circuit board. The transmission control means for transmitting and receiving transmission data between each can be mounted.

FIG. 2 is a block diagram illustrating a schematic configuration of a printed circuit board that is a target of failure analysis according to an embodiment of the present invention.
2, the defective printed board 2 and the non-defective printed board 3 are provided with a transmission driver 23 for transmitting / receiving transmission data to / from the failure analysis control unit 1, a transmission control IC 21 for controlling transmission of transmission data, and control of the entire board. Microprocessor 20 to perform, dual port memory 22 to store data, DO IC 24 to output digital data, AO IC 25 to output analog data, DI IC 26 to input digital data, analog data input An AI IC 27 is provided. The microprocessor 20, the transmission control IC 21, the dual port memory 22, the DO IC 24, the AO IC 25, the DI IC 26, and the AI IC 27 are connected via the data / address bus 28, and the transmission control IC 21 and the dual port. The memory 22 is connected via a data / address bus 29, and the microprocessor 20 and the transmission control IC 21 are connected via an interrupt signal line 30.

  Then, the transmission data sent to the defective printed circuit board 2 and the non-defective printed circuit board 3 through the transmission lines 4 a and 4 b are input to the transmission control IC 21 through the transmission driver 23. Then, the transmission control IC 21 gives an interrupt signal to the microprocessor 20 via the interrupt signal line 30 in accordance with the reception timing of the transmission data. The microprocessor 20 performs a digital output operation to the DO IC 24, an analog output operation to the AO IC 25, a digital input operation to the DI IC 26, and a digital input operation to the AI IC 27 in accordance with the interrupt signal. Do.

FIG. 3 is a diagram showing a schematic configuration of a transmission format at the time of failure analysis according to an embodiment of the present invention.
In FIG. 3, a flag pattern 41 having a specific pattern is incorporated in transmission data 40 sent via transmission lines 4a and 4b. Then, the transmission control IC 21 detects the flag pattern 41 to generate a flag detection signal 42. Here, the transmission control IC 21 can make the generation timing of the flag detection signal 42 and the interrupt signal supplied to the microprocessor 20 completely equal or have a certain time difference.

  Then, the failure analysis control unit 1 simultaneously sends transmission data to the defective printed circuit board 2 and the non-defective printed circuit board 3, whereby the timings of the interrupt signals from the transmission control ICs 21 generated on the defective printed circuit board 2 and the non-defective printed circuit board 3 respectively. And the programs executed on the defective printed circuit board 2 and the non-defective printed circuit board 3 can be synchronized.

FIG. 4 is a flowchart showing a failure analysis process according to an embodiment of the present invention.
In FIG. 4, when executing failure analysis processing of a defective printed circuit board 2, the failure analysis control unit 1 performs CPU self-diagnosis test (T 1), memory test (T 2), communication test (T 3), and AI / O test (T 4). ), The DI / O test (T5) can be executed on the defective printed circuit board 2 and the non-defective printed circuit board 3.
If an abnormality occurs during the execution of these tests, the information can be sent to the failure analysis control unit 1 via the LED or the transmission path on the defective printed board 2 or the non-defective printed board 3 and displayed.
In the CPU self-diagnosis test (T1), register decoding (a), data storage (b), data operation (c), internal RAM test (d), and internal ROM test (e) are sequentially executed.

In register decoding, it is checked whether or not registers (for example, 16 registers R0 to R15) built in the microprocessor 20 are correctly selected.
For this reason, if the registers built in the microprocessor 20 are given an order and the order of R0 to R15 is given, the pattern A (10101010) is written to the register R0 and the pattern B (01010101) is given to the register R1. Write. Then, the contents of the registers R0 and R1 are read to check whether a correct value is read (step 1).

Next, the pattern A (10101010) is written to the registers R0 and R1, and the pattern B (01010101) is written to the register R2. Then, the contents of the registers R0, R1, and R2 are read to check whether a correct value is read (step 2).
After the above operation is repeated up to the register R15 (step 3), the pattern A (10101010) and the pattern B (01010101) are exchanged, and then the same operation is repeated (step 4).
In the data storage in the CPU self-diagnostic test (T1) in FIG. 4, a test data pattern is written to the 16 individual registers R0 to R15 to check whether a correct value is read.

FIG. 5 is a diagram showing an example of a test data pattern used for failure analysis according to an embodiment of the present invention.
In FIG. 5, a code “wide Reed-Muller code” can be used as the test data pattern. By using this test data pattern, it is possible to detect a stack of each bit in the “0” state, a stack of each bit in the “1” state, and a short circuit with another bit line.

  In the data operation in the CPU self-diagnosis test (T1) in FIG. 4, it is checked whether the data operation instruction of the microprocessor 20 is correctly executed. Here, all instructions are tested in one address mode, and one instruction is tested in all address modes. In the test of the data operation instruction, all the flags affected by each instruction are set and reset. In this, it is possible to test including a conditional JMP instruction.

In the internal RAM test in the CPU self-diagnosis test (T1) in FIG. 4, the register decoding and data storage tests are applied to the internal RAM test, and the same inspection as that of the register decoding and data storage is performed.
In the internal ROM test in the CPU self-diagnosis test (T1) in FIG. 4, Check Sum 1 byte is stored at the last address of the ROM, and the validity of the ROM data is checked.

Details of the internal test of the microprocessor 20 are described in “D. Brahme and JA Abraham, Functional testing of microprocessors, IEEE Trans. Comput. C-33 (6) (June 1984) 475-485”. Has been.
Next, in the memory test (T2), a test similar to the internal memory of the microprocessor 20 is performed.

Next, in the communication test (T3), the test data pattern of FIG. 5 is sent from the failure analysis control unit 1 to the defective printed circuit board 2, and the return data for the received data received by the defective printed circuit board 2 is tested.
Next, in the AI / O test (T4), analog data is simultaneously obtained from the defective printed circuit board 2 and the non-defective printed circuit board 3 in a resolution unit (for example, 1/1024 unit with respect to full scale if there is a 10-bit resolution). After the output, the defective printed circuit board 2 and the non-defective printed circuit board 3 input analog data, and sequentially inspect that the analog input / output value does not have a resolution of 1 unit. Since the operations of the defective printed circuit board 2 and the non-defective printed circuit board 3 are synchronized by the transmission data from the failure analysis control unit 1, accurate simultaneous processing can be performed.

Here, if a difference of 1 unit or more in resolution is detected in the analog input / output value on the defective printed circuit board 2, it can be determined that the AI IC 27 of the defective printed circuit board 2 has a failure. Further, if a non-defective printed circuit board 3 detects a difference of 1 unit or more in resolution between analog input and output values, it can be determined that the AO IC 25 of the defective printed circuit board 2 has a failure.
Next, in the DI / O test (T5), after simultaneously outputting digital data from the defective printed circuit board 2 and the non-defective printed circuit board 3, the own defective printed circuit board 2 and the non-defective printed circuit board 3 input the digital data, and the digital input Sequentially check that there is no difference in output value.
Here, if a difference in the digital input / output values is detected on the defective printed circuit board 2, it can be determined that the DI IC 26 of the defective printed circuit board 2 has a failure. If a difference in digital input / output values is detected on the non-defective printed circuit board 3, it can be determined that the DO IC 24 of the defective printed circuit board 2 has a failure.

As a result, failure analysis of the defective printed circuit board 2 can be performed without connecting the AI terminal 6 and the AO terminal 7 on the defective printed circuit board 2, and the failure of the AO IC 25 and the AI IC 27 can be identified. In addition, failure analysis of the defective printed circuit board 2 can be performed without connecting the DI terminal 10 and the DO terminal 11 on the defective printed circuit board 2, and the failure of the DO IC 24 and the DI IC 26 can be identified. It becomes possible. For this reason, it is possible to accurately inspect the analog input / output function and the digital input / output function without using a highly functional test apparatus, and improve the defect analysis accuracy while suppressing the cost increase of the test apparatus. be able to.
In addition, the defective printed circuit board 2 and the non-defective printed circuit board 3 can be operated while being accurately synchronized, and it is necessary to secure an extra waiting time in consideration of the processing time difference between the defective printed circuit board 2 and the non-compliant printed circuit board 3. This eliminates the test time.

FIG. 6 is a diagram showing a data transmission sequence at the time of failure analysis according to an embodiment of the present invention.
In FIG. 6, the failure analysis control unit 1 simultaneously transmits a failure analysis sequence start command of FIG. 4 to the defective printed circuit board 2 and the non-defective printed circuit board 3 through the transmission lines 4a and 4b, respectively. The defective printed circuit board 2 and the non-defective printed circuit board 3 detect the flag pattern 41 from the transmission data 40, and simultaneously execute the failure analysis sequence while synchronizing them, and the execution results are transmitted through the transmission lines 4a and 4b, respectively. Return to the failure analysis control unit 1. The failure analysis control unit 1 can determine the inspection result in the corresponding failure analysis sequence from the return data from the defective printed circuit board 2 and the non-defective printed circuit board 3 and the time taken for the return.

For example, the failure analysis control unit 1 transmits simultaneously the step 1 command of register decoding (a) in the CPU self-diagnosis test (T1) of FIG. 4 to the defective printed circuit board 2 and the non-defective printed circuit board 3 as transmission data A1 and A2. The defective printed circuit board 2 and the non-defective printed circuit board 3 can return the return data B1 and B2 to the failure analysis control unit 1, respectively.
Next, the failure analysis control unit 1 simultaneously transmits to the defective printed board 2 and the non-defective printed board 3 as transmission data A3 and A4, a step 2 command for register decoding (a) in the CPU self-diagnosis test (T1) in FIG. The defective printed circuit board 2 and the non-defective printed circuit board 3 can return the return data B3 and B4 to the failure analysis control unit 1, respectively.

Next, the failure analysis control unit 1 simultaneously transmits the transmission data A5 and A6 to the defective printed circuit board 2 and the non-defective printed circuit board 3 in the memory test, respectively, and when there is a difference in the return time of the return data B5 and B6, It can be determined that there is a failure in the memory.
Further, the failure analysis control unit 1 simultaneously transmits the transmission data A7 and A8 to the defective printed circuit board 2 and the non-defective printed circuit board 3, respectively, and when there is no response from the defective printed circuit board 2, there is a failure at the test location. It can be judged.

1 is a perspective view illustrating a schematic configuration of a printed circuit board failure analysis system according to an embodiment of the present invention. It is a block diagram which shows schematic structure of the printed circuit board used as the object of the defect analysis which concerns on one Embodiment of this invention. It is a figure which shows schematic structure of the transmission format at the time of the failure analysis which concerns on one Embodiment of this invention. It is a flowchart which shows the defect analysis process which concerns on one Embodiment of this invention. It is a figure which shows an example of the test data pattern used for the failure analysis which concerns on one Embodiment of this invention. It is a figure which shows the data transmission sequence at the time of the defect analysis which concerns on one Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Failure analysis control part 2 Defective printed circuit board 3 Non-defective printed circuit board 4a, 4b Transmission line 5a, 5b Connector 6, 8 AI terminal 7, 9 AO terminal 10, 12 DI terminal 11, 13 DO terminal 14, 15 AI / O cable 16 , 17 DI / O cable 18, 19 Electronic component 21 Transmission control IC
22 Dual Port Memory 23 Transmission Driver 24 IC for DO
25 IC for AO
26 IC for DI
27 IC for AI
28, 29 Data / address bus 30 Interrupt signal line

Claims (5)

The external signal input unit of the printed circuit board for failure analysis and the external signal output unit of the non-defective printed circuit board are connected to each other, and the external signal output unit of the printed circuit board for failure analysis and the external signal input unit of the non-defective printed circuit board are connected to each other. Connection means;
Transmission data is sent to the defect analysis target printed circuit board and the non-defective print board, and failure analysis of the defect analysis target print circuit board is performed based on responses from the defect analysis target print circuit board and the non-defective print circuit board to the transmission data. A failure analysis system for a printed circuit board, comprising: a failure analysis control unit that performs the failure analysis control. An analog input unit and a digital input unit are provided as the external signal input unit, and an analog output unit and a digital output unit are provided as the external signal output unit,
The connection means connects the analog input part of the printed circuit board for failure analysis to the analog output part of the non-defective printed circuit board, connects the digital input part of the printed circuit board for failure analysis to the digital output part of the printed circuit board for defective analysis, 2. The printed circuit board according to claim 1, wherein an analog output section of the printed circuit board is connected to an analog input section of the non-defective printed circuit board, and a digital output section of the printed circuit board subject to failure analysis is connected to the digital input section of the non-defective printed circuit board. Failure analysis system. The defect analysis target printed circuit board and the non-defective printed circuit board are provided with a microprocessor and a transmission control means for receiving the transmission data,
The failure analysis control unit sends the transmission data to the failure analysis target printed circuit board and the non-defective printed circuit board, thereby synchronizing the failure analysis operations of the failure analysis target printed circuit board and the non-defective printed circuit board. 3. The printed circuit board failure analysis system according to claim 1, wherein the failure analysis is performed on the failure analysis target printed circuit board based on the failure analysis result.   The failure analysis control unit sends a test program to the printed circuit board for failure analysis and the non-defective printed circuit board, and causes the failure analysis to be executed on the printed circuit board for failure analysis and the printed circuit board for non-defective product. The failure analysis system for a printed circuit board according to claim 3, wherein failure analysis of the target printed circuit board is performed.   The failure analysis control unit operates the failure analysis target printed circuit board and the non-defective printed circuit board in synchronization with the transmission data, and if there is a difference in analog input / output values of the failure analysis target printed circuit board, the failure analysis is performed. It is determined that there is a failure in the analog input part of the target printed circuit board, and if there is a difference in the analog input / output values of the non-defective printed circuit board, it is determined that there is a failure in the analog output part of the printed circuit board subject to failure analysis, and the defect If there is a difference in the digital input / output values of the analysis target printed circuit board, it is determined that there is a failure in the digital input part of the failure analysis target printed circuit board. 3. The printed circuit board failure analysis system according to claim 2, wherein the failure is detected in the digital output unit of the analysis target printed circuit board.

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